2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_uniform.h"
27 #include "main/context.h"
28 #include "main/macros.h"
29 #include "program/prog_parameter.h"
30 #include "program/sampler.h"
35 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
36 enum opcode opcode
, dst_reg dst
,
37 src_reg src0
, src_reg src1
, src_reg src2
)
39 this->opcode
= opcode
;
44 this->ir
= v
->base_ir
;
45 this->annotation
= v
->current_annotation
;
49 vec4_visitor::emit(vec4_instruction
*inst
)
51 this->instructions
.push_tail(inst
);
57 vec4_visitor::emit_before(vec4_instruction
*inst
, vec4_instruction
*new_inst
)
59 new_inst
->ir
= inst
->ir
;
60 new_inst
->annotation
= inst
->annotation
;
62 inst
->insert_before(new_inst
);
68 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
69 src_reg src0
, src_reg src1
, src_reg src2
)
71 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
77 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
79 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
83 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
85 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
89 vec4_visitor::emit(enum opcode opcode
)
91 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
96 vec4_visitor::op(dst_reg dst, src_reg src0) \
98 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
104 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \
106 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
131 /** Gen4 predicated IF. */
133 vec4_visitor::IF(uint32_t predicate
)
135 vec4_instruction
*inst
;
137 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
138 inst
->predicate
= predicate
;
143 /** Gen6+ IF with embedded comparison. */
145 vec4_visitor::IF(src_reg src0
, src_reg src1
, uint32_t condition
)
147 assert(intel
->gen
>= 6);
149 vec4_instruction
*inst
;
151 resolve_ud_negate(&src0
);
152 resolve_ud_negate(&src1
);
154 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
156 inst
->conditional_mod
= condition
;
162 * CMP: Sets the low bit of the destination channels with the result
163 * of the comparison, while the upper bits are undefined, and updates
164 * the flag register with the packed 16 bits of the result.
167 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
, uint32_t condition
)
169 vec4_instruction
*inst
;
171 /* original gen4 does type conversion to the destination type
172 * before before comparison, producing garbage results for floating
175 if (intel
->gen
== 4) {
176 dst
.type
= src0
.type
;
177 if (dst
.file
== HW_REG
)
178 dst
.fixed_hw_reg
.type
= dst
.type
;
181 resolve_ud_negate(&src0
);
182 resolve_ud_negate(&src1
);
184 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
, src0
, src1
);
185 inst
->conditional_mod
= condition
;
191 vec4_visitor::SCRATCH_READ(dst_reg dst
, src_reg index
)
193 vec4_instruction
*inst
;
195 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_READ
,
204 vec4_visitor::SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
)
206 vec4_instruction
*inst
;
208 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_WRITE
,
217 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
219 static enum opcode dot_opcodes
[] = {
220 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
223 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
227 vec4_visitor::fix_3src_operand(src_reg src
)
229 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
230 * able to use vertical stride of zero to replicate the vec4 uniform, like
232 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
234 * But you can't, since vertical stride is always four in three-source
235 * instructions. Instead, insert a MOV instruction to do the replication so
236 * that the three-source instruction can consume it.
239 /* The MOV is only needed if the source is a uniform or immediate. */
240 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
243 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
244 expanded
.type
= src
.type
;
245 emit(MOV(expanded
, src
));
246 return src_reg(expanded
);
250 vec4_visitor::fix_math_operand(src_reg src
)
252 /* The gen6 math instruction ignores the source modifiers --
253 * swizzle, abs, negate, and at least some parts of the register
254 * region description.
256 * Rather than trying to enumerate all these cases, *always* expand the
257 * operand to a temp GRF for gen6.
259 * For gen7, keep the operand as-is, except if immediate, which gen7 still
263 if (intel
->gen
== 7 && src
.file
!= IMM
)
266 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
267 expanded
.type
= src
.type
;
268 emit(MOV(expanded
, src
));
269 return src_reg(expanded
);
273 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
275 src
= fix_math_operand(src
);
277 if (dst
.writemask
!= WRITEMASK_XYZW
) {
278 /* The gen6 math instruction must be align1, so we can't do
281 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
283 emit(opcode
, temp_dst
, src
);
285 emit(MOV(dst
, src_reg(temp_dst
)));
287 emit(opcode
, dst
, src
);
292 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
294 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
300 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
303 case SHADER_OPCODE_RCP
:
304 case SHADER_OPCODE_RSQ
:
305 case SHADER_OPCODE_SQRT
:
306 case SHADER_OPCODE_EXP2
:
307 case SHADER_OPCODE_LOG2
:
308 case SHADER_OPCODE_SIN
:
309 case SHADER_OPCODE_COS
:
312 assert(!"not reached: bad math opcode");
316 if (intel
->gen
>= 6) {
317 return emit_math1_gen6(opcode
, dst
, src
);
319 return emit_math1_gen4(opcode
, dst
, src
);
324 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
325 dst_reg dst
, src_reg src0
, src_reg src1
)
327 src0
= fix_math_operand(src0
);
328 src1
= fix_math_operand(src1
);
330 if (dst
.writemask
!= WRITEMASK_XYZW
) {
331 /* The gen6 math instruction must be align1, so we can't do
334 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
335 temp_dst
.type
= dst
.type
;
337 emit(opcode
, temp_dst
, src0
, src1
);
339 emit(MOV(dst
, src_reg(temp_dst
)));
341 emit(opcode
, dst
, src0
, src1
);
346 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
347 dst_reg dst
, src_reg src0
, src_reg src1
)
349 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
355 vec4_visitor::emit_math(enum opcode opcode
,
356 dst_reg dst
, src_reg src0
, src_reg src1
)
359 case SHADER_OPCODE_POW
:
360 case SHADER_OPCODE_INT_QUOTIENT
:
361 case SHADER_OPCODE_INT_REMAINDER
:
364 assert(!"not reached: unsupported binary math opcode");
368 if (intel
->gen
>= 6) {
369 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
371 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
376 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
379 assert(!"ir_unop_pack_half_2x16 should be lowered");
381 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
382 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
384 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
386 * Because this instruction does not have a 16-bit floating-point type,
387 * the destination data type must be Word (W).
389 * The destination must be DWord-aligned and specify a horizontal stride
390 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
391 * each destination channel and the upper word is not modified.
393 * The above restriction implies that the f32to16 instruction must use
394 * align1 mode, because only in align1 mode is it possible to specify
395 * horizontal stride. We choose here to defy the hardware docs and emit
396 * align16 instructions.
398 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
399 * instructions. I was partially successful in that the code passed all
400 * tests. However, the code was dubiously correct and fragile, and the
401 * tests were not harsh enough to probe that frailty. Not trusting the
402 * code, I chose instead to remain in align16 mode in defiance of the hw
405 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
406 * simulator, emitting a f32to16 in align16 mode with UD as destination
407 * data type is safe. The behavior differs from that specified in the PRM
408 * in that the upper word of each destination channel is cleared to 0.
411 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
412 src_reg
tmp_src(tmp_dst
);
415 /* Verify the undocumented behavior on which the following instructions
416 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
417 * then the result of the bit-or instruction below will be incorrect.
419 * You should inspect the disasm output in order to verify that the MOV is
420 * not optimized away.
422 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
425 /* Give tmp the form below, where "." means untouched.
428 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
430 * That the upper word of each write-channel be 0 is required for the
431 * following bit-shift and bit-or instructions to work. Note that this
432 * relies on the undocumented hardware behavior mentioned above.
434 tmp_dst
.writemask
= WRITEMASK_XY
;
435 emit(F32TO16(tmp_dst
, src0
));
437 /* Give the write-channels of dst the form:
440 tmp_src
.swizzle
= SWIZZLE_Y
;
441 emit(SHL(dst
, tmp_src
, src_reg(16u)));
443 /* Finally, give the write-channels of dst the form of packHalf2x16's
447 tmp_src
.swizzle
= SWIZZLE_X
;
448 emit(OR(dst
, src_reg(dst
), tmp_src
));
452 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
455 assert(!"ir_unop_unpack_half_2x16 should be lowered");
457 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
458 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
460 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
462 * Because this instruction does not have a 16-bit floating-point type,
463 * the source data type must be Word (W). The destination type must be
466 * To use W as the source data type, we must adjust horizontal strides,
467 * which is only possible in align1 mode. All my [chadv] attempts at
468 * emitting align1 instructions for unpackHalf2x16 failed to pass the
469 * Piglit tests, so I gave up.
471 * I've verified that, on gen7 hardware and the simulator, it is safe to
472 * emit f16to32 in align16 mode with UD as source data type.
475 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
476 src_reg
tmp_src(tmp_dst
);
478 tmp_dst
.writemask
= WRITEMASK_X
;
479 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
481 tmp_dst
.writemask
= WRITEMASK_Y
;
482 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
484 dst
.writemask
= WRITEMASK_XY
;
485 emit(F16TO32(dst
, tmp_src
));
489 vec4_visitor::visit_instructions(const exec_list
*list
)
491 foreach_list(node
, list
) {
492 ir_instruction
*ir
= (ir_instruction
*)node
;
501 type_size(const struct glsl_type
*type
)
506 switch (type
->base_type
) {
509 case GLSL_TYPE_FLOAT
:
511 if (type
->is_matrix()) {
512 return type
->matrix_columns
;
514 /* Regardless of size of vector, it gets a vec4. This is bad
515 * packing for things like floats, but otherwise arrays become a
516 * mess. Hopefully a later pass over the code can pack scalars
517 * down if appropriate.
521 case GLSL_TYPE_ARRAY
:
522 assert(type
->length
> 0);
523 return type_size(type
->fields
.array
) * type
->length
;
524 case GLSL_TYPE_STRUCT
:
526 for (i
= 0; i
< type
->length
; i
++) {
527 size
+= type_size(type
->fields
.structure
[i
].type
);
530 case GLSL_TYPE_SAMPLER
:
531 /* Samplers take up one slot in UNIFORMS[], but they're baked in
536 case GLSL_TYPE_ERROR
:
537 case GLSL_TYPE_INTERFACE
:
546 vec4_visitor::virtual_grf_alloc(int size
)
548 if (virtual_grf_array_size
<= virtual_grf_count
) {
549 if (virtual_grf_array_size
== 0)
550 virtual_grf_array_size
= 16;
552 virtual_grf_array_size
*= 2;
553 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
554 virtual_grf_array_size
);
555 virtual_grf_reg_map
= reralloc(mem_ctx
, virtual_grf_reg_map
, int,
556 virtual_grf_array_size
);
558 virtual_grf_reg_map
[virtual_grf_count
] = virtual_grf_reg_count
;
559 virtual_grf_reg_count
+= size
;
560 virtual_grf_sizes
[virtual_grf_count
] = size
;
561 return virtual_grf_count
++;
564 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
569 this->reg
= v
->virtual_grf_alloc(type_size(type
));
571 if (type
->is_array() || type
->is_record()) {
572 this->swizzle
= BRW_SWIZZLE_NOOP
;
574 this->swizzle
= swizzle_for_size(type
->vector_elements
);
577 this->type
= brw_type_for_base_type(type
);
580 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
585 this->reg
= v
->virtual_grf_alloc(type_size(type
));
587 if (type
->is_array() || type
->is_record()) {
588 this->writemask
= WRITEMASK_XYZW
;
590 this->writemask
= (1 << type
->vector_elements
) - 1;
593 this->type
= brw_type_for_base_type(type
);
596 /* Our support for uniforms is piggy-backed on the struct
597 * gl_fragment_program, because that's where the values actually
598 * get stored, rather than in some global gl_shader_program uniform
602 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
604 int namelen
= strlen(ir
->name
);
606 /* The data for our (non-builtin) uniforms is stored in a series of
607 * gl_uniform_driver_storage structs for each subcomponent that
608 * glGetUniformLocation() could name. We know it's been set up in the same
609 * order we'd walk the type, so walk the list of storage and find anything
610 * with our name, or the prefix of a component that starts with our name.
612 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
613 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
615 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
616 (storage
->name
[namelen
] != 0 &&
617 storage
->name
[namelen
] != '.' &&
618 storage
->name
[namelen
] != '[')) {
622 gl_constant_value
*components
= storage
->storage
;
623 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
624 storage
->type
->matrix_columns
);
626 for (unsigned s
= 0; s
< vector_count
; s
++) {
627 uniform_vector_size
[uniforms
] = storage
->type
->vector_elements
;
630 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
631 prog_data
->param
[uniforms
* 4 + i
] = &components
->f
;
635 static float zero
= 0;
636 prog_data
->param
[uniforms
* 4 + i
] = &zero
;
645 vec4_visitor::setup_uniform_clipplane_values()
647 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
649 if (intel
->gen
< 6) {
650 /* Pre-Gen6, we compact clip planes. For example, if the user
651 * enables just clip planes 0, 1, and 3, we will enable clip planes
652 * 0, 1, and 2 in the hardware, and we'll move clip plane 3 to clip
653 * plane 2. This simplifies the implementation of the Gen6 clip
656 int compacted_clipplane_index
= 0;
657 for (int i
= 0; i
< MAX_CLIP_PLANES
; ++i
) {
658 if (!(key
->userclip_planes_enabled_gen_4_5
& (1 << i
)))
661 this->uniform_vector_size
[this->uniforms
] = 4;
662 this->userplane
[compacted_clipplane_index
] = dst_reg(UNIFORM
, this->uniforms
);
663 this->userplane
[compacted_clipplane_index
].type
= BRW_REGISTER_TYPE_F
;
664 for (int j
= 0; j
< 4; ++j
) {
665 prog_data
->param
[this->uniforms
* 4 + j
] = &clip_planes
[i
][j
];
667 ++compacted_clipplane_index
;
671 /* In Gen6 and later, we don't compact clip planes, because this
672 * simplifies the implementation of gl_ClipDistance.
674 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
675 this->uniform_vector_size
[this->uniforms
] = 4;
676 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
677 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
678 for (int j
= 0; j
< 4; ++j
) {
679 prog_data
->param
[this->uniforms
* 4 + j
] = &clip_planes
[i
][j
];
686 /* Our support for builtin uniforms is even scarier than non-builtin.
687 * It sits on top of the PROG_STATE_VAR parameters that are
688 * automatically updated from GL context state.
691 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
693 const ir_state_slot
*const slots
= ir
->state_slots
;
694 assert(ir
->state_slots
!= NULL
);
696 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
697 /* This state reference has already been setup by ir_to_mesa,
698 * but we'll get the same index back here. We can reference
699 * ParameterValues directly, since unlike brw_fs.cpp, we never
700 * add new state references during compile.
702 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
703 (gl_state_index
*)slots
[i
].tokens
);
704 float *values
= &this->prog
->Parameters
->ParameterValues
[index
][0].f
;
706 this->uniform_vector_size
[this->uniforms
] = 0;
707 /* Add each of the unique swizzled channels of the element.
708 * This will end up matching the size of the glsl_type of this field.
711 for (unsigned int j
= 0; j
< 4; j
++) {
712 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
715 prog_data
->param
[this->uniforms
* 4 + j
] = &values
[swiz
];
716 if (swiz
<= last_swiz
)
717 this->uniform_vector_size
[this->uniforms
]++;
724 vec4_visitor::variable_storage(ir_variable
*var
)
726 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
730 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
)
732 ir_expression
*expr
= ir
->as_expression();
734 *predicate
= BRW_PREDICATE_NORMAL
;
738 vec4_instruction
*inst
;
740 assert(expr
->get_num_operands() <= 2);
741 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
742 expr
->operands
[i
]->accept(this);
743 op
[i
] = this->result
;
745 resolve_ud_negate(&op
[i
]);
748 switch (expr
->operation
) {
749 case ir_unop_logic_not
:
750 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
751 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
754 case ir_binop_logic_xor
:
755 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
756 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
759 case ir_binop_logic_or
:
760 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
761 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
764 case ir_binop_logic_and
:
765 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
766 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
770 if (intel
->gen
>= 6) {
771 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
773 inst
= emit(MOV(dst_null_f(), op
[0]));
774 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
779 if (intel
->gen
>= 6) {
780 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
782 inst
= emit(MOV(dst_null_d(), op
[0]));
783 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
787 case ir_binop_all_equal
:
788 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
789 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
792 case ir_binop_any_nequal
:
793 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
794 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
798 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
799 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
802 case ir_binop_greater
:
803 case ir_binop_gequal
:
805 case ir_binop_lequal
:
807 case ir_binop_nequal
:
808 emit(CMP(dst_null_d(), op
[0], op
[1],
809 brw_conditional_for_comparison(expr
->operation
)));
813 assert(!"not reached");
821 resolve_ud_negate(&this->result
);
823 if (intel
->gen
>= 6) {
824 vec4_instruction
*inst
= emit(AND(dst_null_d(),
825 this->result
, src_reg(1)));
826 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
828 vec4_instruction
*inst
= emit(MOV(dst_null_d(), this->result
));
829 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
834 * Emit a gen6 IF statement with the comparison folded into the IF
838 vec4_visitor::emit_if_gen6(ir_if
*ir
)
840 ir_expression
*expr
= ir
->condition
->as_expression();
846 assert(expr
->get_num_operands() <= 2);
847 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
848 expr
->operands
[i
]->accept(this);
849 op
[i
] = this->result
;
852 switch (expr
->operation
) {
853 case ir_unop_logic_not
:
854 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
857 case ir_binop_logic_xor
:
858 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
861 case ir_binop_logic_or
:
862 temp
= dst_reg(this, glsl_type::bool_type
);
863 emit(OR(temp
, op
[0], op
[1]));
864 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
867 case ir_binop_logic_and
:
868 temp
= dst_reg(this, glsl_type::bool_type
);
869 emit(AND(temp
, op
[0], op
[1]));
870 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
874 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
878 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
881 case ir_binop_greater
:
882 case ir_binop_gequal
:
884 case ir_binop_lequal
:
886 case ir_binop_nequal
:
887 emit(IF(op
[0], op
[1],
888 brw_conditional_for_comparison(expr
->operation
)));
891 case ir_binop_all_equal
:
892 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
893 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
896 case ir_binop_any_nequal
:
897 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
898 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
902 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
903 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
907 assert(!"not reached");
908 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
914 ir
->condition
->accept(this);
916 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
920 with_writemask(dst_reg
const & r
, int mask
)
923 result
.writemask
= mask
;
928 vec4_vs_visitor::emit_prolog()
930 dst_reg sign_recovery_shift
;
931 dst_reg normalize_factor
;
932 dst_reg es3_normalize_factor
;
934 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
935 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
936 uint8_t wa_flags
= vs_compile
->key
.gl_attrib_wa_flags
[i
];
937 dst_reg
reg(ATTR
, i
);
939 reg_d
.type
= BRW_REGISTER_TYPE_D
;
940 dst_reg reg_ud
= reg
;
941 reg_ud
.type
= BRW_REGISTER_TYPE_UD
;
943 /* Do GL_FIXED rescaling for GLES2.0. Our GL_FIXED attributes
944 * come in as floating point conversions of the integer values.
946 if (wa_flags
& BRW_ATTRIB_WA_COMPONENT_MASK
) {
948 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
949 dst
.writemask
= (1 << (wa_flags
& BRW_ATTRIB_WA_COMPONENT_MASK
)) - 1;
950 emit(MUL(dst
, src_reg(dst
), src_reg(1.0f
/ 65536.0f
)));
953 /* Do sign recovery for 2101010 formats if required. */
954 if (wa_flags
& BRW_ATTRIB_WA_SIGN
) {
955 if (sign_recovery_shift
.file
== BAD_FILE
) {
956 /* shift constant: <22,22,22,30> */
957 sign_recovery_shift
= dst_reg(this, glsl_type::uvec4_type
);
958 emit(MOV(with_writemask(sign_recovery_shift
, WRITEMASK_XYZ
), src_reg(22u)));
959 emit(MOV(with_writemask(sign_recovery_shift
, WRITEMASK_W
), src_reg(30u)));
962 emit(SHL(reg_ud
, src_reg(reg_ud
), src_reg(sign_recovery_shift
)));
963 emit(ASR(reg_d
, src_reg(reg_d
), src_reg(sign_recovery_shift
)));
966 /* Apply BGRA swizzle if required. */
967 if (wa_flags
& BRW_ATTRIB_WA_BGRA
) {
968 src_reg temp
= src_reg(reg
);
969 temp
.swizzle
= BRW_SWIZZLE4(2,1,0,3);
970 emit(MOV(reg
, temp
));
973 if (wa_flags
& BRW_ATTRIB_WA_NORMALIZE
) {
974 /* ES 3.0 has different rules for converting signed normalized
975 * fixed-point numbers than desktop GL.
977 if (_mesa_is_gles3(ctx
) && (wa_flags
& BRW_ATTRIB_WA_SIGN
)) {
978 /* According to equation 2.2 of the ES 3.0 specification,
979 * signed normalization conversion is done by:
981 * f = c / (2^(b-1)-1)
983 if (es3_normalize_factor
.file
== BAD_FILE
) {
984 /* mul constant: 1 / (2^(b-1) - 1) */
985 es3_normalize_factor
= dst_reg(this, glsl_type::vec4_type
);
986 emit(MOV(with_writemask(es3_normalize_factor
, WRITEMASK_XYZ
),
987 src_reg(1.0f
/ ((1<<9) - 1))));
988 emit(MOV(with_writemask(es3_normalize_factor
, WRITEMASK_W
),
989 src_reg(1.0f
/ ((1<<1) - 1))));
993 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
994 emit(MOV(dst
, src_reg(reg_d
)));
995 emit(MUL(dst
, src_reg(dst
), src_reg(es3_normalize_factor
)));
996 emit_minmax(BRW_CONDITIONAL_G
, dst
, src_reg(dst
), src_reg(-1.0f
));
998 /* The following equations are from the OpenGL 3.2 specification:
1000 * 2.1 unsigned normalization
1003 * 2.2 signed normalization
1004 * f = (2c+1)/(2^n-1)
1006 * Both of these share a common divisor, which is represented by
1007 * "normalize_factor" in the code below.
1009 if (normalize_factor
.file
== BAD_FILE
) {
1010 /* 1 / (2^b - 1) for b=<10,10,10,2> */
1011 normalize_factor
= dst_reg(this, glsl_type::vec4_type
);
1012 emit(MOV(with_writemask(normalize_factor
, WRITEMASK_XYZ
),
1013 src_reg(1.0f
/ ((1<<10) - 1))));
1014 emit(MOV(with_writemask(normalize_factor
, WRITEMASK_W
),
1015 src_reg(1.0f
/ ((1<<2) - 1))));
1019 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
1020 emit(MOV(dst
, src_reg((wa_flags
& BRW_ATTRIB_WA_SIGN
) ? reg_d
: reg_ud
)));
1022 /* For signed normalization, we want the numerator to be 2c+1. */
1023 if (wa_flags
& BRW_ATTRIB_WA_SIGN
) {
1024 emit(MUL(dst
, src_reg(dst
), src_reg(2.0f
)));
1025 emit(ADD(dst
, src_reg(dst
), src_reg(1.0f
)));
1028 emit(MUL(dst
, src_reg(dst
), src_reg(normalize_factor
)));
1032 if (wa_flags
& BRW_ATTRIB_WA_SCALE
) {
1034 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
1035 emit(MOV(dst
, src_reg((wa_flags
& BRW_ATTRIB_WA_SIGN
) ? reg_d
: reg_ud
)));
1043 vec4_vs_visitor::make_reg_for_system_value(ir_variable
*ir
)
1045 /* VertexID is stored by the VF as the last vertex element, but
1046 * we don't represent it with a flag in inputs_read, so we call
1047 * it VERT_ATTRIB_MAX, which setup_attributes() picks up on.
1049 dst_reg
*reg
= new(mem_ctx
) dst_reg(ATTR
, VERT_ATTRIB_MAX
);
1050 vs_prog_data
->uses_vertexid
= true;
1052 switch (ir
->location
) {
1053 case SYSTEM_VALUE_VERTEX_ID
:
1054 reg
->writemask
= WRITEMASK_X
;
1056 case SYSTEM_VALUE_INSTANCE_ID
:
1057 reg
->writemask
= WRITEMASK_Y
;
1060 assert(!"not reached");
1069 vec4_visitor::visit(ir_variable
*ir
)
1071 dst_reg
*reg
= NULL
;
1073 if (variable_storage(ir
))
1077 case ir_var_shader_in
:
1078 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->location
);
1081 case ir_var_shader_out
:
1082 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1084 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
1085 output_reg
[ir
->location
+ i
] = *reg
;
1086 output_reg
[ir
->location
+ i
].reg_offset
= i
;
1087 output_reg
[ir
->location
+ i
].type
=
1088 brw_type_for_base_type(ir
->type
->get_scalar_type());
1089 output_reg_annotation
[ir
->location
+ i
] = ir
->name
;
1094 case ir_var_temporary
:
1095 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1098 case ir_var_uniform
:
1099 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
1101 /* Thanks to the lower_ubo_reference pass, we will see only
1102 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
1103 * variables, so no need for them to be in variable_ht.
1105 if (ir
->is_in_uniform_block())
1108 /* Track how big the whole uniform variable is, in case we need to put a
1109 * copy of its data into pull constants for array access.
1111 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
1113 if (!strncmp(ir
->name
, "gl_", 3)) {
1114 setup_builtin_uniform_values(ir
);
1116 setup_uniform_values(ir
);
1120 case ir_var_system_value
:
1121 reg
= make_reg_for_system_value(ir
);
1125 assert(!"not reached");
1128 reg
->type
= brw_type_for_base_type(ir
->type
);
1129 hash_table_insert(this->variable_ht
, reg
, ir
);
1133 vec4_visitor::visit(ir_loop
*ir
)
1137 /* We don't want debugging output to print the whole body of the
1138 * loop as the annotation.
1140 this->base_ir
= NULL
;
1142 if (ir
->counter
!= NULL
) {
1143 this->base_ir
= ir
->counter
;
1144 ir
->counter
->accept(this);
1145 counter
= *(variable_storage(ir
->counter
));
1147 if (ir
->from
!= NULL
) {
1148 this->base_ir
= ir
->from
;
1149 ir
->from
->accept(this);
1151 emit(MOV(counter
, this->result
));
1155 emit(BRW_OPCODE_DO
);
1158 this->base_ir
= ir
->to
;
1159 ir
->to
->accept(this);
1161 emit(CMP(dst_null_d(), src_reg(counter
), this->result
,
1162 brw_conditional_for_comparison(ir
->cmp
)));
1164 vec4_instruction
*inst
= emit(BRW_OPCODE_BREAK
);
1165 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1168 visit_instructions(&ir
->body_instructions
);
1171 if (ir
->increment
) {
1172 this->base_ir
= ir
->increment
;
1173 ir
->increment
->accept(this);
1174 emit(ADD(counter
, src_reg(counter
), this->result
));
1177 emit(BRW_OPCODE_WHILE
);
1181 vec4_visitor::visit(ir_loop_jump
*ir
)
1184 case ir_loop_jump::jump_break
:
1185 emit(BRW_OPCODE_BREAK
);
1187 case ir_loop_jump::jump_continue
:
1188 emit(BRW_OPCODE_CONTINUE
);
1195 vec4_visitor::visit(ir_function_signature
*ir
)
1202 vec4_visitor::visit(ir_function
*ir
)
1204 /* Ignore function bodies other than main() -- we shouldn't see calls to
1205 * them since they should all be inlined.
1207 if (strcmp(ir
->name
, "main") == 0) {
1208 const ir_function_signature
*sig
;
1211 sig
= ir
->matching_signature(&empty
);
1215 visit_instructions(&sig
->body
);
1220 vec4_visitor::try_emit_sat(ir_expression
*ir
)
1222 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
1226 sat_src
->accept(this);
1227 src_reg src
= this->result
;
1229 this->result
= src_reg(this, ir
->type
);
1230 vec4_instruction
*inst
;
1231 inst
= emit(MOV(dst_reg(this->result
), src
));
1232 inst
->saturate
= true;
1238 vec4_visitor::emit_bool_comparison(unsigned int op
,
1239 dst_reg dst
, src_reg src0
, src_reg src1
)
1241 /* original gen4 does destination conversion before comparison. */
1243 dst
.type
= src0
.type
;
1245 emit(CMP(dst
, src0
, src1
, brw_conditional_for_comparison(op
)));
1247 dst
.type
= BRW_REGISTER_TYPE_D
;
1248 emit(AND(dst
, src_reg(dst
), src_reg(0x1)));
1252 vec4_visitor::emit_minmax(uint32_t conditionalmod
, dst_reg dst
,
1253 src_reg src0
, src_reg src1
)
1255 vec4_instruction
*inst
;
1257 if (intel
->gen
>= 6) {
1258 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1259 inst
->conditional_mod
= conditionalmod
;
1261 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1263 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1264 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1269 vec4_visitor::visit(ir_expression
*ir
)
1271 unsigned int operand
;
1272 src_reg op
[Elements(ir
->operands
)];
1275 vec4_instruction
*inst
;
1277 if (try_emit_sat(ir
))
1280 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1281 this->result
.file
= BAD_FILE
;
1282 ir
->operands
[operand
]->accept(this);
1283 if (this->result
.file
== BAD_FILE
) {
1284 printf("Failed to get tree for expression operand:\n");
1285 ir
->operands
[operand
]->print();
1288 op
[operand
] = this->result
;
1290 /* Matrix expression operands should have been broken down to vector
1291 * operations already.
1293 assert(!ir
->operands
[operand
]->type
->is_matrix());
1296 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1297 if (ir
->operands
[1]) {
1298 vector_elements
= MAX2(vector_elements
,
1299 ir
->operands
[1]->type
->vector_elements
);
1302 this->result
.file
= BAD_FILE
;
1304 /* Storage for our result. Ideally for an assignment we'd be using
1305 * the actual storage for the result here, instead.
1307 result_src
= src_reg(this, ir
->type
);
1308 /* convenience for the emit functions below. */
1309 result_dst
= dst_reg(result_src
);
1310 /* If nothing special happens, this is the result. */
1311 this->result
= result_src
;
1312 /* Limit writes to the channels that will be used by result_src later.
1313 * This does limit this temp's use as a temporary for multi-instruction
1316 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1318 switch (ir
->operation
) {
1319 case ir_unop_logic_not
:
1320 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
1321 * ones complement of the whole register, not just bit 0.
1323 emit(XOR(result_dst
, op
[0], src_reg(1)));
1326 op
[0].negate
= !op
[0].negate
;
1327 this->result
= op
[0];
1331 op
[0].negate
= false;
1332 this->result
= op
[0];
1336 emit(MOV(result_dst
, src_reg(0.0f
)));
1338 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_G
));
1339 inst
= emit(MOV(result_dst
, src_reg(1.0f
)));
1340 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1342 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_L
));
1343 inst
= emit(MOV(result_dst
, src_reg(-1.0f
)));
1344 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1349 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1353 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1356 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1360 assert(!"not reached: should be handled by ir_explog_to_explog2");
1363 case ir_unop_sin_reduced
:
1364 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1367 case ir_unop_cos_reduced
:
1368 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1373 assert(!"derivatives not valid in vertex shader");
1377 assert(!"not reached: should be handled by lower_noise");
1381 emit(ADD(result_dst
, op
[0], op
[1]));
1384 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1388 if (ir
->type
->is_integer()) {
1389 /* For integer multiplication, the MUL uses the low 16 bits
1390 * of one of the operands (src0 on gen6, src1 on gen7). The
1391 * MACH accumulates in the contribution of the upper 16 bits
1394 * FINISHME: Emit just the MUL if we know an operand is small
1397 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
1399 emit(MUL(acc
, op
[0], op
[1]));
1400 emit(MACH(dst_null_d(), op
[0], op
[1]));
1401 emit(MOV(result_dst
, src_reg(acc
)));
1403 emit(MUL(result_dst
, op
[0], op
[1]));
1407 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1408 assert(ir
->type
->is_integer());
1409 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1412 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1413 assert(ir
->type
->is_integer());
1414 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1418 case ir_binop_greater
:
1419 case ir_binop_lequal
:
1420 case ir_binop_gequal
:
1421 case ir_binop_equal
:
1422 case ir_binop_nequal
: {
1423 emit(CMP(result_dst
, op
[0], op
[1],
1424 brw_conditional_for_comparison(ir
->operation
)));
1425 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1429 case ir_binop_all_equal
:
1430 /* "==" operator producing a scalar boolean. */
1431 if (ir
->operands
[0]->type
->is_vector() ||
1432 ir
->operands
[1]->type
->is_vector()) {
1433 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1434 emit(MOV(result_dst
, src_reg(0)));
1435 inst
= emit(MOV(result_dst
, src_reg(1)));
1436 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1438 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1439 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1442 case ir_binop_any_nequal
:
1443 /* "!=" operator producing a scalar boolean. */
1444 if (ir
->operands
[0]->type
->is_vector() ||
1445 ir
->operands
[1]->type
->is_vector()) {
1446 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1448 emit(MOV(result_dst
, src_reg(0)));
1449 inst
= emit(MOV(result_dst
, src_reg(1)));
1450 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1452 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1453 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1458 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1459 emit(MOV(result_dst
, src_reg(0)));
1461 inst
= emit(MOV(result_dst
, src_reg(1)));
1462 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1465 case ir_binop_logic_xor
:
1466 emit(XOR(result_dst
, op
[0], op
[1]));
1469 case ir_binop_logic_or
:
1470 emit(OR(result_dst
, op
[0], op
[1]));
1473 case ir_binop_logic_and
:
1474 emit(AND(result_dst
, op
[0], op
[1]));
1478 assert(ir
->operands
[0]->type
->is_vector());
1479 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1480 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1484 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1487 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1490 case ir_unop_bitcast_i2f
:
1491 case ir_unop_bitcast_u2f
:
1492 this->result
= op
[0];
1493 this->result
.type
= BRW_REGISTER_TYPE_F
;
1496 case ir_unop_bitcast_f2i
:
1497 this->result
= op
[0];
1498 this->result
.type
= BRW_REGISTER_TYPE_D
;
1501 case ir_unop_bitcast_f2u
:
1502 this->result
= op
[0];
1503 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1514 emit(MOV(result_dst
, op
[0]));
1518 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1519 emit(AND(result_dst
, result_src
, src_reg(1)));
1524 emit(RNDZ(result_dst
, op
[0]));
1527 op
[0].negate
= !op
[0].negate
;
1528 inst
= emit(RNDD(result_dst
, op
[0]));
1529 this->result
.negate
= true;
1532 inst
= emit(RNDD(result_dst
, op
[0]));
1535 inst
= emit(FRC(result_dst
, op
[0]));
1537 case ir_unop_round_even
:
1538 emit(RNDE(result_dst
, op
[0]));
1542 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1545 emit_minmax(BRW_CONDITIONAL_G
, result_dst
, op
[0], op
[1]);
1549 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1552 case ir_unop_bit_not
:
1553 inst
= emit(NOT(result_dst
, op
[0]));
1555 case ir_binop_bit_and
:
1556 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1558 case ir_binop_bit_xor
:
1559 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1561 case ir_binop_bit_or
:
1562 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1565 case ir_binop_lshift
:
1566 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1569 case ir_binop_rshift
:
1570 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1571 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1573 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1576 case ir_binop_ubo_load
: {
1577 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
1578 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1579 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1580 src_reg offset
= op
[1];
1582 /* Now, load the vector from that offset. */
1583 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1585 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1586 packed_consts
.type
= result
.type
;
1587 src_reg surf_index
=
1588 src_reg(SURF_INDEX_VS_UBO(uniform_block
->value
.u
[0]));
1589 if (const_offset_ir
) {
1590 offset
= src_reg(const_offset
/ 16);
1592 emit(SHR(dst_reg(offset
), offset
, src_reg(4)));
1595 vec4_instruction
*pull
=
1596 emit(new(mem_ctx
) vec4_instruction(this,
1597 VS_OPCODE_PULL_CONSTANT_LOAD
,
1598 dst_reg(packed_consts
),
1601 pull
->base_mrf
= 14;
1604 packed_consts
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1605 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1606 const_offset
% 16 / 4,
1607 const_offset
% 16 / 4,
1608 const_offset
% 16 / 4);
1610 /* UBO bools are any nonzero int. We store bools as either 0 or 1. */
1611 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1612 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1613 BRW_CONDITIONAL_NZ
));
1614 emit(AND(result_dst
, result
, src_reg(0x1)));
1616 emit(MOV(result_dst
, packed_consts
));
1622 assert(!"not reached: should be handled by lrp_to_arith");
1625 case ir_quadop_vector
:
1626 assert(!"not reached: should be handled by lower_quadop_vector");
1629 case ir_unop_pack_half_2x16
:
1630 emit_pack_half_2x16(result_dst
, op
[0]);
1632 case ir_unop_unpack_half_2x16
:
1633 emit_unpack_half_2x16(result_dst
, op
[0]);
1635 case ir_unop_pack_snorm_2x16
:
1636 case ir_unop_pack_snorm_4x8
:
1637 case ir_unop_pack_unorm_2x16
:
1638 case ir_unop_pack_unorm_4x8
:
1639 case ir_unop_unpack_snorm_2x16
:
1640 case ir_unop_unpack_snorm_4x8
:
1641 case ir_unop_unpack_unorm_2x16
:
1642 case ir_unop_unpack_unorm_4x8
:
1643 assert(!"not reached: should be handled by lower_packing_builtins");
1645 case ir_unop_unpack_half_2x16_split_x
:
1646 case ir_unop_unpack_half_2x16_split_y
:
1647 case ir_binop_pack_half_2x16_split
:
1648 assert(!"not reached: should not occur in vertex shader");
1655 vec4_visitor::visit(ir_swizzle
*ir
)
1661 /* Note that this is only swizzles in expressions, not those on the left
1662 * hand side of an assignment, which do write masking. See ir_assignment
1666 ir
->val
->accept(this);
1668 assert(src
.file
!= BAD_FILE
);
1670 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1673 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1676 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1679 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1682 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1686 for (; i
< 4; i
++) {
1687 /* Replicate the last channel out. */
1688 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1691 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1697 vec4_visitor::visit(ir_dereference_variable
*ir
)
1699 const struct glsl_type
*type
= ir
->type
;
1700 dst_reg
*reg
= variable_storage(ir
->var
);
1703 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1704 this->result
= src_reg(brw_null_reg());
1708 this->result
= src_reg(*reg
);
1710 /* System values get their swizzle from the dst_reg writemask */
1711 if (ir
->var
->mode
== ir_var_system_value
)
1714 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1715 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1720 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
1722 /* Under normal circumstances array elements are stored consecutively, so
1723 * the stride is equal to the size of the array element.
1725 return type_size(ir
->type
);
1730 vec4_visitor::visit(ir_dereference_array
*ir
)
1732 ir_constant
*constant_index
;
1734 int array_stride
= compute_array_stride(ir
);
1736 constant_index
= ir
->array_index
->constant_expression_value();
1738 ir
->array
->accept(this);
1741 if (constant_index
) {
1742 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
1744 /* Variable index array dereference. It eats the "vec4" of the
1745 * base of the array and an index that offsets the Mesa register
1748 ir
->array_index
->accept(this);
1752 if (array_stride
== 1) {
1753 index_reg
= this->result
;
1755 index_reg
= src_reg(this, glsl_type::int_type
);
1757 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
1761 src_reg temp
= src_reg(this, glsl_type::int_type
);
1763 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1768 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1769 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1772 /* If the type is smaller than a vec4, replicate the last channel out. */
1773 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1774 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1776 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1777 src
.type
= brw_type_for_base_type(ir
->type
);
1783 vec4_visitor::visit(ir_dereference_record
*ir
)
1786 const glsl_type
*struct_type
= ir
->record
->type
;
1789 ir
->record
->accept(this);
1791 for (i
= 0; i
< struct_type
->length
; i
++) {
1792 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1794 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1797 /* If the type is smaller than a vec4, replicate the last channel out. */
1798 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1799 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1801 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1802 this->result
.type
= brw_type_for_base_type(ir
->type
);
1804 this->result
.reg_offset
+= offset
;
1808 * We want to be careful in assignment setup to hit the actual storage
1809 * instead of potentially using a temporary like we might with the
1810 * ir_dereference handler.
1813 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1815 /* The LHS must be a dereference. If the LHS is a variable indexed array
1816 * access of a vector, it must be separated into a series conditional moves
1817 * before reaching this point (see ir_vec_index_to_cond_assign).
1819 assert(ir
->as_dereference());
1820 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1822 assert(!deref_array
->array
->type
->is_vector());
1825 /* Use the rvalue deref handler for the most part. We'll ignore
1826 * swizzles in it and write swizzles using writemask, though.
1829 return dst_reg(v
->result
);
1833 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1834 const struct glsl_type
*type
, uint32_t predicate
)
1836 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1837 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1838 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
1843 if (type
->is_array()) {
1844 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1845 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
1850 if (type
->is_matrix()) {
1851 const struct glsl_type
*vec_type
;
1853 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1854 type
->vector_elements
, 1);
1856 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1857 emit_block_move(dst
, src
, vec_type
, predicate
);
1862 assert(type
->is_scalar() || type
->is_vector());
1864 dst
->type
= brw_type_for_base_type(type
);
1865 src
->type
= dst
->type
;
1867 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1869 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1871 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
1872 inst
->predicate
= predicate
;
1879 /* If the RHS processing resulted in an instruction generating a
1880 * temporary value, and it would be easy to rewrite the instruction to
1881 * generate its result right into the LHS instead, do so. This ends
1882 * up reliably removing instructions where it can be tricky to do so
1883 * later without real UD chain information.
1886 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1889 vec4_instruction
*pre_rhs_inst
,
1890 vec4_instruction
*last_rhs_inst
)
1892 /* This could be supported, but it would take more smarts. */
1896 if (pre_rhs_inst
== last_rhs_inst
)
1897 return false; /* No instructions generated to work with. */
1899 /* Make sure the last instruction generated our source reg. */
1900 if (src
.file
!= GRF
||
1901 src
.file
!= last_rhs_inst
->dst
.file
||
1902 src
.reg
!= last_rhs_inst
->dst
.reg
||
1903 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
1907 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
1910 /* Check that that last instruction fully initialized the channels
1911 * we want to use, in the order we want to use them. We could
1912 * potentially reswizzle the operands of many instructions so that
1913 * we could handle out of order channels, but don't yet.
1916 for (unsigned i
= 0; i
< 4; i
++) {
1917 if (dst
.writemask
& (1 << i
)) {
1918 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
1921 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
1926 /* Success! Rewrite the instruction. */
1927 last_rhs_inst
->dst
.file
= dst
.file
;
1928 last_rhs_inst
->dst
.reg
= dst
.reg
;
1929 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
1930 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
1931 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
1937 vec4_visitor::visit(ir_assignment
*ir
)
1939 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
1940 uint32_t predicate
= BRW_PREDICATE_NONE
;
1942 if (!ir
->lhs
->type
->is_scalar() &&
1943 !ir
->lhs
->type
->is_vector()) {
1944 ir
->rhs
->accept(this);
1945 src_reg src
= this->result
;
1947 if (ir
->condition
) {
1948 emit_bool_to_cond_code(ir
->condition
, &predicate
);
1951 /* emit_block_move doesn't account for swizzles in the source register.
1952 * This should be ok, since the source register is a structure or an
1953 * array, and those can't be swizzled. But double-check to be sure.
1955 assert(src
.swizzle
==
1956 (ir
->rhs
->type
->is_matrix()
1957 ? swizzle_for_size(ir
->rhs
->type
->vector_elements
)
1958 : BRW_SWIZZLE_NOOP
));
1960 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
1964 /* Now we're down to just a scalar/vector with writemasks. */
1967 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
1968 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1970 ir
->rhs
->accept(this);
1972 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1974 src_reg src
= this->result
;
1977 int first_enabled_chan
= 0;
1980 assert(ir
->lhs
->type
->is_vector() ||
1981 ir
->lhs
->type
->is_scalar());
1982 dst
.writemask
= ir
->write_mask
;
1984 for (int i
= 0; i
< 4; i
++) {
1985 if (dst
.writemask
& (1 << i
)) {
1986 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
1991 /* Swizzle a small RHS vector into the channels being written.
1993 * glsl ir treats write_mask as dictating how many channels are
1994 * present on the RHS while in our instructions we need to make
1995 * those channels appear in the slots of the vec4 they're written to.
1997 for (int i
= 0; i
< 4; i
++) {
1998 if (dst
.writemask
& (1 << i
))
1999 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
2001 swizzles
[i
] = first_enabled_chan
;
2003 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2004 swizzles
[2], swizzles
[3]);
2006 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2010 if (ir
->condition
) {
2011 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2014 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2015 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2016 inst
->predicate
= predicate
;
2024 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2026 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2027 foreach_list(node
, &ir
->components
) {
2028 ir_constant
*field_value
= (ir_constant
*)node
;
2030 emit_constant_values(dst
, field_value
);
2035 if (ir
->type
->is_array()) {
2036 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2037 emit_constant_values(dst
, ir
->array_elements
[i
]);
2042 if (ir
->type
->is_matrix()) {
2043 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2044 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2046 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2047 dst
->writemask
= 1 << j
;
2048 dst
->type
= BRW_REGISTER_TYPE_F
;
2050 emit(MOV(*dst
, src_reg(vec
[j
])));
2057 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2059 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2060 if (!(remaining_writemask
& (1 << i
)))
2063 dst
->writemask
= 1 << i
;
2064 dst
->type
= brw_type_for_base_type(ir
->type
);
2066 /* Find other components that match the one we're about to
2067 * write. Emits fewer instructions for things like vec4(0.5,
2070 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2071 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2072 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2073 dst
->writemask
|= (1 << j
);
2075 /* u, i, and f storage all line up, so no need for a
2076 * switch case for comparing each type.
2078 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2079 dst
->writemask
|= (1 << j
);
2083 switch (ir
->type
->base_type
) {
2084 case GLSL_TYPE_FLOAT
:
2085 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2088 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2090 case GLSL_TYPE_UINT
:
2091 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2093 case GLSL_TYPE_BOOL
:
2094 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
])));
2097 assert(!"Non-float/uint/int/bool constant");
2101 remaining_writemask
&= ~dst
->writemask
;
2107 vec4_visitor::visit(ir_constant
*ir
)
2109 dst_reg dst
= dst_reg(this, ir
->type
);
2110 this->result
= src_reg(dst
);
2112 emit_constant_values(&dst
, ir
);
2116 vec4_visitor::visit(ir_call
*ir
)
2118 assert(!"not reached");
2122 vec4_visitor::visit(ir_texture
*ir
)
2125 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2127 /* Should be lowered by do_lower_texture_projection */
2128 assert(!ir
->projector
);
2130 /* Generate code to compute all the subexpression trees. This has to be
2131 * done before loading any values into MRFs for the sampler message since
2132 * generating these values may involve SEND messages that need the MRFs.
2135 if (ir
->coordinate
) {
2136 ir
->coordinate
->accept(this);
2137 coordinate
= this->result
;
2140 src_reg shadow_comparitor
;
2141 if (ir
->shadow_comparitor
) {
2142 ir
->shadow_comparitor
->accept(this);
2143 shadow_comparitor
= this->result
;
2146 const glsl_type
*lod_type
= NULL
, *sample_index_type
= NULL
;
2147 src_reg lod
, dPdx
, dPdy
, sample_index
;
2150 lod
= src_reg(0.0f
);
2151 lod_type
= glsl_type::float_type
;
2156 ir
->lod_info
.lod
->accept(this);
2158 lod_type
= ir
->lod_info
.lod
->type
;
2161 ir
->lod_info
.sample_index
->accept(this);
2162 sample_index
= this->result
;
2163 sample_index_type
= ir
->lod_info
.sample_index
->type
;
2166 ir
->lod_info
.grad
.dPdx
->accept(this);
2167 dPdx
= this->result
;
2169 ir
->lod_info
.grad
.dPdy
->accept(this);
2170 dPdy
= this->result
;
2172 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2179 vec4_instruction
*inst
= NULL
;
2183 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXL
);
2186 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXD
);
2189 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF
);
2192 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF_MS
);
2195 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXS
);
2198 assert(!"TXB is not valid for vertex shaders.");
2201 assert(!"LOD is not valid for vertex shaders.");
2205 bool use_texture_offset
= ir
->offset
!= NULL
&& ir
->op
!= ir_txf
;
2207 /* Texel offsets go in the message header; Gen4 also requires headers. */
2208 inst
->header_present
= use_texture_offset
|| intel
->gen
< 5;
2210 inst
->mlen
= inst
->header_present
+ 1; /* always at least one */
2211 inst
->sampler
= sampler
;
2212 inst
->dst
= dst_reg(this, ir
->type
);
2213 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2214 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2216 if (use_texture_offset
)
2217 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
2219 /* MRF for the first parameter */
2220 int param_base
= inst
->base_mrf
+ inst
->header_present
;
2222 if (ir
->op
== ir_txs
) {
2223 int writemask
= intel
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2224 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2226 int i
, coord_mask
= 0, zero_mask
= 0;
2227 /* Load the coordinate */
2228 /* FINISHME: gl_clamp_mask and saturate */
2229 for (i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++)
2230 coord_mask
|= (1 << i
);
2232 zero_mask
|= (1 << i
);
2234 if (ir
->offset
&& ir
->op
== ir_txf
) {
2235 /* It appears that the ld instruction used for txf does its
2236 * address bounds check before adding in the offset. To work
2237 * around this, just add the integer offset to the integer
2238 * texel coordinate, and don't put the offset in the header.
2240 ir_constant
*offset
= ir
->offset
->as_constant();
2243 for (int j
= 0; j
< ir
->coordinate
->type
->vector_elements
; j
++) {
2244 src_reg src
= coordinate
;
2245 src
.swizzle
= BRW_SWIZZLE4(BRW_GET_SWZ(src
.swizzle
, j
),
2246 BRW_GET_SWZ(src
.swizzle
, j
),
2247 BRW_GET_SWZ(src
.swizzle
, j
),
2248 BRW_GET_SWZ(src
.swizzle
, j
));
2249 emit(ADD(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, 1 << j
),
2250 src
, offset
->value
.i
[j
]));
2253 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2256 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2258 /* Load the shadow comparitor */
2259 if (ir
->shadow_comparitor
) {
2260 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2262 shadow_comparitor
));
2266 /* Load the LOD info */
2267 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2269 if (intel
->gen
>= 5) {
2270 mrf
= param_base
+ 1;
2271 if (ir
->shadow_comparitor
) {
2272 writemask
= WRITEMASK_Y
;
2273 /* mlen already incremented */
2275 writemask
= WRITEMASK_X
;
2278 } else /* intel->gen == 4 */ {
2280 writemask
= WRITEMASK_Z
;
2282 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2283 } else if (ir
->op
== ir_txf
) {
2284 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
), lod
));
2285 } else if (ir
->op
== ir_txf_ms
) {
2286 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index_type
, WRITEMASK_X
),
2290 /* on Gen7, there is an additional MCS parameter here after SI,
2291 * but we don't bother to emit it since it's always zero. If
2292 * we start supporting texturing from CMS surfaces, this will have
2295 } else if (ir
->op
== ir_txd
) {
2296 const glsl_type
*type
= lod_type
;
2298 if (intel
->gen
>= 5) {
2299 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2300 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2301 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2302 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2305 if (ir
->type
->vector_elements
== 3) {
2306 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2307 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2308 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2309 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2312 } else /* intel->gen == 4 */ {
2313 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2314 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2322 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2323 * spec requires layers.
2325 if (ir
->op
== ir_txs
) {
2326 glsl_type
const *type
= ir
->sampler
->type
;
2327 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2328 type
->sampler_array
) {
2329 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2330 with_writemask(inst
->dst
, WRITEMASK_Z
),
2331 src_reg(inst
->dst
), src_reg(6));
2335 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2339 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, int sampler
)
2341 int s
= key
->tex
.swizzles
[sampler
];
2343 this->result
= src_reg(this, ir
->type
);
2344 dst_reg
swizzled_result(this->result
);
2346 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2347 || s
== SWIZZLE_NOOP
) {
2348 emit(MOV(swizzled_result
, orig_val
));
2352 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2355 for (int i
= 0; i
< 4; i
++) {
2356 switch (GET_SWZ(s
, i
)) {
2358 zero_mask
|= (1 << i
);
2361 one_mask
|= (1 << i
);
2364 copy_mask
|= (1 << i
);
2365 swizzle
[i
] = GET_SWZ(s
, i
);
2371 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2372 swizzled_result
.writemask
= copy_mask
;
2373 emit(MOV(swizzled_result
, orig_val
));
2377 swizzled_result
.writemask
= zero_mask
;
2378 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2382 swizzled_result
.writemask
= one_mask
;
2383 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2388 vec4_visitor::visit(ir_return
*ir
)
2390 assert(!"not reached");
2394 vec4_visitor::visit(ir_discard
*ir
)
2396 assert(!"not reached");
2400 vec4_visitor::visit(ir_if
*ir
)
2402 /* Don't point the annotation at the if statement, because then it plus
2403 * the then and else blocks get printed.
2405 this->base_ir
= ir
->condition
;
2407 if (intel
->gen
== 6) {
2411 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2412 emit(IF(predicate
));
2415 visit_instructions(&ir
->then_instructions
);
2417 if (!ir
->else_instructions
.is_empty()) {
2418 this->base_ir
= ir
->condition
;
2419 emit(BRW_OPCODE_ELSE
);
2421 visit_instructions(&ir
->else_instructions
);
2424 this->base_ir
= ir
->condition
;
2425 emit(BRW_OPCODE_ENDIF
);
2429 vec4_visitor::emit_ndc_computation()
2431 /* Get the position */
2432 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
2434 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
2435 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
2436 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
2438 current_annotation
= "NDC";
2439 dst_reg ndc_w
= ndc
;
2440 ndc_w
.writemask
= WRITEMASK_W
;
2441 src_reg pos_w
= pos
;
2442 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2443 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
2445 dst_reg ndc_xyz
= ndc
;
2446 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
2448 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
2452 vec4_visitor::emit_psiz_and_flags(struct brw_reg reg
)
2454 if (intel
->gen
< 6 &&
2455 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
2456 key
->userclip_active
|| brw
->has_negative_rhw_bug
)) {
2457 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
2458 dst_reg header1_w
= header1
;
2459 header1_w
.writemask
= WRITEMASK_W
;
2462 emit(MOV(header1
, 0u));
2464 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2465 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
2467 current_annotation
= "Point size";
2468 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
2469 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
2472 current_annotation
= "Clipping flags";
2473 for (i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
2474 vec4_instruction
*inst
;
2476 inst
= emit(DP4(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_POS
]),
2477 src_reg(this->userplane
[i
])));
2478 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
2480 inst
= emit(OR(header1_w
, src_reg(header1_w
), 1u << i
));
2481 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2484 /* i965 clipping workaround:
2485 * 1) Test for -ve rhw
2487 * set ndc = (0,0,0,0)
2490 * Later, clipping will detect ucp[6] and ensure the primitive is
2491 * clipped against all fixed planes.
2493 if (brw
->has_negative_rhw_bug
) {
2494 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
2495 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
2496 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
2497 vec4_instruction
*inst
;
2498 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
2499 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2500 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
2501 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2504 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
2505 } else if (intel
->gen
< 6) {
2506 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
2508 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
2509 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2510 emit(MOV(brw_writemask(reg
, WRITEMASK_W
),
2511 src_reg(output_reg
[VARYING_SLOT_PSIZ
])));
2517 vec4_visitor::emit_clip_distances(struct brw_reg reg
, int offset
)
2519 if (intel
->gen
< 6) {
2520 /* Clip distance slots are set aside in gen5, but they are not used. It
2521 * is not clear whether we actually need to set aside space for them,
2522 * but the performance cost is negligible.
2527 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
2529 * "If a linked set of shaders forming the vertex stage contains no
2530 * static write to gl_ClipVertex or gl_ClipDistance, but the
2531 * application has requested clipping against user clip planes through
2532 * the API, then the coordinate written to gl_Position is used for
2533 * comparison against the user clip planes."
2535 * This function is only called if the shader didn't write to
2536 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
2537 * if the user wrote to it; otherwise we use gl_Position.
2539 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
2540 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
2541 clip_vertex
= VARYING_SLOT_POS
;
2544 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
2546 emit(DP4(dst_reg(brw_writemask(reg
, 1 << i
)),
2547 src_reg(output_reg
[clip_vertex
]),
2548 src_reg(this->userplane
[i
+ offset
])));
2553 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
2555 assert (varying
< VARYING_SLOT_MAX
);
2556 reg
.type
= output_reg
[varying
].type
;
2557 current_annotation
= output_reg_annotation
[varying
];
2558 /* Copy the register, saturating if necessary */
2559 vec4_instruction
*inst
= emit(MOV(reg
,
2560 src_reg(output_reg
[varying
])));
2561 if ((varying
== VARYING_SLOT_COL0
||
2562 varying
== VARYING_SLOT_COL1
||
2563 varying
== VARYING_SLOT_BFC0
||
2564 varying
== VARYING_SLOT_BFC1
) &&
2565 key
->clamp_vertex_color
) {
2566 inst
->saturate
= true;
2571 vec4_visitor::emit_urb_slot(int mrf
, int varying
)
2573 struct brw_reg hw_reg
= brw_message_reg(mrf
);
2574 dst_reg reg
= dst_reg(MRF
, mrf
);
2575 reg
.type
= BRW_REGISTER_TYPE_F
;
2578 case VARYING_SLOT_PSIZ
:
2579 /* PSIZ is always in slot 0, and is coupled with other flags. */
2580 current_annotation
= "indices, point width, clip flags";
2581 emit_psiz_and_flags(hw_reg
);
2583 case BRW_VARYING_SLOT_NDC
:
2584 current_annotation
= "NDC";
2585 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
2587 case BRW_VARYING_SLOT_POS_DUPLICATE
:
2588 case VARYING_SLOT_POS
:
2589 current_annotation
= "gl_Position";
2590 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
2592 case VARYING_SLOT_CLIP_DIST0
:
2593 case VARYING_SLOT_CLIP_DIST1
:
2594 if (this->key
->uses_clip_distance
) {
2595 emit_generic_urb_slot(reg
, varying
);
2597 current_annotation
= "user clip distances";
2598 emit_clip_distances(hw_reg
, (varying
- VARYING_SLOT_CLIP_DIST0
) * 4);
2601 case VARYING_SLOT_EDGE
:
2602 /* This is present when doing unfilled polygons. We're supposed to copy
2603 * the edge flag from the user-provided vertex array
2604 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
2605 * of that attribute (starts as 1.0f). This is then used in clipping to
2606 * determine which edges should be drawn as wireframe.
2608 current_annotation
= "edge flag";
2609 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
2610 glsl_type::float_type
, WRITEMASK_XYZW
))));
2612 case BRW_VARYING_SLOT_PAD
:
2613 /* No need to write to this slot */
2616 emit_generic_urb_slot(reg
, varying
);
2622 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
2624 struct intel_context
*intel
= &brw
->intel
;
2626 if (intel
->gen
>= 6) {
2627 /* URB data written (does not include the message header reg) must
2628 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
2629 * section 5.4.3.2.2: URB_INTERLEAVED.
2631 * URB entries are allocated on a multiple of 1024 bits, so an
2632 * extra 128 bits written here to make the end align to 256 is
2635 if ((mlen
% 2) != 1)
2643 vec4_vs_visitor::emit_urb_write_header(int mrf
)
2645 /* No need to do anything for VS; an implied write to this MRF will be
2646 * performed by VS_OPCODE_URB_WRITE.
2652 vec4_vs_visitor::emit_urb_write_opcode(bool complete
)
2654 /* For VS, the URB writes end the thread. */
2656 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2657 emit_shader_time_end();
2660 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
2661 inst
->eot
= complete
;
2667 * Generates the VUE payload plus the necessary URB write instructions to
2670 * The VUE layout is documented in Volume 2a.
2673 vec4_visitor::emit_vertex()
2675 /* MRF 0 is reserved for the debugger, so start with message header
2680 /* In the process of generating our URB write message contents, we
2681 * may need to unspill a register or load from an array. Those
2682 * reads would use MRFs 14-15.
2684 int max_usable_mrf
= 13;
2686 /* The following assertion verifies that max_usable_mrf causes an
2687 * even-numbered amount of URB write data, which will meet gen6's
2688 * requirements for length alignment.
2690 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
2692 /* First mrf is the g0-based message header containing URB handles and
2695 emit_urb_write_header(mrf
++);
2697 if (intel
->gen
< 6) {
2698 emit_ndc_computation();
2701 /* Set up the VUE data for the first URB write */
2703 for (slot
= 0; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
2704 emit_urb_slot(mrf
++, prog_data
->vue_map
.slot_to_varying
[slot
]);
2706 /* If this was max_usable_mrf, we can't fit anything more into this URB
2709 if (mrf
> max_usable_mrf
) {
2715 bool complete
= slot
>= prog_data
->vue_map
.num_slots
;
2716 current_annotation
= "URB write";
2717 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
2718 inst
->base_mrf
= base_mrf
;
2719 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
2721 /* Optional second URB write */
2725 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
2726 assert(mrf
< max_usable_mrf
);
2728 emit_urb_slot(mrf
++, prog_data
->vue_map
.slot_to_varying
[slot
]);
2731 current_annotation
= "URB write";
2732 inst
= emit_urb_write_opcode(true /* complete */);
2733 inst
->base_mrf
= base_mrf
;
2734 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
2735 /* URB destination offset. In the previous write, we got MRFs
2736 * 2-13 minus the one header MRF, so 12 regs. URB offset is in
2737 * URB row increments, and each of our MRFs is half of one of
2738 * those, since we're doing interleaved writes.
2740 inst
->offset
= (max_usable_mrf
- base_mrf
) / 2;
2745 vec4_vs_visitor::emit_thread_end()
2747 /* For VS, we always end the thread by emitting a single vertex.
2748 * emit_urb_write_opcode() will take care of setting the eot flag on the
2755 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
2756 src_reg
*reladdr
, int reg_offset
)
2758 /* Because we store the values to scratch interleaved like our
2759 * vertex data, we need to scale the vec4 index by 2.
2761 int message_header_scale
= 2;
2763 /* Pre-gen6, the message header uses byte offsets instead of vec4
2764 * (16-byte) offset units.
2767 message_header_scale
*= 16;
2770 src_reg index
= src_reg(this, glsl_type::int_type
);
2772 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
2773 emit_before(inst
, MUL(dst_reg(index
),
2774 index
, src_reg(message_header_scale
)));
2778 return src_reg(reg_offset
* message_header_scale
);
2783 vec4_visitor::get_pull_constant_offset(vec4_instruction
*inst
,
2784 src_reg
*reladdr
, int reg_offset
)
2787 src_reg index
= src_reg(this, glsl_type::int_type
);
2789 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
2791 /* Pre-gen6, the message header uses byte offsets instead of vec4
2792 * (16-byte) offset units.
2794 if (intel
->gen
< 6) {
2795 emit_before(inst
, MUL(dst_reg(index
), index
, src_reg(16)));
2800 int message_header_scale
= intel
->gen
< 6 ? 16 : 1;
2801 return src_reg(reg_offset
* message_header_scale
);
2806 * Emits an instruction before @inst to load the value named by @orig_src
2807 * from scratch space at @base_offset to @temp.
2809 * @base_offset is measured in 32-byte units (the size of a register).
2812 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
2813 dst_reg temp
, src_reg orig_src
,
2816 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2817 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
2819 emit_before(inst
, SCRATCH_READ(temp
, index
));
2823 * Emits an instruction after @inst to store the value to be written
2824 * to @orig_dst to scratch space at @base_offset, from @temp.
2826 * @base_offset is measured in 32-byte units (the size of a register).
2829 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
, int base_offset
)
2831 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
2832 src_reg index
= get_scratch_offset(inst
, inst
->dst
.reladdr
, reg_offset
);
2834 /* Create a temporary register to store *inst's result in.
2836 * We have to be careful in MOVing from our temporary result register in
2837 * the scratch write. If we swizzle from channels of the temporary that
2838 * weren't initialized, it will confuse live interval analysis, which will
2839 * make spilling fail to make progress.
2841 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
2842 temp
.type
= inst
->dst
.type
;
2843 int first_writemask_chan
= ffs(inst
->dst
.writemask
) - 1;
2845 for (int i
= 0; i
< 4; i
++)
2846 if (inst
->dst
.writemask
& (1 << i
))
2849 swizzles
[i
] = first_writemask_chan
;
2850 temp
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2851 swizzles
[2], swizzles
[3]);
2853 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
2854 inst
->dst
.writemask
));
2855 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
2856 write
->predicate
= inst
->predicate
;
2857 write
->ir
= inst
->ir
;
2858 write
->annotation
= inst
->annotation
;
2859 inst
->insert_after(write
);
2861 inst
->dst
.file
= temp
.file
;
2862 inst
->dst
.reg
= temp
.reg
;
2863 inst
->dst
.reg_offset
= temp
.reg_offset
;
2864 inst
->dst
.reladdr
= NULL
;
2868 * We can't generally support array access in GRF space, because a
2869 * single instruction's destination can only span 2 contiguous
2870 * registers. So, we send all GRF arrays that get variable index
2871 * access to scratch space.
2874 vec4_visitor::move_grf_array_access_to_scratch()
2876 int scratch_loc
[this->virtual_grf_count
];
2878 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
2879 scratch_loc
[i
] = -1;
2882 /* First, calculate the set of virtual GRFs that need to be punted
2883 * to scratch due to having any array access on them, and where in
2886 foreach_list(node
, &this->instructions
) {
2887 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2889 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
2890 scratch_loc
[inst
->dst
.reg
] == -1) {
2891 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
2892 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
];
2895 for (int i
= 0 ; i
< 3; i
++) {
2896 src_reg
*src
= &inst
->src
[i
];
2898 if (src
->file
== GRF
&& src
->reladdr
&&
2899 scratch_loc
[src
->reg
] == -1) {
2900 scratch_loc
[src
->reg
] = c
->last_scratch
;
2901 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
];
2906 /* Now, for anything that will be accessed through scratch, rewrite
2907 * it to load/store. Note that this is a _safe list walk, because
2908 * we may generate a new scratch_write instruction after the one
2911 foreach_list_safe(node
, &this->instructions
) {
2912 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2914 /* Set up the annotation tracking for new generated instructions. */
2916 current_annotation
= inst
->annotation
;
2918 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
2919 emit_scratch_write(inst
, scratch_loc
[inst
->dst
.reg
]);
2922 for (int i
= 0 ; i
< 3; i
++) {
2923 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
2926 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2928 emit_scratch_read(inst
, temp
, inst
->src
[i
],
2929 scratch_loc
[inst
->src
[i
].reg
]);
2931 inst
->src
[i
].file
= temp
.file
;
2932 inst
->src
[i
].reg
= temp
.reg
;
2933 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2934 inst
->src
[i
].reladdr
= NULL
;
2940 * Emits an instruction before @inst to load the value named by @orig_src
2941 * from the pull constant buffer (surface) at @base_offset to @temp.
2944 vec4_visitor::emit_pull_constant_load(vec4_instruction
*inst
,
2945 dst_reg temp
, src_reg orig_src
,
2948 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2949 src_reg index
= src_reg((unsigned)SURF_INDEX_VERT_CONST_BUFFER
);
2950 src_reg offset
= get_pull_constant_offset(inst
, orig_src
.reladdr
, reg_offset
);
2951 vec4_instruction
*load
;
2953 if (intel
->gen
>= 7) {
2954 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
2955 grf_offset
.type
= offset
.type
;
2956 emit_before(inst
, MOV(grf_offset
, offset
));
2958 load
= new(mem_ctx
) vec4_instruction(this,
2959 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
2960 temp
, index
, src_reg(grf_offset
));
2962 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
2963 temp
, index
, offset
);
2964 load
->base_mrf
= 14;
2967 emit_before(inst
, load
);
2971 * Implements array access of uniforms by inserting a
2972 * PULL_CONSTANT_LOAD instruction.
2974 * Unlike temporary GRF array access (where we don't support it due to
2975 * the difficulty of doing relative addressing on instruction
2976 * destinations), we could potentially do array access of uniforms
2977 * that were loaded in GRF space as push constants. In real-world
2978 * usage we've seen, though, the arrays being used are always larger
2979 * than we could load as push constants, so just always move all
2980 * uniform array access out to a pull constant buffer.
2983 vec4_visitor::move_uniform_array_access_to_pull_constants()
2985 int pull_constant_loc
[this->uniforms
];
2987 for (int i
= 0; i
< this->uniforms
; i
++) {
2988 pull_constant_loc
[i
] = -1;
2991 /* Walk through and find array access of uniforms. Put a copy of that
2992 * uniform in the pull constant buffer.
2994 * Note that we don't move constant-indexed accesses to arrays. No
2995 * testing has been done of the performance impact of this choice.
2997 foreach_list_safe(node
, &this->instructions
) {
2998 vec4_instruction
*inst
= (vec4_instruction
*)node
;
3000 for (int i
= 0 ; i
< 3; i
++) {
3001 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3004 int uniform
= inst
->src
[i
].reg
;
3006 /* If this array isn't already present in the pull constant buffer,
3009 if (pull_constant_loc
[uniform
] == -1) {
3010 const float **values
= &prog_data
->param
[uniform
* 4];
3012 pull_constant_loc
[uniform
] = prog_data
->nr_pull_params
/ 4;
3014 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3015 prog_data
->pull_param
[prog_data
->nr_pull_params
++]
3020 /* Set up the annotation tracking for new generated instructions. */
3022 current_annotation
= inst
->annotation
;
3024 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3026 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
3027 pull_constant_loc
[uniform
]);
3029 inst
->src
[i
].file
= temp
.file
;
3030 inst
->src
[i
].reg
= temp
.reg
;
3031 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3032 inst
->src
[i
].reladdr
= NULL
;
3036 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3037 * no need to track them as larger-than-vec4 objects. This will be
3038 * relied on in cutting out unused uniform vectors from push
3041 split_uniform_registers();
3045 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3047 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3051 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3052 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3056 vec4_visitor::vec4_visitor(struct brw_context
*brw
,
3057 struct brw_vec4_compile
*c
,
3058 struct gl_program
*prog
,
3059 const struct brw_vec4_prog_key
*key
,
3060 struct brw_vec4_prog_data
*prog_data
,
3061 struct gl_shader_program
*shader_prog
,
3062 struct brw_shader
*shader
,
3065 : debug_flag(debug_flag
)
3068 this->intel
= &brw
->intel
;
3069 this->ctx
= &intel
->ctx
;
3070 this->shader_prog
= shader_prog
;
3071 this->shader
= shader
;
3073 this->mem_ctx
= mem_ctx
;
3074 this->failed
= false;
3076 this->base_ir
= NULL
;
3077 this->current_annotation
= NULL
;
3078 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3083 this->prog_data
= prog_data
;
3085 this->variable_ht
= hash_table_ctor(0,
3086 hash_table_pointer_hash
,
3087 hash_table_pointer_compare
);
3089 this->virtual_grf_def
= NULL
;
3090 this->virtual_grf_use
= NULL
;
3091 this->virtual_grf_sizes
= NULL
;
3092 this->virtual_grf_count
= 0;
3093 this->virtual_grf_reg_map
= NULL
;
3094 this->virtual_grf_reg_count
= 0;
3095 this->virtual_grf_array_size
= 0;
3096 this->live_intervals_valid
= false;
3098 this->max_grf
= intel
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3103 vec4_visitor::~vec4_visitor()
3105 hash_table_dtor(this->variable_ht
);
3109 vec4_vs_visitor::vec4_vs_visitor(struct brw_context
*brw
,
3110 struct brw_vs_compile
*vs_compile
,
3111 struct brw_vs_prog_data
*vs_prog_data
,
3112 struct gl_shader_program
*prog
,
3113 struct brw_shader
*shader
,
3115 : vec4_visitor(brw
, &vs_compile
->base
, &vs_compile
->vp
->program
.Base
,
3116 &vs_compile
->key
.base
, &vs_prog_data
->base
, prog
, shader
,
3117 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
),
3118 vs_compile(vs_compile
),
3119 vs_prog_data(vs_prog_data
)
3125 vec4_visitor::fail(const char *format
, ...)
3135 va_start(va
, format
);
3136 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3138 msg
= ralloc_asprintf(mem_ctx
, "VS compile failed: %s\n", msg
);
3140 this->fail_msg
= msg
;
3143 fprintf(stderr
, "%s", msg
);
3147 } /* namespace brw */