2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "main/macros.h"
27 #include "program/prog_parameter.h"
28 #include "program/sampler.h"
33 src_reg::src_reg(dst_reg reg
)
37 this->file
= reg
.file
;
39 this->reg_offset
= reg
.reg_offset
;
40 this->type
= reg
.type
;
41 this->reladdr
= reg
.reladdr
;
42 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
48 for (int i
= 0; i
< 4; i
++) {
49 if (!(reg
.writemask
& (1 << i
)))
52 swizzles
[next_chan
++] = last
= i
;
55 for (; next_chan
< 4; next_chan
++) {
56 swizzles
[next_chan
] = last
;
59 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
60 swizzles
[2], swizzles
[3]);
63 dst_reg::dst_reg(src_reg reg
)
67 this->file
= reg
.file
;
69 this->reg_offset
= reg
.reg_offset
;
70 this->type
= reg
.type
;
71 this->writemask
= WRITEMASK_XYZW
;
72 this->reladdr
= reg
.reladdr
;
73 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
76 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
77 enum opcode opcode
, dst_reg dst
,
78 src_reg src0
, src_reg src1
, src_reg src2
)
80 this->opcode
= opcode
;
85 this->ir
= v
->base_ir
;
86 this->annotation
= v
->current_annotation
;
90 vec4_visitor::emit(vec4_instruction
*inst
)
92 this->instructions
.push_tail(inst
);
98 vec4_visitor::emit_before(vec4_instruction
*inst
, vec4_instruction
*new_inst
)
100 new_inst
->ir
= inst
->ir
;
101 new_inst
->annotation
= inst
->annotation
;
103 inst
->insert_before(new_inst
);
109 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
110 src_reg src0
, src_reg src1
, src_reg src2
)
112 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
118 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
120 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
124 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
126 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
130 vec4_visitor::emit(enum opcode opcode
)
132 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
137 vec4_visitor::op(dst_reg dst, src_reg src0) \
139 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
145 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \
147 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
166 /** Gen4 predicated IF. */
168 vec4_visitor::IF(uint32_t predicate
)
170 vec4_instruction
*inst
;
172 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
173 inst
->predicate
= predicate
;
178 /** Gen6+ IF with embedded comparison. */
180 vec4_visitor::IF(src_reg src0
, src_reg src1
, uint32_t condition
)
182 assert(intel
->gen
>= 6);
184 vec4_instruction
*inst
;
186 resolve_ud_negate(&src0
);
187 resolve_ud_negate(&src1
);
189 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
191 inst
->conditional_mod
= condition
;
197 * CMP: Sets the low bit of the destination channels with the result
198 * of the comparison, while the upper bits are undefined, and updates
199 * the flag register with the packed 16 bits of the result.
202 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
, uint32_t condition
)
204 vec4_instruction
*inst
;
206 /* original gen4 does type conversion to the destination type
207 * before before comparison, producing garbage results for floating
210 if (intel
->gen
== 4) {
211 dst
.type
= src0
.type
;
212 if (dst
.file
== HW_REG
)
213 dst
.fixed_hw_reg
.type
= dst
.type
;
216 resolve_ud_negate(&src0
);
217 resolve_ud_negate(&src1
);
219 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
, src0
, src1
);
220 inst
->conditional_mod
= condition
;
226 vec4_visitor::SCRATCH_READ(dst_reg dst
, src_reg index
)
228 vec4_instruction
*inst
;
230 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_READ
,
239 vec4_visitor::SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
)
241 vec4_instruction
*inst
;
243 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_WRITE
,
252 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
254 static enum opcode dot_opcodes
[] = {
255 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
258 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
262 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
264 /* The gen6 math instruction ignores the source modifiers --
265 * swizzle, abs, negate, and at least some parts of the register
266 * region description.
268 * While it would seem that this MOV could be avoided at this point
269 * in the case that the swizzle is matched up with the destination
270 * writemask, note that uniform packing and register allocation
271 * could rearrange our swizzle, so let's leave this matter up to
272 * copy propagation later.
274 src_reg temp_src
= src_reg(this, glsl_type::vec4_type
);
275 emit(MOV(dst_reg(temp_src
), src
));
277 if (dst
.writemask
!= WRITEMASK_XYZW
) {
278 /* The gen6 math instruction must be align1, so we can't do
281 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
283 emit(opcode
, temp_dst
, temp_src
);
285 emit(MOV(dst
, src_reg(temp_dst
)));
287 emit(opcode
, dst
, temp_src
);
292 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
294 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
300 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
303 case SHADER_OPCODE_RCP
:
304 case SHADER_OPCODE_RSQ
:
305 case SHADER_OPCODE_SQRT
:
306 case SHADER_OPCODE_EXP2
:
307 case SHADER_OPCODE_LOG2
:
308 case SHADER_OPCODE_SIN
:
309 case SHADER_OPCODE_COS
:
312 assert(!"not reached: bad math opcode");
316 if (intel
->gen
>= 7) {
317 emit(opcode
, dst
, src
);
318 } else if (intel
->gen
== 6) {
319 return emit_math1_gen6(opcode
, dst
, src
);
321 return emit_math1_gen4(opcode
, dst
, src
);
326 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
327 dst_reg dst
, src_reg src0
, src_reg src1
)
331 /* The gen6 math instruction ignores the source modifiers --
332 * swizzle, abs, negate, and at least some parts of the register
333 * region description. Move the sources to temporaries to make it
337 expanded
= src_reg(this, glsl_type::vec4_type
);
338 expanded
.type
= src0
.type
;
339 emit(MOV(dst_reg(expanded
), src0
));
342 expanded
= src_reg(this, glsl_type::vec4_type
);
343 expanded
.type
= src1
.type
;
344 emit(MOV(dst_reg(expanded
), src1
));
347 if (dst
.writemask
!= WRITEMASK_XYZW
) {
348 /* The gen6 math instruction must be align1, so we can't do
351 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
352 temp_dst
.type
= dst
.type
;
354 emit(opcode
, temp_dst
, src0
, src1
);
356 emit(MOV(dst
, src_reg(temp_dst
)));
358 emit(opcode
, dst
, src0
, src1
);
363 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
364 dst_reg dst
, src_reg src0
, src_reg src1
)
366 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
372 vec4_visitor::emit_math(enum opcode opcode
,
373 dst_reg dst
, src_reg src0
, src_reg src1
)
376 case SHADER_OPCODE_POW
:
377 case SHADER_OPCODE_INT_QUOTIENT
:
378 case SHADER_OPCODE_INT_REMAINDER
:
381 assert(!"not reached: unsupported binary math opcode");
385 if (intel
->gen
>= 7) {
386 emit(opcode
, dst
, src0
, src1
);
387 } else if (intel
->gen
== 6) {
388 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
390 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
395 vec4_visitor::visit_instructions(const exec_list
*list
)
397 foreach_list(node
, list
) {
398 ir_instruction
*ir
= (ir_instruction
*)node
;
407 type_size(const struct glsl_type
*type
)
412 switch (type
->base_type
) {
415 case GLSL_TYPE_FLOAT
:
417 if (type
->is_matrix()) {
418 return type
->matrix_columns
;
420 /* Regardless of size of vector, it gets a vec4. This is bad
421 * packing for things like floats, but otherwise arrays become a
422 * mess. Hopefully a later pass over the code can pack scalars
423 * down if appropriate.
427 case GLSL_TYPE_ARRAY
:
428 assert(type
->length
> 0);
429 return type_size(type
->fields
.array
) * type
->length
;
430 case GLSL_TYPE_STRUCT
:
432 for (i
= 0; i
< type
->length
; i
++) {
433 size
+= type_size(type
->fields
.structure
[i
].type
);
436 case GLSL_TYPE_SAMPLER
:
437 /* Samplers take up one slot in UNIFORMS[], but they're baked in
448 vec4_visitor::virtual_grf_alloc(int size
)
450 if (virtual_grf_array_size
<= virtual_grf_count
) {
451 if (virtual_grf_array_size
== 0)
452 virtual_grf_array_size
= 16;
454 virtual_grf_array_size
*= 2;
455 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
456 virtual_grf_array_size
);
457 virtual_grf_reg_map
= reralloc(mem_ctx
, virtual_grf_reg_map
, int,
458 virtual_grf_array_size
);
460 virtual_grf_reg_map
[virtual_grf_count
] = virtual_grf_reg_count
;
461 virtual_grf_reg_count
+= size
;
462 virtual_grf_sizes
[virtual_grf_count
] = size
;
463 return virtual_grf_count
++;
466 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
471 this->reg
= v
->virtual_grf_alloc(type_size(type
));
473 if (type
->is_array() || type
->is_record()) {
474 this->swizzle
= BRW_SWIZZLE_NOOP
;
476 this->swizzle
= swizzle_for_size(type
->vector_elements
);
479 this->type
= brw_type_for_base_type(type
);
482 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
487 this->reg
= v
->virtual_grf_alloc(type_size(type
));
489 if (type
->is_array() || type
->is_record()) {
490 this->writemask
= WRITEMASK_XYZW
;
492 this->writemask
= (1 << type
->vector_elements
) - 1;
495 this->type
= brw_type_for_base_type(type
);
498 /* Our support for uniforms is piggy-backed on the struct
499 * gl_fragment_program, because that's where the values actually
500 * get stored, rather than in some global gl_shader_program uniform
504 vec4_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
506 unsigned int offset
= 0;
507 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[loc
][0].f
;
509 if (type
->is_matrix()) {
510 const glsl_type
*column
= type
->column_type();
512 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
513 offset
+= setup_uniform_values(loc
+ offset
, column
);
519 switch (type
->base_type
) {
520 case GLSL_TYPE_FLOAT
:
524 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
525 c
->prog_data
.param
[this->uniforms
* 4 + i
] = &values
[i
];
528 /* Set up pad elements to get things aligned to a vec4 boundary. */
529 for (unsigned int i
= type
->vector_elements
; i
< 4; i
++) {
530 static float zero
= 0;
532 c
->prog_data
.param
[this->uniforms
* 4 + i
] = &zero
;
535 /* Track the size of this uniform vector, for future packing of
538 this->uniform_vector_size
[this->uniforms
] = type
->vector_elements
;
543 case GLSL_TYPE_STRUCT
:
544 for (unsigned int i
= 0; i
< type
->length
; i
++) {
545 offset
+= setup_uniform_values(loc
+ offset
,
546 type
->fields
.structure
[i
].type
);
550 case GLSL_TYPE_ARRAY
:
551 for (unsigned int i
= 0; i
< type
->length
; i
++) {
552 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
556 case GLSL_TYPE_SAMPLER
:
557 /* The sampler takes up a slot, but we don't use any values from it. */
561 assert(!"not reached");
567 vec4_visitor::setup_uniform_clipplane_values()
569 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
571 /* Pre-Gen6, we compact clip planes. For example, if the user
572 * enables just clip planes 0, 1, and 3, we will enable clip planes
573 * 0, 1, and 2 in the hardware, and we'll move clip plane 3 to clip
574 * plane 2. This simplifies the implementation of the Gen6 clip
577 * In Gen6 and later, we don't compact clip planes, because this
578 * simplifies the implementation of gl_ClipDistance.
580 int compacted_clipplane_index
= 0;
581 for (int i
= 0; i
< c
->key
.nr_userclip_plane_consts
; ++i
) {
582 if (intel
->gen
< 6 &&
583 !(c
->key
.userclip_planes_enabled_gen_4_5
& (1 << i
))) {
586 this->uniform_vector_size
[this->uniforms
] = 4;
587 this->userplane
[compacted_clipplane_index
] = dst_reg(UNIFORM
, this->uniforms
);
588 this->userplane
[compacted_clipplane_index
].type
= BRW_REGISTER_TYPE_F
;
589 for (int j
= 0; j
< 4; ++j
) {
590 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &clip_planes
[i
][j
];
592 ++compacted_clipplane_index
;
597 /* Our support for builtin uniforms is even scarier than non-builtin.
598 * It sits on top of the PROG_STATE_VAR parameters that are
599 * automatically updated from GL context state.
602 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
604 const ir_state_slot
*const slots
= ir
->state_slots
;
605 assert(ir
->state_slots
!= NULL
);
607 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
608 /* This state reference has already been setup by ir_to_mesa,
609 * but we'll get the same index back here. We can reference
610 * ParameterValues directly, since unlike brw_fs.cpp, we never
611 * add new state references during compile.
613 int index
= _mesa_add_state_reference(this->vp
->Base
.Parameters
,
614 (gl_state_index
*)slots
[i
].tokens
);
615 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
617 this->uniform_vector_size
[this->uniforms
] = 0;
618 /* Add each of the unique swizzled channels of the element.
619 * This will end up matching the size of the glsl_type of this field.
622 for (unsigned int j
= 0; j
< 4; j
++) {
623 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
626 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &values
[swiz
];
627 if (swiz
<= last_swiz
)
628 this->uniform_vector_size
[this->uniforms
]++;
635 vec4_visitor::variable_storage(ir_variable
*var
)
637 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
641 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
)
643 ir_expression
*expr
= ir
->as_expression();
645 *predicate
= BRW_PREDICATE_NORMAL
;
649 vec4_instruction
*inst
;
651 assert(expr
->get_num_operands() <= 2);
652 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
653 expr
->operands
[i
]->accept(this);
654 op
[i
] = this->result
;
656 resolve_ud_negate(&op
[i
]);
659 switch (expr
->operation
) {
660 case ir_unop_logic_not
:
661 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
662 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
665 case ir_binop_logic_xor
:
666 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
667 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
670 case ir_binop_logic_or
:
671 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
672 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
675 case ir_binop_logic_and
:
676 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
677 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
681 if (intel
->gen
>= 6) {
682 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
684 inst
= emit(MOV(dst_null_f(), op
[0]));
685 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
690 if (intel
->gen
>= 6) {
691 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
693 inst
= emit(MOV(dst_null_d(), op
[0]));
694 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
698 case ir_binop_all_equal
:
699 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
700 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
703 case ir_binop_any_nequal
:
704 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
705 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
709 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
710 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
713 case ir_binop_greater
:
714 case ir_binop_gequal
:
716 case ir_binop_lequal
:
718 case ir_binop_nequal
:
719 emit(CMP(dst_null_d(), op
[0], op
[1],
720 brw_conditional_for_comparison(expr
->operation
)));
724 assert(!"not reached");
732 resolve_ud_negate(&this->result
);
734 if (intel
->gen
>= 6) {
735 vec4_instruction
*inst
= emit(AND(dst_null_d(),
736 this->result
, src_reg(1)));
737 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
739 vec4_instruction
*inst
= emit(MOV(dst_null_d(), this->result
));
740 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
745 * Emit a gen6 IF statement with the comparison folded into the IF
749 vec4_visitor::emit_if_gen6(ir_if
*ir
)
751 ir_expression
*expr
= ir
->condition
->as_expression();
757 assert(expr
->get_num_operands() <= 2);
758 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
759 expr
->operands
[i
]->accept(this);
760 op
[i
] = this->result
;
763 switch (expr
->operation
) {
764 case ir_unop_logic_not
:
765 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
768 case ir_binop_logic_xor
:
769 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
772 case ir_binop_logic_or
:
773 temp
= dst_reg(this, glsl_type::bool_type
);
774 emit(OR(temp
, op
[0], op
[1]));
775 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
778 case ir_binop_logic_and
:
779 temp
= dst_reg(this, glsl_type::bool_type
);
780 emit(AND(temp
, op
[0], op
[1]));
781 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
785 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
789 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
792 case ir_binop_greater
:
793 case ir_binop_gequal
:
795 case ir_binop_lequal
:
797 case ir_binop_nequal
:
798 emit(IF(op
[0], op
[1],
799 brw_conditional_for_comparison(expr
->operation
)));
802 case ir_binop_all_equal
:
803 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
804 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
807 case ir_binop_any_nequal
:
808 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
809 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
813 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
814 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
818 assert(!"not reached");
819 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
825 ir
->condition
->accept(this);
827 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
831 vec4_visitor::visit(ir_variable
*ir
)
835 if (variable_storage(ir
))
840 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->location
);
842 /* Do GL_FIXED rescaling for GLES2.0. Our GL_FIXED attributes
843 * come in as floating point conversions of the integer values.
845 for (int i
= ir
->location
; i
< ir
->location
+ type_size(ir
->type
); i
++) {
846 if (!c
->key
.gl_fixed_input_size
[i
])
850 dst
.type
= brw_type_for_base_type(ir
->type
);
851 dst
.writemask
= (1 << c
->key
.gl_fixed_input_size
[i
]) - 1;
852 emit(MUL(dst
, src_reg(dst
), src_reg(1.0f
/ 65536.0f
)));
857 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
859 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
860 output_reg
[ir
->location
+ i
] = *reg
;
861 output_reg
[ir
->location
+ i
].reg_offset
= i
;
862 output_reg
[ir
->location
+ i
].type
=
863 brw_type_for_base_type(ir
->type
->get_scalar_type());
864 output_reg_annotation
[ir
->location
+ i
] = ir
->name
;
869 case ir_var_temporary
:
870 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
874 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
876 /* Track how big the whole uniform variable is, in case we need to put a
877 * copy of its data into pull constants for array access.
879 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
881 if (!strncmp(ir
->name
, "gl_", 3)) {
882 setup_builtin_uniform_values(ir
);
884 setup_uniform_values(ir
->location
, ir
->type
);
888 case ir_var_system_value
:
889 /* VertexID is stored by the VF as the last vertex element, but
890 * we don't represent it with a flag in inputs_read, so we call
891 * it VERT_ATTRIB_MAX, which setup_attributes() picks up on.
893 reg
= new(mem_ctx
) dst_reg(ATTR
, VERT_ATTRIB_MAX
);
894 prog_data
->uses_vertexid
= true;
896 switch (ir
->location
) {
897 case SYSTEM_VALUE_VERTEX_ID
:
898 reg
->writemask
= WRITEMASK_X
;
900 case SYSTEM_VALUE_INSTANCE_ID
:
901 reg
->writemask
= WRITEMASK_Y
;
904 assert(!"not reached");
910 assert(!"not reached");
913 reg
->type
= brw_type_for_base_type(ir
->type
);
914 hash_table_insert(this->variable_ht
, reg
, ir
);
918 vec4_visitor::visit(ir_loop
*ir
)
922 /* We don't want debugging output to print the whole body of the
923 * loop as the annotation.
925 this->base_ir
= NULL
;
927 if (ir
->counter
!= NULL
) {
928 this->base_ir
= ir
->counter
;
929 ir
->counter
->accept(this);
930 counter
= *(variable_storage(ir
->counter
));
932 if (ir
->from
!= NULL
) {
933 this->base_ir
= ir
->from
;
934 ir
->from
->accept(this);
936 emit(MOV(counter
, this->result
));
943 this->base_ir
= ir
->to
;
944 ir
->to
->accept(this);
946 emit(CMP(dst_null_d(), src_reg(counter
), this->result
,
947 brw_conditional_for_comparison(ir
->cmp
)));
949 vec4_instruction
*inst
= emit(BRW_OPCODE_BREAK
);
950 inst
->predicate
= BRW_PREDICATE_NORMAL
;
953 visit_instructions(&ir
->body_instructions
);
957 this->base_ir
= ir
->increment
;
958 ir
->increment
->accept(this);
959 emit(ADD(counter
, src_reg(counter
), this->result
));
962 emit(BRW_OPCODE_WHILE
);
966 vec4_visitor::visit(ir_loop_jump
*ir
)
969 case ir_loop_jump::jump_break
:
970 emit(BRW_OPCODE_BREAK
);
972 case ir_loop_jump::jump_continue
:
973 emit(BRW_OPCODE_CONTINUE
);
980 vec4_visitor::visit(ir_function_signature
*ir
)
987 vec4_visitor::visit(ir_function
*ir
)
989 /* Ignore function bodies other than main() -- we shouldn't see calls to
990 * them since they should all be inlined.
992 if (strcmp(ir
->name
, "main") == 0) {
993 const ir_function_signature
*sig
;
996 sig
= ir
->matching_signature(&empty
);
1000 visit_instructions(&sig
->body
);
1005 vec4_visitor::try_emit_sat(ir_expression
*ir
)
1007 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
1011 sat_src
->accept(this);
1012 src_reg src
= this->result
;
1014 this->result
= src_reg(this, ir
->type
);
1015 vec4_instruction
*inst
;
1016 inst
= emit(MOV(dst_reg(this->result
), src
));
1017 inst
->saturate
= true;
1023 vec4_visitor::emit_bool_comparison(unsigned int op
,
1024 dst_reg dst
, src_reg src0
, src_reg src1
)
1026 /* original gen4 does destination conversion before comparison. */
1028 dst
.type
= src0
.type
;
1030 emit(CMP(dst
, src0
, src1
, brw_conditional_for_comparison(op
)));
1032 dst
.type
= BRW_REGISTER_TYPE_D
;
1033 emit(AND(dst
, src_reg(dst
), src_reg(0x1)));
1037 vec4_visitor::visit(ir_expression
*ir
)
1039 unsigned int operand
;
1040 src_reg op
[Elements(ir
->operands
)];
1043 vec4_instruction
*inst
;
1045 if (try_emit_sat(ir
))
1048 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1049 this->result
.file
= BAD_FILE
;
1050 ir
->operands
[operand
]->accept(this);
1051 if (this->result
.file
== BAD_FILE
) {
1052 printf("Failed to get tree for expression operand:\n");
1053 ir
->operands
[operand
]->print();
1056 op
[operand
] = this->result
;
1058 /* Matrix expression operands should have been broken down to vector
1059 * operations already.
1061 assert(!ir
->operands
[operand
]->type
->is_matrix());
1064 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1065 if (ir
->operands
[1]) {
1066 vector_elements
= MAX2(vector_elements
,
1067 ir
->operands
[1]->type
->vector_elements
);
1070 this->result
.file
= BAD_FILE
;
1072 /* Storage for our result. Ideally for an assignment we'd be using
1073 * the actual storage for the result here, instead.
1075 result_src
= src_reg(this, ir
->type
);
1076 /* convenience for the emit functions below. */
1077 result_dst
= dst_reg(result_src
);
1078 /* If nothing special happens, this is the result. */
1079 this->result
= result_src
;
1080 /* Limit writes to the channels that will be used by result_src later.
1081 * This does limit this temp's use as a temporary for multi-instruction
1084 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1086 switch (ir
->operation
) {
1087 case ir_unop_logic_not
:
1088 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
1089 * ones complement of the whole register, not just bit 0.
1091 emit(XOR(result_dst
, op
[0], src_reg(1)));
1094 op
[0].negate
= !op
[0].negate
;
1095 this->result
= op
[0];
1099 op
[0].negate
= false;
1100 this->result
= op
[0];
1104 emit(MOV(result_dst
, src_reg(0.0f
)));
1106 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_G
));
1107 inst
= emit(MOV(result_dst
, src_reg(1.0f
)));
1108 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1110 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_L
));
1111 inst
= emit(MOV(result_dst
, src_reg(-1.0f
)));
1112 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1117 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1121 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1124 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1128 assert(!"not reached: should be handled by ir_explog_to_explog2");
1131 case ir_unop_sin_reduced
:
1132 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1135 case ir_unop_cos_reduced
:
1136 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1141 assert(!"derivatives not valid in vertex shader");
1145 assert(!"not reached: should be handled by lower_noise");
1149 emit(ADD(result_dst
, op
[0], op
[1]));
1152 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1156 if (ir
->type
->is_integer()) {
1157 /* For integer multiplication, the MUL uses the low 16 bits
1158 * of one of the operands (src0 on gen6, src1 on gen7). The
1159 * MACH accumulates in the contribution of the upper 16 bits
1162 * FINISHME: Emit just the MUL if we know an operand is small
1165 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
1167 emit(MUL(acc
, op
[0], op
[1]));
1168 emit(MACH(dst_null_d(), op
[0], op
[1]));
1169 emit(MOV(result_dst
, src_reg(acc
)));
1171 emit(MUL(result_dst
, op
[0], op
[1]));
1175 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1176 assert(ir
->type
->is_integer());
1177 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1180 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1181 assert(ir
->type
->is_integer());
1182 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1186 case ir_binop_greater
:
1187 case ir_binop_lequal
:
1188 case ir_binop_gequal
:
1189 case ir_binop_equal
:
1190 case ir_binop_nequal
: {
1191 emit(CMP(result_dst
, op
[0], op
[1],
1192 brw_conditional_for_comparison(ir
->operation
)));
1193 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1197 case ir_binop_all_equal
:
1198 /* "==" operator producing a scalar boolean. */
1199 if (ir
->operands
[0]->type
->is_vector() ||
1200 ir
->operands
[1]->type
->is_vector()) {
1201 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1202 emit(MOV(result_dst
, src_reg(0)));
1203 inst
= emit(MOV(result_dst
, src_reg(1)));
1204 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1206 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1207 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1210 case ir_binop_any_nequal
:
1211 /* "!=" operator producing a scalar boolean. */
1212 if (ir
->operands
[0]->type
->is_vector() ||
1213 ir
->operands
[1]->type
->is_vector()) {
1214 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1216 emit(MOV(result_dst
, src_reg(0)));
1217 inst
= emit(MOV(result_dst
, src_reg(1)));
1218 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1220 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1221 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1226 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1227 emit(MOV(result_dst
, src_reg(0)));
1229 inst
= emit(MOV(result_dst
, src_reg(1)));
1230 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1233 case ir_binop_logic_xor
:
1234 emit(XOR(result_dst
, op
[0], op
[1]));
1237 case ir_binop_logic_or
:
1238 emit(OR(result_dst
, op
[0], op
[1]));
1241 case ir_binop_logic_and
:
1242 emit(AND(result_dst
, op
[0], op
[1]));
1246 assert(ir
->operands
[0]->type
->is_vector());
1247 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1248 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1252 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1255 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1264 emit(MOV(result_dst
, op
[0]));
1268 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1269 emit(AND(result_dst
, result_src
, src_reg(1)));
1274 emit(RNDZ(result_dst
, op
[0]));
1277 op
[0].negate
= !op
[0].negate
;
1278 inst
= emit(RNDD(result_dst
, op
[0]));
1279 this->result
.negate
= true;
1282 inst
= emit(RNDD(result_dst
, op
[0]));
1285 inst
= emit(FRC(result_dst
, op
[0]));
1287 case ir_unop_round_even
:
1288 emit(RNDE(result_dst
, op
[0]));
1292 if (intel
->gen
>= 6) {
1293 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1294 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1296 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_L
));
1298 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1299 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1303 if (intel
->gen
>= 6) {
1304 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1305 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1307 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_G
));
1309 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1310 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1315 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1318 case ir_unop_bit_not
:
1319 inst
= emit(NOT(result_dst
, op
[0]));
1321 case ir_binop_bit_and
:
1322 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1324 case ir_binop_bit_xor
:
1325 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1327 case ir_binop_bit_or
:
1328 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1331 case ir_binop_lshift
:
1332 inst
= emit(BRW_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
1335 case ir_binop_rshift
:
1336 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1337 inst
= emit(BRW_OPCODE_ASR
, result_dst
, op
[0], op
[1]);
1339 inst
= emit(BRW_OPCODE_SHR
, result_dst
, op
[0], op
[1]);
1342 case ir_quadop_vector
:
1343 assert(!"not reached: should be handled by lower_quadop_vector");
1350 vec4_visitor::visit(ir_swizzle
*ir
)
1356 /* Note that this is only swizzles in expressions, not those on the left
1357 * hand side of an assignment, which do write masking. See ir_assignment
1361 ir
->val
->accept(this);
1363 assert(src
.file
!= BAD_FILE
);
1365 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1368 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1371 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1374 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1377 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1381 for (; i
< 4; i
++) {
1382 /* Replicate the last channel out. */
1383 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1386 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1392 vec4_visitor::visit(ir_dereference_variable
*ir
)
1394 const struct glsl_type
*type
= ir
->type
;
1395 dst_reg
*reg
= variable_storage(ir
->var
);
1398 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1399 this->result
= src_reg(brw_null_reg());
1403 this->result
= src_reg(*reg
);
1405 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1406 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1410 vec4_visitor::visit(ir_dereference_array
*ir
)
1412 ir_constant
*constant_index
;
1414 int element_size
= type_size(ir
->type
);
1416 constant_index
= ir
->array_index
->constant_expression_value();
1418 ir
->array
->accept(this);
1421 if (constant_index
) {
1422 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
1424 /* Variable index array dereference. It eats the "vec4" of the
1425 * base of the array and an index that offsets the Mesa register
1428 ir
->array_index
->accept(this);
1432 if (element_size
== 1) {
1433 index_reg
= this->result
;
1435 index_reg
= src_reg(this, glsl_type::int_type
);
1437 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(element_size
)));
1441 src_reg temp
= src_reg(this, glsl_type::int_type
);
1443 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1448 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1449 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1452 /* If the type is smaller than a vec4, replicate the last channel out. */
1453 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1454 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1456 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1457 src
.type
= brw_type_for_base_type(ir
->type
);
1463 vec4_visitor::visit(ir_dereference_record
*ir
)
1466 const glsl_type
*struct_type
= ir
->record
->type
;
1469 ir
->record
->accept(this);
1471 for (i
= 0; i
< struct_type
->length
; i
++) {
1472 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1474 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1477 /* If the type is smaller than a vec4, replicate the last channel out. */
1478 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1479 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1481 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1482 this->result
.type
= brw_type_for_base_type(ir
->type
);
1484 this->result
.reg_offset
+= offset
;
1488 * We want to be careful in assignment setup to hit the actual storage
1489 * instead of potentially using a temporary like we might with the
1490 * ir_dereference handler.
1493 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1495 /* The LHS must be a dereference. If the LHS is a variable indexed array
1496 * access of a vector, it must be separated into a series conditional moves
1497 * before reaching this point (see ir_vec_index_to_cond_assign).
1499 assert(ir
->as_dereference());
1500 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1502 assert(!deref_array
->array
->type
->is_vector());
1505 /* Use the rvalue deref handler for the most part. We'll ignore
1506 * swizzles in it and write swizzles using writemask, though.
1509 return dst_reg(v
->result
);
1513 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1514 const struct glsl_type
*type
, uint32_t predicate
)
1516 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1517 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1518 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
1523 if (type
->is_array()) {
1524 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1525 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
1530 if (type
->is_matrix()) {
1531 const struct glsl_type
*vec_type
;
1533 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1534 type
->vector_elements
, 1);
1536 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1537 emit_block_move(dst
, src
, vec_type
, predicate
);
1542 assert(type
->is_scalar() || type
->is_vector());
1544 dst
->type
= brw_type_for_base_type(type
);
1545 src
->type
= dst
->type
;
1547 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1549 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1551 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
1552 inst
->predicate
= predicate
;
1559 /* If the RHS processing resulted in an instruction generating a
1560 * temporary value, and it would be easy to rewrite the instruction to
1561 * generate its result right into the LHS instead, do so. This ends
1562 * up reliably removing instructions where it can be tricky to do so
1563 * later without real UD chain information.
1566 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1569 vec4_instruction
*pre_rhs_inst
,
1570 vec4_instruction
*last_rhs_inst
)
1572 /* This could be supported, but it would take more smarts. */
1576 if (pre_rhs_inst
== last_rhs_inst
)
1577 return false; /* No instructions generated to work with. */
1579 /* Make sure the last instruction generated our source reg. */
1580 if (src
.file
!= GRF
||
1581 src
.file
!= last_rhs_inst
->dst
.file
||
1582 src
.reg
!= last_rhs_inst
->dst
.reg
||
1583 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
1587 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
1590 /* Check that that last instruction fully initialized the channels
1591 * we want to use, in the order we want to use them. We could
1592 * potentially reswizzle the operands of many instructions so that
1593 * we could handle out of order channels, but don't yet.
1596 for (unsigned i
= 0; i
< 4; i
++) {
1597 if (dst
.writemask
& (1 << i
)) {
1598 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
1601 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
1606 /* Success! Rewrite the instruction. */
1607 last_rhs_inst
->dst
.file
= dst
.file
;
1608 last_rhs_inst
->dst
.reg
= dst
.reg
;
1609 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
1610 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
1611 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
1617 vec4_visitor::visit(ir_assignment
*ir
)
1619 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
1620 uint32_t predicate
= BRW_PREDICATE_NONE
;
1622 if (!ir
->lhs
->type
->is_scalar() &&
1623 !ir
->lhs
->type
->is_vector()) {
1624 ir
->rhs
->accept(this);
1625 src_reg src
= this->result
;
1627 if (ir
->condition
) {
1628 emit_bool_to_cond_code(ir
->condition
, &predicate
);
1631 /* emit_block_move doesn't account for swizzles in the source register.
1632 * This should be ok, since the source register is a structure or an
1633 * array, and those can't be swizzled. But double-check to be sure.
1635 assert(src
.swizzle
==
1636 (ir
->rhs
->type
->is_matrix()
1637 ? swizzle_for_size(ir
->rhs
->type
->vector_elements
)
1638 : BRW_SWIZZLE_NOOP
));
1640 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
1644 /* Now we're down to just a scalar/vector with writemasks. */
1647 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
1648 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1650 ir
->rhs
->accept(this);
1652 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1654 src_reg src
= this->result
;
1657 int first_enabled_chan
= 0;
1660 assert(ir
->lhs
->type
->is_vector() ||
1661 ir
->lhs
->type
->is_scalar());
1662 dst
.writemask
= ir
->write_mask
;
1664 for (int i
= 0; i
< 4; i
++) {
1665 if (dst
.writemask
& (1 << i
)) {
1666 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
1671 /* Swizzle a small RHS vector into the channels being written.
1673 * glsl ir treats write_mask as dictating how many channels are
1674 * present on the RHS while in our instructions we need to make
1675 * those channels appear in the slots of the vec4 they're written to.
1677 for (int i
= 0; i
< 4; i
++) {
1678 if (dst
.writemask
& (1 << i
))
1679 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
1681 swizzles
[i
] = first_enabled_chan
;
1683 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
1684 swizzles
[2], swizzles
[3]);
1686 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
1690 if (ir
->condition
) {
1691 emit_bool_to_cond_code(ir
->condition
, &predicate
);
1694 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1695 vec4_instruction
*inst
= emit(MOV(dst
, src
));
1696 inst
->predicate
= predicate
;
1704 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
1706 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1707 foreach_list(node
, &ir
->components
) {
1708 ir_constant
*field_value
= (ir_constant
*)node
;
1710 emit_constant_values(dst
, field_value
);
1715 if (ir
->type
->is_array()) {
1716 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
1717 emit_constant_values(dst
, ir
->array_elements
[i
]);
1722 if (ir
->type
->is_matrix()) {
1723 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1724 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
1726 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
1727 dst
->writemask
= 1 << j
;
1728 dst
->type
= BRW_REGISTER_TYPE_F
;
1730 emit(MOV(*dst
, src_reg(vec
[j
])));
1737 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
1739 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1740 if (!(remaining_writemask
& (1 << i
)))
1743 dst
->writemask
= 1 << i
;
1744 dst
->type
= brw_type_for_base_type(ir
->type
);
1746 /* Find other components that match the one we're about to
1747 * write. Emits fewer instructions for things like vec4(0.5,
1750 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
1751 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1752 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
1753 dst
->writemask
|= (1 << j
);
1755 /* u, i, and f storage all line up, so no need for a
1756 * switch case for comparing each type.
1758 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
1759 dst
->writemask
|= (1 << j
);
1763 switch (ir
->type
->base_type
) {
1764 case GLSL_TYPE_FLOAT
:
1765 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
1768 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
1770 case GLSL_TYPE_UINT
:
1771 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
1773 case GLSL_TYPE_BOOL
:
1774 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
])));
1777 assert(!"Non-float/uint/int/bool constant");
1781 remaining_writemask
&= ~dst
->writemask
;
1787 vec4_visitor::visit(ir_constant
*ir
)
1789 dst_reg dst
= dst_reg(this, ir
->type
);
1790 this->result
= src_reg(dst
);
1792 emit_constant_values(&dst
, ir
);
1796 vec4_visitor::visit(ir_call
*ir
)
1798 assert(!"not reached");
1802 vec4_visitor::visit(ir_texture
*ir
)
1804 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &vp
->Base
);
1805 sampler
= vp
->Base
.SamplerUnits
[sampler
];
1807 /* Should be lowered by do_lower_texture_projection */
1808 assert(!ir
->projector
);
1810 vec4_instruction
*inst
= NULL
;
1814 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXL
);
1817 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXD
);
1820 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF
);
1823 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXS
);
1826 assert(!"TXB is not valid for vertex shaders.");
1829 /* Texel offsets go in the message header; Gen4 also requires headers. */
1830 inst
->header_present
= ir
->offset
|| intel
->gen
< 5;
1832 inst
->mlen
= inst
->header_present
+ 1; /* always at least one */
1833 inst
->sampler
= sampler
;
1834 inst
->dst
= dst_reg(this, ir
->type
);
1835 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
1837 if (ir
->offset
!= NULL
)
1838 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
1840 /* MRF for the first parameter */
1841 int param_base
= inst
->base_mrf
+ inst
->header_present
;
1843 if (ir
->op
== ir_txs
) {
1844 ir
->lod_info
.lod
->accept(this);
1845 int writemask
= intel
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
1846 emit(MOV(dst_reg(MRF
, param_base
, ir
->lod_info
.lod
->type
, writemask
),
1849 int i
, coord_mask
= 0, zero_mask
= 0;
1850 /* Load the coordinate */
1851 /* FINISHME: gl_clamp_mask and saturate */
1852 for (i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++)
1853 coord_mask
|= (1 << i
);
1855 zero_mask
|= (1 << i
);
1857 ir
->coordinate
->accept(this);
1858 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
1860 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
1862 /* Load the shadow comparitor */
1863 if (ir
->shadow_comparitor
) {
1864 ir
->shadow_comparitor
->accept(this);
1865 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
1871 /* Load the LOD info */
1872 if (ir
->op
== ir_txl
) {
1874 if (intel
->gen
>= 5) {
1875 mrf
= param_base
+ 1;
1876 if (ir
->shadow_comparitor
) {
1877 writemask
= WRITEMASK_Y
;
1878 /* mlen already incremented */
1880 writemask
= WRITEMASK_X
;
1883 } else /* intel->gen == 4 */ {
1885 writemask
= WRITEMASK_Z
;
1887 ir
->lod_info
.lod
->accept(this);
1888 emit(MOV(dst_reg(MRF
, mrf
, ir
->lod_info
.lod
->type
, writemask
),
1890 } else if (ir
->op
== ir_txf
) {
1891 ir
->lod_info
.lod
->accept(this);
1892 emit(MOV(dst_reg(MRF
, param_base
, ir
->lod_info
.lod
->type
, WRITEMASK_W
),
1894 } else if (ir
->op
== ir_txd
) {
1895 const glsl_type
*type
= ir
->lod_info
.grad
.dPdx
->type
;
1897 ir
->lod_info
.grad
.dPdx
->accept(this);
1898 src_reg dPdx
= this->result
;
1899 ir
->lod_info
.grad
.dPdy
->accept(this);
1900 src_reg dPdy
= this->result
;
1902 if (intel
->gen
>= 5) {
1903 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
1904 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
1905 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
1906 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
1909 if (ir
->type
->vector_elements
== 3) {
1910 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1911 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1912 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
1913 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
1916 } else /* intel->gen == 4 */ {
1917 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
1918 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
1926 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
1930 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, int sampler
)
1932 this->result
= orig_val
;
1934 int s
= c
->key
.tex
.swizzles
[sampler
];
1936 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
1937 || s
== SWIZZLE_NOOP
)
1940 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
1943 for (int i
= 0; i
< 4; i
++) {
1944 switch (GET_SWZ(s
, i
)) {
1946 zero_mask
|= (1 << i
);
1949 one_mask
|= (1 << i
);
1952 copy_mask
|= (1 << i
);
1953 swizzle
[i
] = GET_SWZ(s
, i
);
1958 this->result
= src_reg(this, ir
->type
);
1959 dst_reg
swizzled_result(this->result
);
1962 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1963 swizzled_result
.writemask
= copy_mask
;
1964 emit(MOV(swizzled_result
, orig_val
));
1968 swizzled_result
.writemask
= zero_mask
;
1969 emit(MOV(swizzled_result
, src_reg(0.0f
)));
1973 swizzled_result
.writemask
= one_mask
;
1974 emit(MOV(swizzled_result
, src_reg(1.0f
)));
1979 vec4_visitor::visit(ir_return
*ir
)
1981 assert(!"not reached");
1985 vec4_visitor::visit(ir_discard
*ir
)
1987 assert(!"not reached");
1991 vec4_visitor::visit(ir_if
*ir
)
1993 /* Don't point the annotation at the if statement, because then it plus
1994 * the then and else blocks get printed.
1996 this->base_ir
= ir
->condition
;
1998 if (intel
->gen
== 6) {
2002 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2003 emit(IF(predicate
));
2006 visit_instructions(&ir
->then_instructions
);
2008 if (!ir
->else_instructions
.is_empty()) {
2009 this->base_ir
= ir
->condition
;
2010 emit(BRW_OPCODE_ELSE
);
2012 visit_instructions(&ir
->else_instructions
);
2015 this->base_ir
= ir
->condition
;
2016 emit(BRW_OPCODE_ENDIF
);
2020 vec4_visitor::emit_ndc_computation()
2022 /* Get the position */
2023 src_reg pos
= src_reg(output_reg
[VERT_RESULT_HPOS
]);
2025 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
2026 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
2027 output_reg
[BRW_VERT_RESULT_NDC
] = ndc
;
2029 current_annotation
= "NDC";
2030 dst_reg ndc_w
= ndc
;
2031 ndc_w
.writemask
= WRITEMASK_W
;
2032 src_reg pos_w
= pos
;
2033 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2034 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
2036 dst_reg ndc_xyz
= ndc
;
2037 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
2039 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
2043 vec4_visitor::emit_psiz_and_flags(struct brw_reg reg
)
2045 if (intel
->gen
< 6 &&
2046 ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
2047 c
->key
.userclip_active
|| brw
->has_negative_rhw_bug
)) {
2048 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
2049 dst_reg header1_w
= header1
;
2050 header1_w
.writemask
= WRITEMASK_W
;
2053 emit(MOV(header1
, 0u));
2055 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
2056 src_reg psiz
= src_reg(output_reg
[VERT_RESULT_PSIZ
]);
2058 current_annotation
= "Point size";
2059 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
2060 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
2063 current_annotation
= "Clipping flags";
2064 for (i
= 0; i
< c
->key
.nr_userclip_plane_consts
; i
++) {
2065 vec4_instruction
*inst
;
2067 inst
= emit(DP4(dst_null_f(), src_reg(output_reg
[VERT_RESULT_HPOS
]),
2068 src_reg(this->userplane
[i
])));
2069 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
2071 inst
= emit(OR(header1_w
, src_reg(header1_w
), 1u << i
));
2072 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2075 /* i965 clipping workaround:
2076 * 1) Test for -ve rhw
2078 * set ndc = (0,0,0,0)
2081 * Later, clipping will detect ucp[6] and ensure the primitive is
2082 * clipped against all fixed planes.
2084 if (brw
->has_negative_rhw_bug
) {
2088 vec8(brw_null_reg()),
2090 brw_swizzle1(output_reg
[BRW_VERT_RESULT_NDC
], 3),
2093 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
2094 brw_MOV(p
, output_reg
[BRW_VERT_RESULT_NDC
], brw_imm_f(0));
2095 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2099 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
2100 } else if (intel
->gen
< 6) {
2101 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
2103 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
2104 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
2105 emit(MOV(brw_writemask(reg
, WRITEMASK_W
),
2106 src_reg(output_reg
[VERT_RESULT_PSIZ
])));
2112 vec4_visitor::emit_clip_distances(struct brw_reg reg
, int offset
)
2114 if (intel
->gen
< 6) {
2115 /* Clip distance slots are set aside in gen5, but they are not used. It
2116 * is not clear whether we actually need to set aside space for them,
2117 * but the performance cost is negligible.
2122 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
2124 * "If a linked set of shaders forming the vertex stage contains no
2125 * static write to gl_ClipVertex or gl_ClipDistance, but the
2126 * application has requested clipping against user clip planes through
2127 * the API, then the coordinate written to gl_Position is used for
2128 * comparison against the user clip planes."
2130 * This function is only called if the shader didn't write to
2131 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
2132 * if the user wrote to it; otherwise we use gl_Position.
2134 gl_vert_result clip_vertex
= VERT_RESULT_CLIP_VERTEX
;
2135 if (!(c
->prog_data
.outputs_written
2136 & BITFIELD64_BIT(VERT_RESULT_CLIP_VERTEX
))) {
2137 clip_vertex
= VERT_RESULT_HPOS
;
2140 for (int i
= 0; i
+ offset
< c
->key
.nr_userclip_plane_consts
&& i
< 4;
2142 emit(DP4(dst_reg(brw_writemask(reg
, 1 << i
)),
2143 src_reg(output_reg
[clip_vertex
]),
2144 src_reg(this->userplane
[i
+ offset
])));
2149 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int vert_result
)
2151 assert (vert_result
< VERT_RESULT_MAX
);
2152 reg
.type
= output_reg
[vert_result
].type
;
2153 current_annotation
= output_reg_annotation
[vert_result
];
2154 /* Copy the register, saturating if necessary */
2155 vec4_instruction
*inst
= emit(MOV(reg
,
2156 src_reg(output_reg
[vert_result
])));
2157 if ((vert_result
== VERT_RESULT_COL0
||
2158 vert_result
== VERT_RESULT_COL1
||
2159 vert_result
== VERT_RESULT_BFC0
||
2160 vert_result
== VERT_RESULT_BFC1
) &&
2161 c
->key
.clamp_vertex_color
) {
2162 inst
->saturate
= true;
2167 vec4_visitor::emit_urb_slot(int mrf
, int vert_result
)
2169 struct brw_reg hw_reg
= brw_message_reg(mrf
);
2170 dst_reg reg
= dst_reg(MRF
, mrf
);
2171 reg
.type
= BRW_REGISTER_TYPE_F
;
2173 switch (vert_result
) {
2174 case VERT_RESULT_PSIZ
:
2175 /* PSIZ is always in slot 0, and is coupled with other flags. */
2176 current_annotation
= "indices, point width, clip flags";
2177 emit_psiz_and_flags(hw_reg
);
2179 case BRW_VERT_RESULT_NDC
:
2180 current_annotation
= "NDC";
2181 emit(MOV(reg
, src_reg(output_reg
[BRW_VERT_RESULT_NDC
])));
2183 case BRW_VERT_RESULT_HPOS_DUPLICATE
:
2184 case VERT_RESULT_HPOS
:
2185 current_annotation
= "gl_Position";
2186 emit(MOV(reg
, src_reg(output_reg
[VERT_RESULT_HPOS
])));
2188 case VERT_RESULT_CLIP_DIST0
:
2189 case VERT_RESULT_CLIP_DIST1
:
2190 if (this->c
->key
.uses_clip_distance
) {
2191 emit_generic_urb_slot(reg
, vert_result
);
2193 current_annotation
= "user clip distances";
2194 emit_clip_distances(hw_reg
, (vert_result
- VERT_RESULT_CLIP_DIST0
) * 4);
2197 case BRW_VERT_RESULT_PAD
:
2198 /* No need to write to this slot */
2201 emit_generic_urb_slot(reg
, vert_result
);
2207 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
2209 struct intel_context
*intel
= &brw
->intel
;
2211 if (intel
->gen
>= 6) {
2212 /* URB data written (does not include the message header reg) must
2213 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
2214 * section 5.4.3.2.2: URB_INTERLEAVED.
2216 * URB entries are allocated on a multiple of 1024 bits, so an
2217 * extra 128 bits written here to make the end align to 256 is
2220 if ((mlen
% 2) != 1)
2228 * Generates the VUE payload plus the 1 or 2 URB write instructions to
2229 * complete the VS thread.
2231 * The VUE layout is documented in Volume 2a.
2234 vec4_visitor::emit_urb_writes()
2236 /* MRF 0 is reserved for the debugger, so start with message header
2241 /* In the process of generating our URB write message contents, we
2242 * may need to unspill a register or load from an array. Those
2243 * reads would use MRFs 14-15.
2245 int max_usable_mrf
= 13;
2247 /* The following assertion verifies that max_usable_mrf causes an
2248 * even-numbered amount of URB write data, which will meet gen6's
2249 * requirements for length alignment.
2251 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
2253 /* FINISHME: edgeflag */
2255 brw_compute_vue_map(&c
->vue_map
, intel
, c
->key
.userclip_active
,
2256 c
->prog_data
.outputs_written
);
2258 /* First mrf is the g0-based message header containing URB handles and such,
2259 * which is implied in VS_OPCODE_URB_WRITE.
2263 if (intel
->gen
< 6) {
2264 emit_ndc_computation();
2267 /* Set up the VUE data for the first URB write */
2269 for (slot
= 0; slot
< c
->vue_map
.num_slots
; ++slot
) {
2270 emit_urb_slot(mrf
++, c
->vue_map
.slot_to_vert_result
[slot
]);
2272 /* If this was max_usable_mrf, we can't fit anything more into this URB
2275 if (mrf
> max_usable_mrf
) {
2281 current_annotation
= "URB write";
2282 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
2283 inst
->base_mrf
= base_mrf
;
2284 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
2285 inst
->eot
= (slot
>= c
->vue_map
.num_slots
);
2287 /* Optional second URB write */
2291 for (; slot
< c
->vue_map
.num_slots
; ++slot
) {
2292 assert(mrf
< max_usable_mrf
);
2294 emit_urb_slot(mrf
++, c
->vue_map
.slot_to_vert_result
[slot
]);
2297 current_annotation
= "URB write";
2298 inst
= emit(VS_OPCODE_URB_WRITE
);
2299 inst
->base_mrf
= base_mrf
;
2300 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
2302 /* URB destination offset. In the previous write, we got MRFs
2303 * 2-13 minus the one header MRF, so 12 regs. URB offset is in
2304 * URB row increments, and each of our MRFs is half of one of
2305 * those, since we're doing interleaved writes.
2307 inst
->offset
= (max_usable_mrf
- base_mrf
) / 2;
2312 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
2313 src_reg
*reladdr
, int reg_offset
)
2315 /* Because we store the values to scratch interleaved like our
2316 * vertex data, we need to scale the vec4 index by 2.
2318 int message_header_scale
= 2;
2320 /* Pre-gen6, the message header uses byte offsets instead of vec4
2321 * (16-byte) offset units.
2324 message_header_scale
*= 16;
2327 src_reg index
= src_reg(this, glsl_type::int_type
);
2329 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
2330 emit_before(inst
, MUL(dst_reg(index
),
2331 index
, src_reg(message_header_scale
)));
2335 return src_reg(reg_offset
* message_header_scale
);
2340 vec4_visitor::get_pull_constant_offset(vec4_instruction
*inst
,
2341 src_reg
*reladdr
, int reg_offset
)
2344 src_reg index
= src_reg(this, glsl_type::int_type
);
2346 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
2348 /* Pre-gen6, the message header uses byte offsets instead of vec4
2349 * (16-byte) offset units.
2351 if (intel
->gen
< 6) {
2352 emit_before(inst
, MUL(dst_reg(index
), index
, src_reg(16)));
2357 int message_header_scale
= intel
->gen
< 6 ? 16 : 1;
2358 return src_reg(reg_offset
* message_header_scale
);
2363 * Emits an instruction before @inst to load the value named by @orig_src
2364 * from scratch space at @base_offset to @temp.
2367 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
2368 dst_reg temp
, src_reg orig_src
,
2371 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2372 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
2374 emit_before(inst
, SCRATCH_READ(temp
, index
));
2378 * Emits an instruction after @inst to store the value to be written
2379 * to @orig_dst to scratch space at @base_offset, from @temp.
2382 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
,
2383 src_reg temp
, dst_reg orig_dst
,
2386 int reg_offset
= base_offset
+ orig_dst
.reg_offset
;
2387 src_reg index
= get_scratch_offset(inst
, orig_dst
.reladdr
, reg_offset
);
2389 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
2390 orig_dst
.writemask
));
2391 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
2392 write
->predicate
= inst
->predicate
;
2393 write
->ir
= inst
->ir
;
2394 write
->annotation
= inst
->annotation
;
2395 inst
->insert_after(write
);
2399 * We can't generally support array access in GRF space, because a
2400 * single instruction's destination can only span 2 contiguous
2401 * registers. So, we send all GRF arrays that get variable index
2402 * access to scratch space.
2405 vec4_visitor::move_grf_array_access_to_scratch()
2407 int scratch_loc
[this->virtual_grf_count
];
2409 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
2410 scratch_loc
[i
] = -1;
2413 /* First, calculate the set of virtual GRFs that need to be punted
2414 * to scratch due to having any array access on them, and where in
2417 foreach_list(node
, &this->instructions
) {
2418 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2420 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
2421 scratch_loc
[inst
->dst
.reg
] == -1) {
2422 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
2423 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
] * 8 * 4;
2426 for (int i
= 0 ; i
< 3; i
++) {
2427 src_reg
*src
= &inst
->src
[i
];
2429 if (src
->file
== GRF
&& src
->reladdr
&&
2430 scratch_loc
[src
->reg
] == -1) {
2431 scratch_loc
[src
->reg
] = c
->last_scratch
;
2432 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
] * 8 * 4;
2437 /* Now, for anything that will be accessed through scratch, rewrite
2438 * it to load/store. Note that this is a _safe list walk, because
2439 * we may generate a new scratch_write instruction after the one
2442 foreach_list_safe(node
, &this->instructions
) {
2443 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2445 /* Set up the annotation tracking for new generated instructions. */
2447 current_annotation
= inst
->annotation
;
2449 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
2450 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
2452 emit_scratch_write(inst
, temp
, inst
->dst
, scratch_loc
[inst
->dst
.reg
]);
2454 inst
->dst
.file
= temp
.file
;
2455 inst
->dst
.reg
= temp
.reg
;
2456 inst
->dst
.reg_offset
= temp
.reg_offset
;
2457 inst
->dst
.reladdr
= NULL
;
2460 for (int i
= 0 ; i
< 3; i
++) {
2461 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
2464 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2466 emit_scratch_read(inst
, temp
, inst
->src
[i
],
2467 scratch_loc
[inst
->src
[i
].reg
]);
2469 inst
->src
[i
].file
= temp
.file
;
2470 inst
->src
[i
].reg
= temp
.reg
;
2471 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2472 inst
->src
[i
].reladdr
= NULL
;
2478 * Emits an instruction before @inst to load the value named by @orig_src
2479 * from the pull constant buffer (surface) at @base_offset to @temp.
2482 vec4_visitor::emit_pull_constant_load(vec4_instruction
*inst
,
2483 dst_reg temp
, src_reg orig_src
,
2486 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2487 src_reg index
= get_pull_constant_offset(inst
, orig_src
.reladdr
, reg_offset
);
2488 vec4_instruction
*load
;
2490 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
2492 load
->base_mrf
= 14;
2494 emit_before(inst
, load
);
2498 * Implements array access of uniforms by inserting a
2499 * PULL_CONSTANT_LOAD instruction.
2501 * Unlike temporary GRF array access (where we don't support it due to
2502 * the difficulty of doing relative addressing on instruction
2503 * destinations), we could potentially do array access of uniforms
2504 * that were loaded in GRF space as push constants. In real-world
2505 * usage we've seen, though, the arrays being used are always larger
2506 * than we could load as push constants, so just always move all
2507 * uniform array access out to a pull constant buffer.
2510 vec4_visitor::move_uniform_array_access_to_pull_constants()
2512 int pull_constant_loc
[this->uniforms
];
2514 for (int i
= 0; i
< this->uniforms
; i
++) {
2515 pull_constant_loc
[i
] = -1;
2518 /* Walk through and find array access of uniforms. Put a copy of that
2519 * uniform in the pull constant buffer.
2521 * Note that we don't move constant-indexed accesses to arrays. No
2522 * testing has been done of the performance impact of this choice.
2524 foreach_list_safe(node
, &this->instructions
) {
2525 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2527 for (int i
= 0 ; i
< 3; i
++) {
2528 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
2531 int uniform
= inst
->src
[i
].reg
;
2533 /* If this array isn't already present in the pull constant buffer,
2536 if (pull_constant_loc
[uniform
] == -1) {
2537 const float **values
= &prog_data
->param
[uniform
* 4];
2539 pull_constant_loc
[uniform
] = prog_data
->nr_pull_params
/ 4;
2541 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
2542 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
2546 /* Set up the annotation tracking for new generated instructions. */
2548 current_annotation
= inst
->annotation
;
2550 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2552 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
2553 pull_constant_loc
[uniform
]);
2555 inst
->src
[i
].file
= temp
.file
;
2556 inst
->src
[i
].reg
= temp
.reg
;
2557 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2558 inst
->src
[i
].reladdr
= NULL
;
2562 /* Now there are no accesses of the UNIFORM file with a reladdr, so
2563 * no need to track them as larger-than-vec4 objects. This will be
2564 * relied on in cutting out unused uniform vectors from push
2567 split_uniform_registers();
2571 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
2573 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2577 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
2578 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
2582 vec4_visitor::vec4_visitor(struct brw_vs_compile
*c
,
2583 struct gl_shader_program
*prog
,
2584 struct brw_shader
*shader
)
2589 this->intel
= &brw
->intel
;
2590 this->ctx
= &intel
->ctx
;
2592 this->shader
= shader
;
2594 this->mem_ctx
= ralloc_context(NULL
);
2595 this->failed
= false;
2597 this->base_ir
= NULL
;
2598 this->current_annotation
= NULL
;
2601 this->vp
= (struct gl_vertex_program
*)
2602 prog
->_LinkedShaders
[MESA_SHADER_VERTEX
]->Program
;
2603 this->prog_data
= &c
->prog_data
;
2605 this->variable_ht
= hash_table_ctor(0,
2606 hash_table_pointer_hash
,
2607 hash_table_pointer_compare
);
2609 this->virtual_grf_def
= NULL
;
2610 this->virtual_grf_use
= NULL
;
2611 this->virtual_grf_sizes
= NULL
;
2612 this->virtual_grf_count
= 0;
2613 this->virtual_grf_reg_map
= NULL
;
2614 this->virtual_grf_reg_count
= 0;
2615 this->virtual_grf_array_size
= 0;
2616 this->live_intervals_valid
= false;
2621 vec4_visitor::~vec4_visitor()
2623 ralloc_free(this->mem_ctx
);
2624 hash_table_dtor(this->variable_ht
);
2629 vec4_visitor::fail(const char *format
, ...)
2639 va_start(va
, format
);
2640 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
2642 msg
= ralloc_asprintf(mem_ctx
, "VS compile failed: %s\n", msg
);
2644 this->fail_msg
= msg
;
2646 if (INTEL_DEBUG
& DEBUG_VS
) {
2647 fprintf(stderr
, "%s", msg
);
2651 } /* namespace brw */