2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "main/macros.h"
27 #include "program/prog_parameter.h"
32 src_reg::src_reg(dst_reg reg
)
36 this->file
= reg
.file
;
38 this->reg_offset
= reg
.reg_offset
;
39 this->type
= reg
.type
;
40 this->reladdr
= reg
.reladdr
;
41 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
47 for (int i
= 0; i
< 4; i
++) {
48 if (!(reg
.writemask
& (1 << i
)))
51 swizzles
[next_chan
++] = last
= i
;
54 for (; next_chan
< 4; next_chan
++) {
55 swizzles
[next_chan
] = last
;
58 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
59 swizzles
[2], swizzles
[3]);
62 dst_reg::dst_reg(src_reg reg
)
66 this->file
= reg
.file
;
68 this->reg_offset
= reg
.reg_offset
;
69 this->type
= reg
.type
;
70 this->writemask
= WRITEMASK_XYZW
;
71 this->reladdr
= reg
.reladdr
;
72 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
75 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
76 enum opcode opcode
, dst_reg dst
,
77 src_reg src0
, src_reg src1
, src_reg src2
)
79 this->opcode
= opcode
;
84 this->ir
= v
->base_ir
;
85 this->annotation
= v
->current_annotation
;
89 vec4_visitor::emit(vec4_instruction
*inst
)
91 this->instructions
.push_tail(inst
);
97 vec4_visitor::emit_before(vec4_instruction
*inst
, vec4_instruction
*new_inst
)
99 new_inst
->ir
= inst
->ir
;
100 new_inst
->annotation
= inst
->annotation
;
102 inst
->insert_before(new_inst
);
108 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
109 src_reg src0
, src_reg src1
, src_reg src2
)
111 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
117 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
119 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
123 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
125 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
129 vec4_visitor::emit(enum opcode opcode
)
131 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
136 vec4_visitor::op(dst_reg dst, src_reg src0) \
138 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
144 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \
146 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
165 /** Gen4 predicated IF. */
167 vec4_visitor::IF(uint32_t predicate
)
169 vec4_instruction
*inst
;
171 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
172 inst
->predicate
= predicate
;
177 /** Gen6+ IF with embedded comparison. */
179 vec4_visitor::IF(src_reg src0
, src_reg src1
, uint32_t condition
)
181 assert(intel
->gen
>= 6);
183 vec4_instruction
*inst
;
185 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
187 inst
->conditional_mod
= condition
;
193 * CMP: Sets the low bit of the destination channels with the result
194 * of the comparison, while the upper bits are undefined, and updates
195 * the flag register with the packed 16 bits of the result.
198 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
, uint32_t condition
)
200 vec4_instruction
*inst
;
202 /* original gen4 does type conversion to the destination type
203 * before before comparison, producing garbage results for floating
206 if (intel
->gen
== 4) {
207 dst
.type
= src0
.type
;
208 if (dst
.file
== HW_REG
)
209 dst
.fixed_hw_reg
.type
= dst
.type
;
212 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
, src0
, src1
);
213 inst
->conditional_mod
= condition
;
219 vec4_visitor::SCRATCH_READ(dst_reg dst
, src_reg index
)
221 vec4_instruction
*inst
;
223 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_READ
,
232 vec4_visitor::SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
)
234 vec4_instruction
*inst
;
236 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_WRITE
,
245 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
247 static enum opcode dot_opcodes
[] = {
248 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
251 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
255 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
257 /* The gen6 math instruction ignores the source modifiers --
258 * swizzle, abs, negate, and at least some parts of the register
259 * region description.
261 * While it would seem that this MOV could be avoided at this point
262 * in the case that the swizzle is matched up with the destination
263 * writemask, note that uniform packing and register allocation
264 * could rearrange our swizzle, so let's leave this matter up to
265 * copy propagation later.
267 src_reg temp_src
= src_reg(this, glsl_type::vec4_type
);
268 emit(MOV(dst_reg(temp_src
), src
));
270 if (dst
.writemask
!= WRITEMASK_XYZW
) {
271 /* The gen6 math instruction must be align1, so we can't do
274 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
276 emit(opcode
, temp_dst
, temp_src
);
278 emit(MOV(dst
, src_reg(temp_dst
)));
280 emit(opcode
, dst
, temp_src
);
285 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
287 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
293 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
296 case SHADER_OPCODE_RCP
:
297 case SHADER_OPCODE_RSQ
:
298 case SHADER_OPCODE_SQRT
:
299 case SHADER_OPCODE_EXP2
:
300 case SHADER_OPCODE_LOG2
:
301 case SHADER_OPCODE_SIN
:
302 case SHADER_OPCODE_COS
:
305 assert(!"not reached: bad math opcode");
309 if (intel
->gen
>= 6) {
310 return emit_math1_gen6(opcode
, dst
, src
);
312 return emit_math1_gen4(opcode
, dst
, src
);
317 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
318 dst_reg dst
, src_reg src0
, src_reg src1
)
322 /* The gen6 math instruction ignores the source modifiers --
323 * swizzle, abs, negate, and at least some parts of the register
324 * region description. Move the sources to temporaries to make it
328 expanded
= src_reg(this, glsl_type::vec4_type
);
329 emit(MOV(dst_reg(expanded
), src0
));
332 expanded
= src_reg(this, glsl_type::vec4_type
);
333 emit(MOV(dst_reg(expanded
), src1
));
336 if (dst
.writemask
!= WRITEMASK_XYZW
) {
337 /* The gen6 math instruction must be align1, so we can't do
340 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
342 emit(opcode
, temp_dst
, src0
, src1
);
344 emit(MOV(dst
, src_reg(temp_dst
)));
346 emit(opcode
, dst
, src0
, src1
);
351 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
352 dst_reg dst
, src_reg src0
, src_reg src1
)
354 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
360 vec4_visitor::emit_math(enum opcode opcode
,
361 dst_reg dst
, src_reg src0
, src_reg src1
)
363 assert(opcode
== SHADER_OPCODE_POW
);
365 if (intel
->gen
>= 6) {
366 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
368 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
373 vec4_visitor::visit_instructions(const exec_list
*list
)
375 foreach_list(node
, list
) {
376 ir_instruction
*ir
= (ir_instruction
*)node
;
385 type_size(const struct glsl_type
*type
)
390 switch (type
->base_type
) {
393 case GLSL_TYPE_FLOAT
:
395 if (type
->is_matrix()) {
396 return type
->matrix_columns
;
398 /* Regardless of size of vector, it gets a vec4. This is bad
399 * packing for things like floats, but otherwise arrays become a
400 * mess. Hopefully a later pass over the code can pack scalars
401 * down if appropriate.
405 case GLSL_TYPE_ARRAY
:
406 assert(type
->length
> 0);
407 return type_size(type
->fields
.array
) * type
->length
;
408 case GLSL_TYPE_STRUCT
:
410 for (i
= 0; i
< type
->length
; i
++) {
411 size
+= type_size(type
->fields
.structure
[i
].type
);
414 case GLSL_TYPE_SAMPLER
:
415 /* Samplers take up one slot in UNIFORMS[], but they're baked in
426 vec4_visitor::virtual_grf_alloc(int size
)
428 if (virtual_grf_array_size
<= virtual_grf_count
) {
429 if (virtual_grf_array_size
== 0)
430 virtual_grf_array_size
= 16;
432 virtual_grf_array_size
*= 2;
433 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
434 virtual_grf_array_size
);
435 virtual_grf_reg_map
= reralloc(mem_ctx
, virtual_grf_reg_map
, int,
436 virtual_grf_array_size
);
438 virtual_grf_reg_map
[virtual_grf_count
] = virtual_grf_reg_count
;
439 virtual_grf_reg_count
+= size
;
440 virtual_grf_sizes
[virtual_grf_count
] = size
;
441 return virtual_grf_count
++;
444 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
449 this->reg
= v
->virtual_grf_alloc(type_size(type
));
451 if (type
->is_array() || type
->is_record()) {
452 this->swizzle
= BRW_SWIZZLE_NOOP
;
454 this->swizzle
= swizzle_for_size(type
->vector_elements
);
457 this->type
= brw_type_for_base_type(type
);
460 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
465 this->reg
= v
->virtual_grf_alloc(type_size(type
));
467 if (type
->is_array() || type
->is_record()) {
468 this->writemask
= WRITEMASK_XYZW
;
470 this->writemask
= (1 << type
->vector_elements
) - 1;
473 this->type
= brw_type_for_base_type(type
);
476 /* Our support for uniforms is piggy-backed on the struct
477 * gl_fragment_program, because that's where the values actually
478 * get stored, rather than in some global gl_shader_program uniform
482 vec4_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
484 unsigned int offset
= 0;
485 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[loc
][0].f
;
487 if (type
->is_matrix()) {
488 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
489 type
->vector_elements
,
492 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
493 offset
+= setup_uniform_values(loc
+ offset
, column
);
499 switch (type
->base_type
) {
500 case GLSL_TYPE_FLOAT
:
504 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
505 c
->prog_data
.param
[this->uniforms
* 4 + i
] = &values
[i
];
508 /* Set up pad elements to get things aligned to a vec4 boundary. */
509 for (unsigned int i
= type
->vector_elements
; i
< 4; i
++) {
510 static float zero
= 0;
512 c
->prog_data
.param
[this->uniforms
* 4 + i
] = &zero
;
515 /* Track the size of this uniform vector, for future packing of
518 this->uniform_vector_size
[this->uniforms
] = type
->vector_elements
;
523 case GLSL_TYPE_STRUCT
:
524 for (unsigned int i
= 0; i
< type
->length
; i
++) {
525 offset
+= setup_uniform_values(loc
+ offset
,
526 type
->fields
.structure
[i
].type
);
530 case GLSL_TYPE_ARRAY
:
531 for (unsigned int i
= 0; i
< type
->length
; i
++) {
532 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
536 case GLSL_TYPE_SAMPLER
:
537 /* The sampler takes up a slot, but we don't use any values from it. */
541 assert(!"not reached");
547 vec4_visitor::setup_uniform_clipplane_values()
549 int compacted_clipplane_index
= 0;
550 for (int i
= 0; i
< MAX_CLIP_PLANES
; ++i
) {
551 if (ctx
->Transform
.ClipPlanesEnabled
& (1 << i
)) {
552 this->uniform_vector_size
[this->uniforms
] = 4;
553 this->userplane
[compacted_clipplane_index
] = dst_reg(UNIFORM
, this->uniforms
);
554 this->userplane
[compacted_clipplane_index
].type
= BRW_REGISTER_TYPE_F
;
555 for (int j
= 0; j
< 4; ++j
) {
556 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &ctx
->Transform
._ClipUserPlane
[i
][j
];
558 ++compacted_clipplane_index
;
564 /* Our support for builtin uniforms is even scarier than non-builtin.
565 * It sits on top of the PROG_STATE_VAR parameters that are
566 * automatically updated from GL context state.
569 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
571 const ir_state_slot
*const slots
= ir
->state_slots
;
572 assert(ir
->state_slots
!= NULL
);
574 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
575 /* This state reference has already been setup by ir_to_mesa,
576 * but we'll get the same index back here. We can reference
577 * ParameterValues directly, since unlike brw_fs.cpp, we never
578 * add new state references during compile.
580 int index
= _mesa_add_state_reference(this->vp
->Base
.Parameters
,
581 (gl_state_index
*)slots
[i
].tokens
);
582 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
584 this->uniform_vector_size
[this->uniforms
] = 0;
585 /* Add each of the unique swizzled channels of the element.
586 * This will end up matching the size of the glsl_type of this field.
589 for (unsigned int j
= 0; j
< 4; j
++) {
590 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
593 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &values
[swiz
];
594 if (swiz
<= last_swiz
)
595 this->uniform_vector_size
[this->uniforms
]++;
602 vec4_visitor::variable_storage(ir_variable
*var
)
604 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
608 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
)
610 ir_expression
*expr
= ir
->as_expression();
612 *predicate
= BRW_PREDICATE_NORMAL
;
616 vec4_instruction
*inst
;
618 assert(expr
->get_num_operands() <= 2);
619 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
620 expr
->operands
[i
]->accept(this);
621 op
[i
] = this->result
;
624 switch (expr
->operation
) {
625 case ir_unop_logic_not
:
626 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
627 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
630 case ir_binop_logic_xor
:
631 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
632 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
635 case ir_binop_logic_or
:
636 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
637 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
640 case ir_binop_logic_and
:
641 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
642 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
646 if (intel
->gen
>= 6) {
647 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
649 inst
= emit(MOV(dst_null_f(), op
[0]));
650 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
655 if (intel
->gen
>= 6) {
656 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
658 inst
= emit(MOV(dst_null_d(), op
[0]));
659 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
663 case ir_binop_all_equal
:
664 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
665 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
668 case ir_binop_any_nequal
:
669 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
670 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
674 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
675 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
678 case ir_binop_greater
:
679 case ir_binop_gequal
:
681 case ir_binop_lequal
:
683 case ir_binop_nequal
:
684 emit(CMP(dst_null_d(), op
[0], op
[1],
685 brw_conditional_for_comparison(expr
->operation
)));
689 assert(!"not reached");
697 if (intel
->gen
>= 6) {
698 vec4_instruction
*inst
= emit(AND(dst_null_d(),
699 this->result
, src_reg(1)));
700 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
702 vec4_instruction
*inst
= emit(MOV(dst_null_d(), this->result
));
703 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
708 * Emit a gen6 IF statement with the comparison folded into the IF
712 vec4_visitor::emit_if_gen6(ir_if
*ir
)
714 ir_expression
*expr
= ir
->condition
->as_expression();
720 assert(expr
->get_num_operands() <= 2);
721 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
722 expr
->operands
[i
]->accept(this);
723 op
[i
] = this->result
;
726 switch (expr
->operation
) {
727 case ir_unop_logic_not
:
728 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
731 case ir_binop_logic_xor
:
732 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
735 case ir_binop_logic_or
:
736 temp
= dst_reg(this, glsl_type::bool_type
);
737 emit(OR(temp
, op
[0], op
[1]));
738 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
741 case ir_binop_logic_and
:
742 temp
= dst_reg(this, glsl_type::bool_type
);
743 emit(AND(temp
, op
[0], op
[1]));
744 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
748 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
752 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
755 case ir_binop_greater
:
756 case ir_binop_gequal
:
758 case ir_binop_lequal
:
760 case ir_binop_nequal
:
761 emit(IF(op
[0], op
[1],
762 brw_conditional_for_comparison(expr
->operation
)));
765 case ir_binop_all_equal
:
766 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
767 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
770 case ir_binop_any_nequal
:
771 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
772 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
776 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
777 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
781 assert(!"not reached");
782 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
788 ir
->condition
->accept(this);
790 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
794 vec4_visitor::visit(ir_variable
*ir
)
798 if (variable_storage(ir
))
803 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->location
);
805 /* Do GL_FIXED rescaling for GLES2.0. Our GL_FIXED attributes
806 * come in as floating point conversions of the integer values.
808 for (int i
= ir
->location
; i
< ir
->location
+ type_size(ir
->type
); i
++) {
809 if (!c
->key
.gl_fixed_input_size
[i
])
813 dst
.writemask
= (1 << c
->key
.gl_fixed_input_size
[i
]) - 1;
814 emit(MUL(dst
, src_reg(dst
), src_reg(1.0f
/ 65536.0f
)));
819 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
821 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
822 output_reg
[ir
->location
+ i
] = *reg
;
823 output_reg
[ir
->location
+ i
].reg_offset
= i
;
824 output_reg
[ir
->location
+ i
].type
= BRW_REGISTER_TYPE_F
;
825 output_reg_annotation
[ir
->location
+ i
] = ir
->name
;
830 case ir_var_temporary
:
831 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
835 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
837 /* Track how big the whole uniform variable is, in case we need to put a
838 * copy of its data into pull constants for array access.
840 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
842 if (!strncmp(ir
->name
, "gl_", 3)) {
843 setup_builtin_uniform_values(ir
);
845 setup_uniform_values(ir
->location
, ir
->type
);
850 assert(!"not reached");
853 reg
->type
= brw_type_for_base_type(ir
->type
);
854 hash_table_insert(this->variable_ht
, reg
, ir
);
858 vec4_visitor::visit(ir_loop
*ir
)
862 /* We don't want debugging output to print the whole body of the
863 * loop as the annotation.
865 this->base_ir
= NULL
;
867 if (ir
->counter
!= NULL
) {
868 this->base_ir
= ir
->counter
;
869 ir
->counter
->accept(this);
870 counter
= *(variable_storage(ir
->counter
));
872 if (ir
->from
!= NULL
) {
873 this->base_ir
= ir
->from
;
874 ir
->from
->accept(this);
876 emit(MOV(counter
, this->result
));
883 this->base_ir
= ir
->to
;
884 ir
->to
->accept(this);
886 emit(CMP(dst_null_d(), src_reg(counter
), this->result
,
887 brw_conditional_for_comparison(ir
->cmp
)));
889 vec4_instruction
*inst
= emit(BRW_OPCODE_BREAK
);
890 inst
->predicate
= BRW_PREDICATE_NORMAL
;
893 visit_instructions(&ir
->body_instructions
);
897 this->base_ir
= ir
->increment
;
898 ir
->increment
->accept(this);
899 emit(ADD(counter
, src_reg(counter
), this->result
));
902 emit(BRW_OPCODE_WHILE
);
906 vec4_visitor::visit(ir_loop_jump
*ir
)
909 case ir_loop_jump::jump_break
:
910 emit(BRW_OPCODE_BREAK
);
912 case ir_loop_jump::jump_continue
:
913 emit(BRW_OPCODE_CONTINUE
);
920 vec4_visitor::visit(ir_function_signature
*ir
)
927 vec4_visitor::visit(ir_function
*ir
)
929 /* Ignore function bodies other than main() -- we shouldn't see calls to
930 * them since they should all be inlined.
932 if (strcmp(ir
->name
, "main") == 0) {
933 const ir_function_signature
*sig
;
936 sig
= ir
->matching_signature(&empty
);
940 visit_instructions(&sig
->body
);
945 vec4_visitor::try_emit_sat(ir_expression
*ir
)
947 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
951 sat_src
->accept(this);
952 src_reg src
= this->result
;
954 this->result
= src_reg(this, ir
->type
);
955 vec4_instruction
*inst
;
956 inst
= emit(MOV(dst_reg(this->result
), src
));
957 inst
->saturate
= true;
963 vec4_visitor::emit_bool_comparison(unsigned int op
,
964 dst_reg dst
, src_reg src0
, src_reg src1
)
966 /* original gen4 does destination conversion before comparison. */
968 dst
.type
= src0
.type
;
970 emit(CMP(dst
, src0
, src1
, brw_conditional_for_comparison(op
)));
972 dst
.type
= BRW_REGISTER_TYPE_D
;
973 emit(AND(dst
, src_reg(dst
), src_reg(0x1)));
977 vec4_visitor::visit(ir_expression
*ir
)
979 unsigned int operand
;
980 src_reg op
[Elements(ir
->operands
)];
983 vec4_instruction
*inst
;
985 if (try_emit_sat(ir
))
988 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
989 this->result
.file
= BAD_FILE
;
990 ir
->operands
[operand
]->accept(this);
991 if (this->result
.file
== BAD_FILE
) {
992 printf("Failed to get tree for expression operand:\n");
993 ir
->operands
[operand
]->print();
996 op
[operand
] = this->result
;
998 /* Matrix expression operands should have been broken down to vector
999 * operations already.
1001 assert(!ir
->operands
[operand
]->type
->is_matrix());
1004 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1005 if (ir
->operands
[1]) {
1006 vector_elements
= MAX2(vector_elements
,
1007 ir
->operands
[1]->type
->vector_elements
);
1010 this->result
.file
= BAD_FILE
;
1012 /* Storage for our result. Ideally for an assignment we'd be using
1013 * the actual storage for the result here, instead.
1015 result_src
= src_reg(this, ir
->type
);
1016 /* convenience for the emit functions below. */
1017 result_dst
= dst_reg(result_src
);
1018 /* If nothing special happens, this is the result. */
1019 this->result
= result_src
;
1020 /* Limit writes to the channels that will be used by result_src later.
1021 * This does limit this temp's use as a temporary for multi-instruction
1024 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1026 switch (ir
->operation
) {
1027 case ir_unop_logic_not
:
1028 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
1029 * ones complement of the whole register, not just bit 0.
1031 emit(XOR(result_dst
, op
[0], src_reg(1)));
1034 op
[0].negate
= !op
[0].negate
;
1035 this->result
= op
[0];
1039 op
[0].negate
= false;
1040 this->result
= op
[0];
1044 emit(MOV(result_dst
, src_reg(0.0f
)));
1046 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_G
));
1047 inst
= emit(MOV(result_dst
, src_reg(1.0f
)));
1048 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1050 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_L
));
1051 inst
= emit(MOV(result_dst
, src_reg(-1.0f
)));
1052 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1057 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1061 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1064 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1068 assert(!"not reached: should be handled by ir_explog_to_explog2");
1071 case ir_unop_sin_reduced
:
1072 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1075 case ir_unop_cos_reduced
:
1076 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1081 assert(!"derivatives not valid in vertex shader");
1085 assert(!"not reached: should be handled by lower_noise");
1089 emit(ADD(result_dst
, op
[0], op
[1]));
1092 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1096 if (ir
->type
->is_integer()) {
1097 /* For integer multiplication, the MUL uses the low 16 bits
1098 * of one of the operands (src0 on gen6, src1 on gen7). The
1099 * MACH accumulates in the contribution of the upper 16 bits
1102 * FINISHME: Emit just the MUL if we know an operand is small
1105 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
1107 emit(MUL(acc
, op
[0], op
[1]));
1108 emit(MACH(dst_null_d(), op
[0], op
[1]));
1109 emit(MOV(result_dst
, src_reg(acc
)));
1111 emit(MUL(result_dst
, op
[0], op
[1]));
1115 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1117 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1121 case ir_binop_greater
:
1122 case ir_binop_lequal
:
1123 case ir_binop_gequal
:
1124 case ir_binop_equal
:
1125 case ir_binop_nequal
: {
1126 emit(CMP(result_dst
, op
[0], op
[1],
1127 brw_conditional_for_comparison(ir
->operation
)));
1128 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1132 case ir_binop_all_equal
:
1133 /* "==" operator producing a scalar boolean. */
1134 if (ir
->operands
[0]->type
->is_vector() ||
1135 ir
->operands
[1]->type
->is_vector()) {
1136 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1137 emit(MOV(result_dst
, src_reg(0)));
1138 inst
= emit(MOV(result_dst
, src_reg(1)));
1139 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1141 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1142 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1145 case ir_binop_any_nequal
:
1146 /* "!=" operator producing a scalar boolean. */
1147 if (ir
->operands
[0]->type
->is_vector() ||
1148 ir
->operands
[1]->type
->is_vector()) {
1149 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1151 emit(MOV(result_dst
, src_reg(0)));
1152 inst
= emit(MOV(result_dst
, src_reg(1)));
1153 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1155 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1156 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1161 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1162 emit(MOV(result_dst
, src_reg(0)));
1164 inst
= emit(MOV(result_dst
, src_reg(1)));
1165 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1168 case ir_binop_logic_xor
:
1169 emit(XOR(result_dst
, op
[0], op
[1]));
1172 case ir_binop_logic_or
:
1173 emit(OR(result_dst
, op
[0], op
[1]));
1176 case ir_binop_logic_and
:
1177 emit(AND(result_dst
, op
[0], op
[1]));
1181 assert(ir
->operands
[0]->type
->is_vector());
1182 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1183 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1187 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1190 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1199 emit(MOV(result_dst
, op
[0]));
1203 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1204 emit(AND(result_dst
, result_src
, src_reg(1)));
1209 emit(RNDZ(result_dst
, op
[0]));
1212 op
[0].negate
= !op
[0].negate
;
1213 inst
= emit(RNDD(result_dst
, op
[0]));
1214 this->result
.negate
= true;
1217 inst
= emit(RNDD(result_dst
, op
[0]));
1220 inst
= emit(FRC(result_dst
, op
[0]));
1222 case ir_unop_round_even
:
1223 emit(RNDE(result_dst
, op
[0]));
1227 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_L
));
1229 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1230 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1233 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_G
));
1235 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1236 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1240 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1243 case ir_unop_bit_not
:
1244 inst
= emit(NOT(result_dst
, op
[0]));
1246 case ir_binop_bit_and
:
1247 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1249 case ir_binop_bit_xor
:
1250 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1252 case ir_binop_bit_or
:
1253 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1256 case ir_binop_lshift
:
1257 case ir_binop_rshift
:
1258 assert(!"GLSL 1.30 features unsupported");
1261 case ir_quadop_vector
:
1262 assert(!"not reached: should be handled by lower_quadop_vector");
1269 vec4_visitor::visit(ir_swizzle
*ir
)
1275 /* Note that this is only swizzles in expressions, not those on the left
1276 * hand side of an assignment, which do write masking. See ir_assignment
1280 ir
->val
->accept(this);
1282 assert(src
.file
!= BAD_FILE
);
1284 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1287 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1290 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1293 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1296 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1300 for (; i
< 4; i
++) {
1301 /* Replicate the last channel out. */
1302 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1305 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1311 vec4_visitor::visit(ir_dereference_variable
*ir
)
1313 const struct glsl_type
*type
= ir
->type
;
1314 dst_reg
*reg
= variable_storage(ir
->var
);
1317 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1318 this->result
= src_reg(brw_null_reg());
1322 this->result
= src_reg(*reg
);
1324 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1325 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1329 vec4_visitor::visit(ir_dereference_array
*ir
)
1331 ir_constant
*constant_index
;
1333 int element_size
= type_size(ir
->type
);
1335 constant_index
= ir
->array_index
->constant_expression_value();
1337 ir
->array
->accept(this);
1340 if (constant_index
) {
1341 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
1343 /* Variable index array dereference. It eats the "vec4" of the
1344 * base of the array and an index that offsets the Mesa register
1347 ir
->array_index
->accept(this);
1351 if (element_size
== 1) {
1352 index_reg
= this->result
;
1354 index_reg
= src_reg(this, glsl_type::int_type
);
1356 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(element_size
)));
1360 src_reg temp
= src_reg(this, glsl_type::int_type
);
1362 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1367 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1368 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1371 /* If the type is smaller than a vec4, replicate the last channel out. */
1372 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1373 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1375 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1376 src
.type
= brw_type_for_base_type(ir
->type
);
1382 vec4_visitor::visit(ir_dereference_record
*ir
)
1385 const glsl_type
*struct_type
= ir
->record
->type
;
1388 ir
->record
->accept(this);
1390 for (i
= 0; i
< struct_type
->length
; i
++) {
1391 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1393 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1396 /* If the type is smaller than a vec4, replicate the last channel out. */
1397 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1398 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1400 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1401 this->result
.type
= brw_type_for_base_type(ir
->type
);
1403 this->result
.reg_offset
+= offset
;
1407 * We want to be careful in assignment setup to hit the actual storage
1408 * instead of potentially using a temporary like we might with the
1409 * ir_dereference handler.
1412 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1414 /* The LHS must be a dereference. If the LHS is a variable indexed array
1415 * access of a vector, it must be separated into a series conditional moves
1416 * before reaching this point (see ir_vec_index_to_cond_assign).
1418 assert(ir
->as_dereference());
1419 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1421 assert(!deref_array
->array
->type
->is_vector());
1424 /* Use the rvalue deref handler for the most part. We'll ignore
1425 * swizzles in it and write swizzles using writemask, though.
1428 return dst_reg(v
->result
);
1432 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1433 const struct glsl_type
*type
, uint32_t predicate
)
1435 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1436 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1437 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
1442 if (type
->is_array()) {
1443 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1444 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
1449 if (type
->is_matrix()) {
1450 const struct glsl_type
*vec_type
;
1452 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1453 type
->vector_elements
, 1);
1455 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1456 emit_block_move(dst
, src
, vec_type
, predicate
);
1461 assert(type
->is_scalar() || type
->is_vector());
1463 dst
->type
= brw_type_for_base_type(type
);
1464 src
->type
= dst
->type
;
1466 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1468 /* Do we need to worry about swizzling a swizzle? */
1469 assert(src
->swizzle
= BRW_SWIZZLE_NOOP
);
1470 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1472 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
1473 inst
->predicate
= predicate
;
1480 /* If the RHS processing resulted in an instruction generating a
1481 * temporary value, and it would be easy to rewrite the instruction to
1482 * generate its result right into the LHS instead, do so. This ends
1483 * up reliably removing instructions where it can be tricky to do so
1484 * later without real UD chain information.
1487 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1490 vec4_instruction
*pre_rhs_inst
,
1491 vec4_instruction
*last_rhs_inst
)
1493 /* This could be supported, but it would take more smarts. */
1497 if (pre_rhs_inst
== last_rhs_inst
)
1498 return false; /* No instructions generated to work with. */
1500 /* Make sure the last instruction generated our source reg. */
1501 if (src
.file
!= GRF
||
1502 src
.file
!= last_rhs_inst
->dst
.file
||
1503 src
.reg
!= last_rhs_inst
->dst
.reg
||
1504 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
1508 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
1511 /* Check that that last instruction fully initialized the channels
1512 * we want to use, in the order we want to use them. We could
1513 * potentially reswizzle the operands of many instructions so that
1514 * we could handle out of order channels, but don't yet.
1516 for (int i
= 0; i
< 4; i
++) {
1517 if (dst
.writemask
& (1 << i
)) {
1518 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
1521 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
1526 /* Success! Rewrite the instruction. */
1527 last_rhs_inst
->dst
.file
= dst
.file
;
1528 last_rhs_inst
->dst
.reg
= dst
.reg
;
1529 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
1530 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
1531 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
1537 vec4_visitor::visit(ir_assignment
*ir
)
1539 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
1540 uint32_t predicate
= BRW_PREDICATE_NONE
;
1542 if (!ir
->lhs
->type
->is_scalar() &&
1543 !ir
->lhs
->type
->is_vector()) {
1544 ir
->rhs
->accept(this);
1545 src_reg src
= this->result
;
1547 if (ir
->condition
) {
1548 emit_bool_to_cond_code(ir
->condition
, &predicate
);
1551 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
1555 /* Now we're down to just a scalar/vector with writemasks. */
1558 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
1559 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1561 ir
->rhs
->accept(this);
1563 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1565 src_reg src
= this->result
;
1568 int first_enabled_chan
= 0;
1571 assert(ir
->lhs
->type
->is_vector() ||
1572 ir
->lhs
->type
->is_scalar());
1573 dst
.writemask
= ir
->write_mask
;
1575 for (int i
= 0; i
< 4; i
++) {
1576 if (dst
.writemask
& (1 << i
)) {
1577 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
1582 /* Swizzle a small RHS vector into the channels being written.
1584 * glsl ir treats write_mask as dictating how many channels are
1585 * present on the RHS while in our instructions we need to make
1586 * those channels appear in the slots of the vec4 they're written to.
1588 for (int i
= 0; i
< 4; i
++) {
1589 if (dst
.writemask
& (1 << i
))
1590 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
1592 swizzles
[i
] = first_enabled_chan
;
1594 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
1595 swizzles
[2], swizzles
[3]);
1597 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
1601 if (ir
->condition
) {
1602 emit_bool_to_cond_code(ir
->condition
, &predicate
);
1605 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1606 vec4_instruction
*inst
= emit(MOV(dst
, src
));
1607 inst
->predicate
= predicate
;
1615 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
1617 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1618 foreach_list(node
, &ir
->components
) {
1619 ir_constant
*field_value
= (ir_constant
*)node
;
1621 emit_constant_values(dst
, field_value
);
1626 if (ir
->type
->is_array()) {
1627 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
1628 emit_constant_values(dst
, ir
->array_elements
[i
]);
1633 if (ir
->type
->is_matrix()) {
1634 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1635 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
1636 dst
->writemask
= 1 << j
;
1637 dst
->type
= BRW_REGISTER_TYPE_F
;
1640 src_reg(ir
->value
.f
[i
* ir
->type
->vector_elements
+ j
])));
1647 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1648 dst
->writemask
= 1 << i
;
1649 dst
->type
= brw_type_for_base_type(ir
->type
);
1651 switch (ir
->type
->base_type
) {
1652 case GLSL_TYPE_FLOAT
:
1653 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
1656 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
1658 case GLSL_TYPE_UINT
:
1659 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
1661 case GLSL_TYPE_BOOL
:
1662 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
])));
1665 assert(!"Non-float/uint/int/bool constant");
1673 vec4_visitor::visit(ir_constant
*ir
)
1675 dst_reg dst
= dst_reg(this, ir
->type
);
1676 this->result
= src_reg(dst
);
1678 emit_constant_values(&dst
, ir
);
1682 vec4_visitor::visit(ir_call
*ir
)
1684 assert(!"not reached");
1688 vec4_visitor::visit(ir_texture
*ir
)
1690 /* FINISHME: Implement vertex texturing.
1692 * With 0 vertex samplers available, the linker will reject
1693 * programs that do vertex texturing, but after our visitor has
1696 this->result
= src_reg(this, glsl_type::vec4_type
);
1700 vec4_visitor::visit(ir_return
*ir
)
1702 assert(!"not reached");
1706 vec4_visitor::visit(ir_discard
*ir
)
1708 assert(!"not reached");
1712 vec4_visitor::visit(ir_if
*ir
)
1714 /* Don't point the annotation at the if statement, because then it plus
1715 * the then and else blocks get printed.
1717 this->base_ir
= ir
->condition
;
1719 if (intel
->gen
== 6) {
1723 emit_bool_to_cond_code(ir
->condition
, &predicate
);
1724 emit(IF(predicate
));
1727 visit_instructions(&ir
->then_instructions
);
1729 if (!ir
->else_instructions
.is_empty()) {
1730 this->base_ir
= ir
->condition
;
1731 emit(BRW_OPCODE_ELSE
);
1733 visit_instructions(&ir
->else_instructions
);
1736 this->base_ir
= ir
->condition
;
1737 emit(BRW_OPCODE_ENDIF
);
1741 vec4_visitor::emit_ndc_computation()
1743 /* Get the position */
1744 src_reg pos
= src_reg(output_reg
[VERT_RESULT_HPOS
]);
1746 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
1747 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
1748 output_reg
[BRW_VERT_RESULT_NDC
] = ndc
;
1750 current_annotation
= "NDC";
1751 dst_reg ndc_w
= ndc
;
1752 ndc_w
.writemask
= WRITEMASK_W
;
1753 src_reg pos_w
= pos
;
1754 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
1755 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
1757 dst_reg ndc_xyz
= ndc
;
1758 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
1760 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
1764 vec4_visitor::emit_psiz_and_flags(struct brw_reg reg
)
1766 if (intel
->gen
< 6 &&
1767 ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
1768 c
->key
.nr_userclip
|| brw
->has_negative_rhw_bug
)) {
1769 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
1772 emit(MOV(header1
, 0u));
1774 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1775 src_reg psiz
= src_reg(output_reg
[VERT_RESULT_PSIZ
]);
1777 current_annotation
= "Point size";
1778 header1
.writemask
= WRITEMASK_W
;
1779 emit(MUL(header1
, psiz
, src_reg((float)(1 << 11))));
1780 emit(AND(header1
, src_reg(header1
), 0x7ff << 8));
1783 current_annotation
= "Clipping flags";
1784 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1785 vec4_instruction
*inst
;
1787 inst
= emit(DP4(dst_null_f(), src_reg(output_reg
[VERT_RESULT_HPOS
]),
1788 src_reg(this->userplane
[i
])));
1789 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1791 emit(OR(header1
, src_reg(header1
), 1u << i
));
1792 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1795 /* i965 clipping workaround:
1796 * 1) Test for -ve rhw
1798 * set ndc = (0,0,0,0)
1801 * Later, clipping will detect ucp[6] and ensure the primitive is
1802 * clipped against all fixed planes.
1804 if (brw
->has_negative_rhw_bug
) {
1808 vec8(brw_null_reg()),
1810 brw_swizzle1(output_reg
[BRW_VERT_RESULT_NDC
], 3),
1813 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1814 brw_MOV(p
, output_reg
[BRW_VERT_RESULT_NDC
], brw_imm_f(0));
1815 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1819 header1
.writemask
= WRITEMASK_XYZW
;
1820 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
1821 } else if (intel
->gen
< 6) {
1822 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
1824 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
1825 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1826 emit(MOV(brw_writemask(reg
, WRITEMASK_W
),
1827 src_reg(output_reg
[VERT_RESULT_PSIZ
])));
1833 vec4_visitor::emit_clip_distances(struct brw_reg reg
, int offset
)
1835 if (intel
->gen
< 6) {
1836 /* Clip distance slots are set aside in gen5, but they are not used. It
1837 * is not clear whether we actually need to set aside space for them,
1838 * but the performance cost is negligible.
1843 for (int i
= 0; i
+ offset
< c
->key
.nr_userclip
&& i
< 4; ++i
) {
1844 emit(DP4(dst_reg(brw_writemask(reg
, 1 << i
)),
1845 src_reg(output_reg
[VERT_RESULT_HPOS
]),
1846 src_reg(this->userplane
[i
+ offset
])));
1851 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int vert_result
)
1853 assert (vert_result
< VERT_RESULT_MAX
);
1854 current_annotation
= output_reg_annotation
[vert_result
];
1855 /* Copy the register, saturating if necessary */
1856 vec4_instruction
*inst
= emit(MOV(reg
,
1857 src_reg(output_reg
[vert_result
])));
1858 if ((vert_result
== VERT_RESULT_COL0
||
1859 vert_result
== VERT_RESULT_COL1
||
1860 vert_result
== VERT_RESULT_BFC0
||
1861 vert_result
== VERT_RESULT_BFC1
) &&
1862 c
->key
.clamp_vertex_color
) {
1863 inst
->saturate
= true;
1868 vec4_visitor::emit_urb_slot(int mrf
, int vert_result
)
1870 struct brw_reg hw_reg
= brw_message_reg(mrf
);
1871 dst_reg reg
= dst_reg(MRF
, mrf
);
1872 reg
.type
= BRW_REGISTER_TYPE_F
;
1874 switch (vert_result
) {
1875 case VERT_RESULT_PSIZ
:
1876 /* PSIZ is always in slot 0, and is coupled with other flags. */
1877 current_annotation
= "indices, point width, clip flags";
1878 emit_psiz_and_flags(hw_reg
);
1880 case BRW_VERT_RESULT_NDC
:
1881 current_annotation
= "NDC";
1882 emit(MOV(reg
, src_reg(output_reg
[BRW_VERT_RESULT_NDC
])));
1884 case BRW_VERT_RESULT_HPOS_DUPLICATE
:
1885 case VERT_RESULT_HPOS
:
1886 current_annotation
= "gl_Position";
1887 emit(MOV(reg
, src_reg(output_reg
[VERT_RESULT_HPOS
])));
1889 case VERT_RESULT_CLIP_DIST0
:
1890 case VERT_RESULT_CLIP_DIST1
:
1891 if (this->c
->key
.uses_clip_distance
) {
1892 emit_generic_urb_slot(reg
, vert_result
);
1894 current_annotation
= "user clip distances";
1895 emit_clip_distances(hw_reg
, (vert_result
- VERT_RESULT_CLIP_DIST0
) * 4);
1898 case BRW_VERT_RESULT_PAD
:
1899 /* No need to write to this slot */
1902 emit_generic_urb_slot(reg
, vert_result
);
1908 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
1910 struct intel_context
*intel
= &brw
->intel
;
1912 if (intel
->gen
>= 6) {
1913 /* URB data written (does not include the message header reg) must
1914 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
1915 * section 5.4.3.2.2: URB_INTERLEAVED.
1917 * URB entries are allocated on a multiple of 1024 bits, so an
1918 * extra 128 bits written here to make the end align to 256 is
1921 if ((mlen
% 2) != 1)
1929 * Generates the VUE payload plus the 1 or 2 URB write instructions to
1930 * complete the VS thread.
1932 * The VUE layout is documented in Volume 2a.
1935 vec4_visitor::emit_urb_writes()
1937 /* MRF 0 is reserved for the debugger, so start with message header
1942 /* In the process of generating our URB write message contents, we
1943 * may need to unspill a register or load from an array. Those
1944 * reads would use MRFs 14-15.
1946 int max_usable_mrf
= 13;
1948 /* The following assertion verifies that max_usable_mrf causes an
1949 * even-numbered amount of URB write data, which will meet gen6's
1950 * requirements for length alignment.
1952 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
1954 /* FINISHME: edgeflag */
1956 brw_compute_vue_map(&c
->vue_map
, intel
, c
->key
.nr_userclip
,
1957 c
->prog_data
.outputs_written
);
1959 /* First mrf is the g0-based message header containing URB handles and such,
1960 * which is implied in VS_OPCODE_URB_WRITE.
1964 if (intel
->gen
< 6) {
1965 emit_ndc_computation();
1968 /* Set up the VUE data for the first URB write */
1970 for (slot
= 0; slot
< c
->vue_map
.num_slots
; ++slot
) {
1971 emit_urb_slot(mrf
++, c
->vue_map
.slot_to_vert_result
[slot
]);
1973 /* If this was max_usable_mrf, we can't fit anything more into this URB
1976 if (mrf
> max_usable_mrf
) {
1982 current_annotation
= "URB write";
1983 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
1984 inst
->base_mrf
= base_mrf
;
1985 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
1986 inst
->eot
= (slot
>= c
->vue_map
.num_slots
);
1988 /* Optional second URB write */
1992 for (; slot
< c
->vue_map
.num_slots
; ++slot
) {
1993 assert(mrf
< max_usable_mrf
);
1995 emit_urb_slot(mrf
++, c
->vue_map
.slot_to_vert_result
[slot
]);
1998 current_annotation
= "URB write";
1999 inst
= emit(VS_OPCODE_URB_WRITE
);
2000 inst
->base_mrf
= base_mrf
;
2001 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
2003 /* URB destination offset. In the previous write, we got MRFs
2004 * 2-13 minus the one header MRF, so 12 regs. URB offset is in
2005 * URB row increments, and each of our MRFs is half of one of
2006 * those, since we're doing interleaved writes.
2008 inst
->offset
= (max_usable_mrf
- base_mrf
) / 2;
2011 if (intel
->gen
== 6)
2012 c
->prog_data
.urb_entry_size
= ALIGN(c
->vue_map
.num_slots
, 8) / 8;
2014 c
->prog_data
.urb_entry_size
= ALIGN(c
->vue_map
.num_slots
, 4) / 4;
2018 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
2019 src_reg
*reladdr
, int reg_offset
)
2021 /* Because we store the values to scratch interleaved like our
2022 * vertex data, we need to scale the vec4 index by 2.
2024 int message_header_scale
= 2;
2026 /* Pre-gen6, the message header uses byte offsets instead of vec4
2027 * (16-byte) offset units.
2030 message_header_scale
*= 16;
2033 src_reg index
= src_reg(this, glsl_type::int_type
);
2035 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
2036 emit_before(inst
, MUL(dst_reg(index
),
2037 index
, src_reg(message_header_scale
)));
2041 return src_reg(reg_offset
* message_header_scale
);
2046 vec4_visitor::get_pull_constant_offset(vec4_instruction
*inst
,
2047 src_reg
*reladdr
, int reg_offset
)
2050 src_reg index
= src_reg(this, glsl_type::int_type
);
2052 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
2054 /* Pre-gen6, the message header uses byte offsets instead of vec4
2055 * (16-byte) offset units.
2057 if (intel
->gen
< 6) {
2058 emit_before(inst
, MUL(dst_reg(index
), index
, src_reg(16)));
2063 int message_header_scale
= intel
->gen
< 6 ? 16 : 1;
2064 return src_reg(reg_offset
* message_header_scale
);
2069 * Emits an instruction before @inst to load the value named by @orig_src
2070 * from scratch space at @base_offset to @temp.
2073 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
2074 dst_reg temp
, src_reg orig_src
,
2077 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2078 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
2080 emit_before(inst
, SCRATCH_READ(temp
, index
));
2084 * Emits an instruction after @inst to store the value to be written
2085 * to @orig_dst to scratch space at @base_offset, from @temp.
2088 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
,
2089 src_reg temp
, dst_reg orig_dst
,
2092 int reg_offset
= base_offset
+ orig_dst
.reg_offset
;
2093 src_reg index
= get_scratch_offset(inst
, orig_dst
.reladdr
, reg_offset
);
2095 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
2096 orig_dst
.writemask
));
2097 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
2098 write
->predicate
= inst
->predicate
;
2099 write
->ir
= inst
->ir
;
2100 write
->annotation
= inst
->annotation
;
2101 inst
->insert_after(write
);
2105 * We can't generally support array access in GRF space, because a
2106 * single instruction's destination can only span 2 contiguous
2107 * registers. So, we send all GRF arrays that get variable index
2108 * access to scratch space.
2111 vec4_visitor::move_grf_array_access_to_scratch()
2113 int scratch_loc
[this->virtual_grf_count
];
2115 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
2116 scratch_loc
[i
] = -1;
2119 /* First, calculate the set of virtual GRFs that need to be punted
2120 * to scratch due to having any array access on them, and where in
2123 foreach_list(node
, &this->instructions
) {
2124 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2126 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
2127 scratch_loc
[inst
->dst
.reg
] == -1) {
2128 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
2129 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
] * 8 * 4;
2132 for (int i
= 0 ; i
< 3; i
++) {
2133 src_reg
*src
= &inst
->src
[i
];
2135 if (src
->file
== GRF
&& src
->reladdr
&&
2136 scratch_loc
[src
->reg
] == -1) {
2137 scratch_loc
[src
->reg
] = c
->last_scratch
;
2138 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
] * 8 * 4;
2143 /* Now, for anything that will be accessed through scratch, rewrite
2144 * it to load/store. Note that this is a _safe list walk, because
2145 * we may generate a new scratch_write instruction after the one
2148 foreach_list_safe(node
, &this->instructions
) {
2149 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2151 /* Set up the annotation tracking for new generated instructions. */
2153 current_annotation
= inst
->annotation
;
2155 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
2156 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
2158 emit_scratch_write(inst
, temp
, inst
->dst
, scratch_loc
[inst
->dst
.reg
]);
2160 inst
->dst
.file
= temp
.file
;
2161 inst
->dst
.reg
= temp
.reg
;
2162 inst
->dst
.reg_offset
= temp
.reg_offset
;
2163 inst
->dst
.reladdr
= NULL
;
2166 for (int i
= 0 ; i
< 3; i
++) {
2167 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
2170 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2172 emit_scratch_read(inst
, temp
, inst
->src
[i
],
2173 scratch_loc
[inst
->src
[i
].reg
]);
2175 inst
->src
[i
].file
= temp
.file
;
2176 inst
->src
[i
].reg
= temp
.reg
;
2177 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2178 inst
->src
[i
].reladdr
= NULL
;
2184 * Emits an instruction before @inst to load the value named by @orig_src
2185 * from the pull constant buffer (surface) at @base_offset to @temp.
2188 vec4_visitor::emit_pull_constant_load(vec4_instruction
*inst
,
2189 dst_reg temp
, src_reg orig_src
,
2192 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2193 src_reg index
= get_pull_constant_offset(inst
, orig_src
.reladdr
, reg_offset
);
2194 vec4_instruction
*load
;
2196 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
2198 load
->base_mrf
= 14;
2200 emit_before(inst
, load
);
2204 * Implements array access of uniforms by inserting a
2205 * PULL_CONSTANT_LOAD instruction.
2207 * Unlike temporary GRF array access (where we don't support it due to
2208 * the difficulty of doing relative addressing on instruction
2209 * destinations), we could potentially do array access of uniforms
2210 * that were loaded in GRF space as push constants. In real-world
2211 * usage we've seen, though, the arrays being used are always larger
2212 * than we could load as push constants, so just always move all
2213 * uniform array access out to a pull constant buffer.
2216 vec4_visitor::move_uniform_array_access_to_pull_constants()
2218 int pull_constant_loc
[this->uniforms
];
2220 for (int i
= 0; i
< this->uniforms
; i
++) {
2221 pull_constant_loc
[i
] = -1;
2224 /* Walk through and find array access of uniforms. Put a copy of that
2225 * uniform in the pull constant buffer.
2227 * Note that we don't move constant-indexed accesses to arrays. No
2228 * testing has been done of the performance impact of this choice.
2230 foreach_list_safe(node
, &this->instructions
) {
2231 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2233 for (int i
= 0 ; i
< 3; i
++) {
2234 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
2237 int uniform
= inst
->src
[i
].reg
;
2239 /* If this array isn't already present in the pull constant buffer,
2242 if (pull_constant_loc
[uniform
] == -1) {
2243 const float **values
= &prog_data
->param
[uniform
* 4];
2245 pull_constant_loc
[uniform
] = prog_data
->nr_pull_params
/ 4;
2247 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
2248 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
2252 /* Set up the annotation tracking for new generated instructions. */
2254 current_annotation
= inst
->annotation
;
2256 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2258 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
2259 pull_constant_loc
[uniform
]);
2261 inst
->src
[i
].file
= temp
.file
;
2262 inst
->src
[i
].reg
= temp
.reg
;
2263 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2264 inst
->src
[i
].reladdr
= NULL
;
2268 /* Now there are no accesses of the UNIFORM file with a reladdr, so
2269 * no need to track them as larger-than-vec4 objects. This will be
2270 * relied on in cutting out unused uniform vectors from push
2273 split_uniform_registers();
2276 vec4_visitor::vec4_visitor(struct brw_vs_compile
*c
,
2277 struct gl_shader_program
*prog
,
2278 struct brw_shader
*shader
)
2283 this->intel
= &brw
->intel
;
2284 this->ctx
= &intel
->ctx
;
2286 this->shader
= shader
;
2288 this->mem_ctx
= ralloc_context(NULL
);
2289 this->failed
= false;
2291 this->base_ir
= NULL
;
2292 this->current_annotation
= NULL
;
2295 this->vp
= prog
->VertexProgram
;
2296 this->prog_data
= &c
->prog_data
;
2298 this->variable_ht
= hash_table_ctor(0,
2299 hash_table_pointer_hash
,
2300 hash_table_pointer_compare
);
2302 this->virtual_grf_def
= NULL
;
2303 this->virtual_grf_use
= NULL
;
2304 this->virtual_grf_sizes
= NULL
;
2305 this->virtual_grf_count
= 0;
2306 this->virtual_grf_reg_map
= NULL
;
2307 this->virtual_grf_reg_count
= 0;
2308 this->virtual_grf_array_size
= 0;
2309 this->live_intervals_valid
= false;
2313 this->variable_ht
= hash_table_ctor(0,
2314 hash_table_pointer_hash
,
2315 hash_table_pointer_compare
);
2318 vec4_visitor::~vec4_visitor()
2320 ralloc_free(this->mem_ctx
);
2321 hash_table_dtor(this->variable_ht
);
2326 vec4_visitor::fail(const char *format
, ...)
2336 va_start(va
, format
);
2337 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
2339 msg
= ralloc_asprintf(mem_ctx
, "VS compile failed: %s\n", msg
);
2341 this->fail_msg
= msg
;
2343 if (INTEL_DEBUG
& DEBUG_VS
) {
2344 fprintf(stderr
, "%s", msg
);
2348 } /* namespace brw */