2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "main/macros.h"
27 #include "program/prog_parameter.h"
32 src_reg::src_reg(dst_reg reg
)
36 this->file
= reg
.file
;
38 this->reg_offset
= reg
.reg_offset
;
39 this->type
= reg
.type
;
40 this->reladdr
= reg
.reladdr
;
41 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
47 for (int i
= 0; i
< 4; i
++) {
48 if (!(reg
.writemask
& (1 << i
)))
51 swizzles
[next_chan
++] = last
= i
;
54 for (; next_chan
< 4; next_chan
++) {
55 swizzles
[next_chan
] = last
;
58 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
59 swizzles
[2], swizzles
[3]);
62 dst_reg::dst_reg(src_reg reg
)
66 this->file
= reg
.file
;
68 this->reg_offset
= reg
.reg_offset
;
69 this->type
= reg
.type
;
70 this->writemask
= WRITEMASK_XYZW
;
71 this->reladdr
= reg
.reladdr
;
72 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
75 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
76 enum opcode opcode
, dst_reg dst
,
77 src_reg src0
, src_reg src1
, src_reg src2
)
79 this->opcode
= opcode
;
84 this->ir
= v
->base_ir
;
85 this->annotation
= v
->current_annotation
;
89 vec4_visitor::emit(vec4_instruction
*inst
)
91 this->instructions
.push_tail(inst
);
97 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
98 src_reg src0
, src_reg src1
, src_reg src2
)
100 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
106 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
108 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
112 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
114 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
118 vec4_visitor::emit(enum opcode opcode
)
120 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
125 vec4_visitor::op(dst_reg dst, src_reg src0) \
127 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
133 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \
135 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
154 /** Gen4 predicated IF. */
156 vec4_visitor::IF(uint32_t predicate
)
158 vec4_instruction
*inst
;
160 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
161 inst
->predicate
= predicate
;
166 /** Gen6+ IF with embedded comparison. */
168 vec4_visitor::IF(src_reg src0
, src_reg src1
, uint32_t condition
)
170 assert(intel
->gen
>= 6);
172 vec4_instruction
*inst
;
174 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
176 inst
->conditional_mod
= condition
;
182 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
, uint32_t condition
)
184 vec4_instruction
*inst
;
186 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
,
187 src0
, src1
, src_reg());
188 inst
->conditional_mod
= condition
;
194 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
196 static enum opcode dot_opcodes
[] = {
197 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
200 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
204 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
206 /* The gen6 math instruction ignores the source modifiers --
207 * swizzle, abs, negate, and at least some parts of the register
208 * region description.
210 * While it would seem that this MOV could be avoided at this point
211 * in the case that the swizzle is matched up with the destination
212 * writemask, note that uniform packing and register allocation
213 * could rearrange our swizzle, so let's leave this matter up to
214 * copy propagation later.
216 src_reg temp_src
= src_reg(this, glsl_type::vec4_type
);
217 emit(BRW_OPCODE_MOV
, dst_reg(temp_src
), src
);
219 if (dst
.writemask
!= WRITEMASK_XYZW
) {
220 /* The gen6 math instruction must be align1, so we can't do
223 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
225 emit(opcode
, temp_dst
, temp_src
);
227 emit(BRW_OPCODE_MOV
, dst
, src_reg(temp_dst
));
229 emit(opcode
, dst
, temp_src
);
234 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
236 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
242 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
245 case SHADER_OPCODE_RCP
:
246 case SHADER_OPCODE_RSQ
:
247 case SHADER_OPCODE_SQRT
:
248 case SHADER_OPCODE_EXP2
:
249 case SHADER_OPCODE_LOG2
:
250 case SHADER_OPCODE_SIN
:
251 case SHADER_OPCODE_COS
:
254 assert(!"not reached: bad math opcode");
258 if (intel
->gen
>= 6) {
259 return emit_math1_gen6(opcode
, dst
, src
);
261 return emit_math1_gen4(opcode
, dst
, src
);
266 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
267 dst_reg dst
, src_reg src0
, src_reg src1
)
271 /* The gen6 math instruction ignores the source modifiers --
272 * swizzle, abs, negate, and at least some parts of the register
273 * region description. Move the sources to temporaries to make it
277 expanded
= src_reg(this, glsl_type::vec4_type
);
278 emit(BRW_OPCODE_MOV
, dst_reg(expanded
), src0
);
281 expanded
= src_reg(this, glsl_type::vec4_type
);
282 emit(BRW_OPCODE_MOV
, dst_reg(expanded
), src1
);
285 if (dst
.writemask
!= WRITEMASK_XYZW
) {
286 /* The gen6 math instruction must be align1, so we can't do
289 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
291 emit(opcode
, temp_dst
, src0
, src1
);
293 emit(BRW_OPCODE_MOV
, dst
, src_reg(temp_dst
));
295 emit(opcode
, dst
, src0
, src1
);
300 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
301 dst_reg dst
, src_reg src0
, src_reg src1
)
303 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
309 vec4_visitor::emit_math(enum opcode opcode
,
310 dst_reg dst
, src_reg src0
, src_reg src1
)
312 assert(opcode
== SHADER_OPCODE_POW
);
314 if (intel
->gen
>= 6) {
315 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
317 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
322 vec4_visitor::visit_instructions(const exec_list
*list
)
324 foreach_list(node
, list
) {
325 ir_instruction
*ir
= (ir_instruction
*)node
;
334 type_size(const struct glsl_type
*type
)
339 switch (type
->base_type
) {
342 case GLSL_TYPE_FLOAT
:
344 if (type
->is_matrix()) {
345 return type
->matrix_columns
;
347 /* Regardless of size of vector, it gets a vec4. This is bad
348 * packing for things like floats, but otherwise arrays become a
349 * mess. Hopefully a later pass over the code can pack scalars
350 * down if appropriate.
354 case GLSL_TYPE_ARRAY
:
355 assert(type
->length
> 0);
356 return type_size(type
->fields
.array
) * type
->length
;
357 case GLSL_TYPE_STRUCT
:
359 for (i
= 0; i
< type
->length
; i
++) {
360 size
+= type_size(type
->fields
.structure
[i
].type
);
363 case GLSL_TYPE_SAMPLER
:
364 /* Samplers take up one slot in UNIFORMS[], but they're baked in
375 vec4_visitor::virtual_grf_alloc(int size
)
377 if (virtual_grf_array_size
<= virtual_grf_count
) {
378 if (virtual_grf_array_size
== 0)
379 virtual_grf_array_size
= 16;
381 virtual_grf_array_size
*= 2;
382 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
383 virtual_grf_array_size
);
385 virtual_grf_sizes
[virtual_grf_count
] = size
;
386 return virtual_grf_count
++;
389 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
394 this->reg
= v
->virtual_grf_alloc(type_size(type
));
396 if (type
->is_array() || type
->is_record()) {
397 this->swizzle
= BRW_SWIZZLE_NOOP
;
399 this->swizzle
= swizzle_for_size(type
->vector_elements
);
402 this->type
= brw_type_for_base_type(type
);
405 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
410 this->reg
= v
->virtual_grf_alloc(type_size(type
));
412 if (type
->is_array() || type
->is_record()) {
413 this->writemask
= WRITEMASK_XYZW
;
415 this->writemask
= (1 << type
->vector_elements
) - 1;
418 this->type
= brw_type_for_base_type(type
);
421 /* Our support for uniforms is piggy-backed on the struct
422 * gl_fragment_program, because that's where the values actually
423 * get stored, rather than in some global gl_shader_program uniform
427 vec4_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
429 unsigned int offset
= 0;
430 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[loc
][0].f
;
432 if (type
->is_matrix()) {
433 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
434 type
->vector_elements
,
437 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
438 offset
+= setup_uniform_values(loc
+ offset
, column
);
444 switch (type
->base_type
) {
445 case GLSL_TYPE_FLOAT
:
449 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
450 c
->prog_data
.param
[this->uniforms
* 4 + i
] = &values
[i
];
453 /* Set up pad elements to get things aligned to a vec4 boundary. */
454 for (unsigned int i
= type
->vector_elements
; i
< 4; i
++) {
455 static float zero
= 0;
457 c
->prog_data
.param
[this->uniforms
* 4 + i
] = &zero
;
460 /* Track the size of this uniform vector, for future packing of
463 this->uniform_vector_size
[this->uniforms
] = type
->vector_elements
;
468 case GLSL_TYPE_STRUCT
:
469 for (unsigned int i
= 0; i
< type
->length
; i
++) {
470 offset
+= setup_uniform_values(loc
+ offset
,
471 type
->fields
.structure
[i
].type
);
475 case GLSL_TYPE_ARRAY
:
476 for (unsigned int i
= 0; i
< type
->length
; i
++) {
477 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
481 case GLSL_TYPE_SAMPLER
:
482 /* The sampler takes up a slot, but we don't use any values from it. */
486 assert(!"not reached");
491 /* Our support for builtin uniforms is even scarier than non-builtin.
492 * It sits on top of the PROG_STATE_VAR parameters that are
493 * automatically updated from GL context state.
496 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
498 const ir_state_slot
*const slots
= ir
->state_slots
;
499 assert(ir
->state_slots
!= NULL
);
501 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
502 /* This state reference has already been setup by ir_to_mesa,
503 * but we'll get the same index back here. We can reference
504 * ParameterValues directly, since unlike brw_fs.cpp, we never
505 * add new state references during compile.
507 int index
= _mesa_add_state_reference(this->vp
->Base
.Parameters
,
508 (gl_state_index
*)slots
[i
].tokens
);
509 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
511 this->uniform_vector_size
[this->uniforms
] = 0;
512 /* Add each of the unique swizzled channels of the element.
513 * This will end up matching the size of the glsl_type of this field.
516 for (unsigned int j
= 0; j
< 4; j
++) {
517 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
520 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &values
[swiz
];
521 if (swiz
<= last_swiz
)
522 this->uniform_vector_size
[this->uniforms
]++;
529 vec4_visitor::variable_storage(ir_variable
*var
)
531 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
535 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
537 ir_expression
*expr
= ir
->as_expression();
541 vec4_instruction
*inst
;
543 assert(expr
->get_num_operands() <= 2);
544 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
545 assert(expr
->operands
[i
]->type
->is_scalar());
547 expr
->operands
[i
]->accept(this);
548 op
[i
] = this->result
;
551 switch (expr
->operation
) {
552 case ir_unop_logic_not
:
553 inst
= emit(BRW_OPCODE_AND
, dst_null_d(), op
[0], src_reg(1));
554 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
557 case ir_binop_logic_xor
:
558 inst
= emit(BRW_OPCODE_XOR
, dst_null_d(), op
[0], op
[1]);
559 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
562 case ir_binop_logic_or
:
563 inst
= emit(BRW_OPCODE_OR
, dst_null_d(), op
[0], op
[1]);
564 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
567 case ir_binop_logic_and
:
568 inst
= emit(BRW_OPCODE_AND
, dst_null_d(), op
[0], op
[1]);
569 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
573 if (intel
->gen
>= 6) {
574 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0.0f
));
576 inst
= emit(BRW_OPCODE_MOV
, dst_null_f(), op
[0]);
578 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
582 if (intel
->gen
>= 6) {
583 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0));
585 inst
= emit(BRW_OPCODE_MOV
, dst_null_d(), op
[0]);
587 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
590 case ir_binop_greater
:
591 case ir_binop_gequal
:
593 case ir_binop_lequal
:
595 case ir_binop_all_equal
:
596 case ir_binop_nequal
:
597 case ir_binop_any_nequal
:
598 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
599 inst
->conditional_mod
=
600 brw_conditional_for_comparison(expr
->operation
);
604 assert(!"not reached");
612 if (intel
->gen
>= 6) {
613 vec4_instruction
*inst
= emit(BRW_OPCODE_AND
, dst_null_d(),
614 this->result
, src_reg(1));
615 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
617 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, dst_null_d(), this->result
);
618 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
623 * Emit a gen6 IF statement with the comparison folded into the IF
627 vec4_visitor::emit_if_gen6(ir_if
*ir
)
629 ir_expression
*expr
= ir
->condition
->as_expression();
633 vec4_instruction
*inst
;
636 assert(expr
->get_num_operands() <= 2);
637 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
638 expr
->operands
[i
]->accept(this);
639 op
[i
] = this->result
;
642 switch (expr
->operation
) {
643 case ir_unop_logic_not
:
644 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
645 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
648 case ir_binop_logic_xor
:
649 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], op
[1]);
650 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
653 case ir_binop_logic_or
:
654 temp
= dst_reg(this, glsl_type::bool_type
);
655 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
656 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), src_reg(temp
), src_reg(0));
657 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
660 case ir_binop_logic_and
:
661 temp
= dst_reg(this, glsl_type::bool_type
);
662 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
663 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), src_reg(temp
), src_reg(0));
664 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
668 inst
= emit(BRW_OPCODE_IF
, dst_null_f(), op
[0], src_reg(0));
669 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
673 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
674 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
677 case ir_binop_greater
:
678 case ir_binop_gequal
:
680 case ir_binop_lequal
:
682 case ir_binop_nequal
:
683 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], op
[1]);
684 inst
->conditional_mod
=
685 brw_conditional_for_comparison(expr
->operation
);
688 case ir_binop_all_equal
:
689 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], op
[1]);
690 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
692 inst
= emit(BRW_OPCODE_IF
);
693 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
696 case ir_binop_any_nequal
:
697 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], op
[1]);
698 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
700 inst
= emit(BRW_OPCODE_IF
);
701 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
705 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0));
706 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
708 inst
= emit(BRW_OPCODE_IF
);
709 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
713 assert(!"not reached");
714 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
715 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
721 ir
->condition
->accept(this);
723 vec4_instruction
*inst
= emit(BRW_OPCODE_IF
, dst_null_d(),
724 this->result
, src_reg(0));
725 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
729 vec4_visitor::visit(ir_variable
*ir
)
733 if (variable_storage(ir
))
738 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->location
);
740 /* Do GL_FIXED rescaling for GLES2.0. Our GL_FIXED attributes
741 * come in as floating point conversions of the integer values.
743 for (int i
= ir
->location
; i
< ir
->location
+ type_size(ir
->type
); i
++) {
744 if (!c
->key
.gl_fixed_input_size
[i
])
748 dst
.writemask
= (1 << c
->key
.gl_fixed_input_size
[i
]) - 1;
749 emit(BRW_OPCODE_MUL
, dst
, src_reg(dst
), src_reg(1.0f
/ 65536.0f
));
754 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
756 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
757 output_reg
[ir
->location
+ i
] = *reg
;
758 output_reg
[ir
->location
+ i
].reg_offset
= i
;
759 output_reg
[ir
->location
+ i
].type
= BRW_REGISTER_TYPE_F
;
764 case ir_var_temporary
:
765 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
769 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
771 /* Track how big the whole uniform variable is, in case we need to put a
772 * copy of its data into pull constants for array access.
774 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
776 if (!strncmp(ir
->name
, "gl_", 3)) {
777 setup_builtin_uniform_values(ir
);
779 setup_uniform_values(ir
->location
, ir
->type
);
784 assert(!"not reached");
787 reg
->type
= brw_type_for_base_type(ir
->type
);
788 hash_table_insert(this->variable_ht
, reg
, ir
);
792 vec4_visitor::visit(ir_loop
*ir
)
796 /* We don't want debugging output to print the whole body of the
797 * loop as the annotation.
799 this->base_ir
= NULL
;
801 if (ir
->counter
!= NULL
) {
802 this->base_ir
= ir
->counter
;
803 ir
->counter
->accept(this);
804 counter
= *(variable_storage(ir
->counter
));
806 if (ir
->from
!= NULL
) {
807 this->base_ir
= ir
->from
;
808 ir
->from
->accept(this);
810 emit(BRW_OPCODE_MOV
, counter
, this->result
);
817 this->base_ir
= ir
->to
;
818 ir
->to
->accept(this);
820 vec4_instruction
*inst
= emit(BRW_OPCODE_CMP
, dst_null_d(),
821 src_reg(counter
), this->result
);
822 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
824 inst
= emit(BRW_OPCODE_BREAK
);
825 inst
->predicate
= BRW_PREDICATE_NORMAL
;
828 visit_instructions(&ir
->body_instructions
);
832 this->base_ir
= ir
->increment
;
833 ir
->increment
->accept(this);
834 emit(BRW_OPCODE_ADD
, counter
, src_reg(counter
), this->result
);
837 emit(BRW_OPCODE_WHILE
);
841 vec4_visitor::visit(ir_loop_jump
*ir
)
844 case ir_loop_jump::jump_break
:
845 emit(BRW_OPCODE_BREAK
);
847 case ir_loop_jump::jump_continue
:
848 emit(BRW_OPCODE_CONTINUE
);
855 vec4_visitor::visit(ir_function_signature
*ir
)
862 vec4_visitor::visit(ir_function
*ir
)
864 /* Ignore function bodies other than main() -- we shouldn't see calls to
865 * them since they should all be inlined.
867 if (strcmp(ir
->name
, "main") == 0) {
868 const ir_function_signature
*sig
;
871 sig
= ir
->matching_signature(&empty
);
875 visit_instructions(&sig
->body
);
880 vec4_visitor::try_emit_sat(ir_expression
*ir
)
882 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
886 sat_src
->accept(this);
887 src_reg src
= this->result
;
889 this->result
= src_reg(this, ir
->type
);
890 vec4_instruction
*inst
;
891 inst
= emit(BRW_OPCODE_MOV
, dst_reg(this->result
), src
);
892 inst
->saturate
= true;
898 vec4_visitor::emit_bool_comparison(unsigned int op
,
899 dst_reg dst
, src_reg src0
, src_reg src1
)
901 /* original gen4 does destination conversion before comparison. */
903 dst
.type
= src0
.type
;
905 vec4_instruction
*inst
= emit(BRW_OPCODE_CMP
, dst
, src0
, src1
);
906 inst
->conditional_mod
= brw_conditional_for_comparison(op
);
908 dst
.type
= BRW_REGISTER_TYPE_D
;
909 emit(BRW_OPCODE_AND
, dst
, src_reg(dst
), src_reg(0x1));
913 vec4_visitor::visit(ir_expression
*ir
)
915 unsigned int operand
;
916 src_reg op
[Elements(ir
->operands
)];
919 vec4_instruction
*inst
;
921 if (try_emit_sat(ir
))
924 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
925 this->result
.file
= BAD_FILE
;
926 ir
->operands
[operand
]->accept(this);
927 if (this->result
.file
== BAD_FILE
) {
928 printf("Failed to get tree for expression operand:\n");
929 ir
->operands
[operand
]->print();
932 op
[operand
] = this->result
;
934 /* Matrix expression operands should have been broken down to vector
935 * operations already.
937 assert(!ir
->operands
[operand
]->type
->is_matrix());
940 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
941 if (ir
->operands
[1]) {
942 vector_elements
= MAX2(vector_elements
,
943 ir
->operands
[1]->type
->vector_elements
);
946 this->result
.file
= BAD_FILE
;
948 /* Storage for our result. Ideally for an assignment we'd be using
949 * the actual storage for the result here, instead.
951 result_src
= src_reg(this, ir
->type
);
952 /* convenience for the emit functions below. */
953 result_dst
= dst_reg(result_src
);
954 /* If nothing special happens, this is the result. */
955 this->result
= result_src
;
956 /* Limit writes to the channels that will be used by result_src later.
957 * This does limit this temp's use as a temporary for multi-instruction
960 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
962 switch (ir
->operation
) {
963 case ir_unop_logic_not
:
964 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
965 * ones complement of the whole register, not just bit 0.
967 emit(BRW_OPCODE_XOR
, result_dst
, op
[0], src_reg(1));
970 op
[0].negate
= !op
[0].negate
;
971 this->result
= op
[0];
975 op
[0].negate
= false;
976 this->result
= op
[0];
980 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0.0f
));
982 inst
= emit(BRW_OPCODE_CMP
, dst_null_f(), op
[0], src_reg(0.0f
));
983 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
984 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1.0f
));
985 inst
->predicate
= BRW_PREDICATE_NORMAL
;
987 inst
= emit(BRW_OPCODE_CMP
, dst_null_f(), op
[0], src_reg(0.0f
));
988 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
989 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(-1.0f
));
990 inst
->predicate
= BRW_PREDICATE_NORMAL
;
995 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
999 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1002 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1006 assert(!"not reached: should be handled by ir_explog_to_explog2");
1009 case ir_unop_sin_reduced
:
1010 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1013 case ir_unop_cos_reduced
:
1014 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1019 assert(!"derivatives not valid in vertex shader");
1023 assert(!"not reached: should be handled by lower_noise");
1027 emit(BRW_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1030 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1034 if (ir
->type
->is_integer()) {
1035 /* For integer multiplication, the MUL uses the low 16 bits
1036 * of one of the operands (src0 on gen6, src1 on gen7). The
1037 * MACH accumulates in the contribution of the upper 16 bits
1040 * FINISHME: Emit just the MUL if we know an operand is small
1043 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
1045 emit(BRW_OPCODE_MUL
, acc
, op
[0], op
[1]);
1046 emit(BRW_OPCODE_MACH
, dst_null_d(), op
[0], op
[1]);
1047 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(acc
));
1049 emit(BRW_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1053 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1055 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1059 case ir_binop_greater
:
1060 case ir_binop_lequal
:
1061 case ir_binop_gequal
:
1062 case ir_binop_equal
:
1063 case ir_binop_nequal
: {
1064 dst_reg temp
= result_dst
;
1065 /* original gen4 does implicit conversion before comparison. */
1067 temp
.type
= op
[0].type
;
1069 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
1070 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
1071 emit(BRW_OPCODE_AND
, result_dst
, this->result
, src_reg(0x1));
1075 case ir_binop_all_equal
:
1076 /* "==" operator producing a scalar boolean. */
1077 if (ir
->operands
[0]->type
->is_vector() ||
1078 ir
->operands
[1]->type
->is_vector()) {
1079 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
1080 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1082 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
1083 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
1084 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1086 dst_reg temp
= result_dst
;
1087 /* original gen4 does implicit conversion before comparison. */
1089 temp
.type
= op
[0].type
;
1091 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
1092 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1093 emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(0x1));
1096 case ir_binop_any_nequal
:
1097 /* "!=" operator producing a scalar boolean. */
1098 if (ir
->operands
[0]->type
->is_vector() ||
1099 ir
->operands
[1]->type
->is_vector()) {
1100 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
1101 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1103 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
1104 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
1105 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1107 dst_reg temp
= result_dst
;
1108 /* original gen4 does implicit conversion before comparison. */
1110 temp
.type
= op
[0].type
;
1112 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
1113 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1114 emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(0x1));
1119 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0));
1120 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1122 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
1124 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
1125 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1128 case ir_binop_logic_xor
:
1129 emit(BRW_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1132 case ir_binop_logic_or
:
1133 emit(BRW_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1136 case ir_binop_logic_and
:
1137 emit(BRW_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1141 assert(ir
->operands
[0]->type
->is_vector());
1142 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1143 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1147 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1150 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1159 emit(BRW_OPCODE_MOV
, result_dst
, op
[0]);
1163 dst_reg temp
= result_dst
;
1164 /* original gen4 does implicit conversion before comparison. */
1166 temp
.type
= op
[0].type
;
1168 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], src_reg(0.0f
));
1169 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1170 inst
= emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(1));
1175 emit(BRW_OPCODE_RNDZ
, result_dst
, op
[0]);
1178 op
[0].negate
= !op
[0].negate
;
1179 inst
= emit(BRW_OPCODE_RNDD
, result_dst
, op
[0]);
1180 this->result
.negate
= true;
1183 inst
= emit(BRW_OPCODE_RNDD
, result_dst
, op
[0]);
1186 inst
= emit(BRW_OPCODE_FRC
, result_dst
, op
[0]);
1188 case ir_unop_round_even
:
1189 emit(BRW_OPCODE_RNDE
, result_dst
, op
[0]);
1193 inst
= emit(BRW_OPCODE_CMP
, result_dst
, op
[0], op
[1]);
1194 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1196 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1197 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1200 inst
= emit(BRW_OPCODE_CMP
, result_dst
, op
[0], op
[1]);
1201 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1203 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1204 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1208 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1211 case ir_unop_bit_not
:
1212 inst
= emit(BRW_OPCODE_NOT
, result_dst
, op
[0]);
1214 case ir_binop_bit_and
:
1215 inst
= emit(BRW_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1217 case ir_binop_bit_xor
:
1218 inst
= emit(BRW_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1220 case ir_binop_bit_or
:
1221 inst
= emit(BRW_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1224 case ir_binop_lshift
:
1225 case ir_binop_rshift
:
1226 assert(!"GLSL 1.30 features unsupported");
1229 case ir_quadop_vector
:
1230 assert(!"not reached: should be handled by lower_quadop_vector");
1237 vec4_visitor::visit(ir_swizzle
*ir
)
1243 /* Note that this is only swizzles in expressions, not those on the left
1244 * hand side of an assignment, which do write masking. See ir_assignment
1248 ir
->val
->accept(this);
1250 assert(src
.file
!= BAD_FILE
);
1252 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1255 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1258 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1261 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1264 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1268 for (; i
< 4; i
++) {
1269 /* Replicate the last channel out. */
1270 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1273 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1279 vec4_visitor::visit(ir_dereference_variable
*ir
)
1281 const struct glsl_type
*type
= ir
->type
;
1282 dst_reg
*reg
= variable_storage(ir
->var
);
1285 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1286 this->result
= src_reg(brw_null_reg());
1290 this->result
= src_reg(*reg
);
1292 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1293 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1297 vec4_visitor::visit(ir_dereference_array
*ir
)
1299 ir_constant
*constant_index
;
1301 int element_size
= type_size(ir
->type
);
1303 constant_index
= ir
->array_index
->constant_expression_value();
1305 ir
->array
->accept(this);
1308 if (constant_index
) {
1309 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
1311 /* Variable index array dereference. It eats the "vec4" of the
1312 * base of the array and an index that offsets the Mesa register
1315 ir
->array_index
->accept(this);
1319 if (element_size
== 1) {
1320 index_reg
= this->result
;
1322 index_reg
= src_reg(this, glsl_type::int_type
);
1324 emit(BRW_OPCODE_MUL
, dst_reg(index_reg
),
1325 this->result
, src_reg(element_size
));
1329 src_reg temp
= src_reg(this, glsl_type::int_type
);
1331 emit(BRW_OPCODE_ADD
, dst_reg(temp
), *src
.reladdr
, index_reg
);
1336 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1337 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1340 /* If the type is smaller than a vec4, replicate the last channel out. */
1341 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1342 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1344 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1345 src
.type
= brw_type_for_base_type(ir
->type
);
1351 vec4_visitor::visit(ir_dereference_record
*ir
)
1354 const glsl_type
*struct_type
= ir
->record
->type
;
1357 ir
->record
->accept(this);
1359 for (i
= 0; i
< struct_type
->length
; i
++) {
1360 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1362 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1365 /* If the type is smaller than a vec4, replicate the last channel out. */
1366 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1367 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1369 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1370 this->result
.type
= brw_type_for_base_type(ir
->type
);
1372 this->result
.reg_offset
+= offset
;
1376 * We want to be careful in assignment setup to hit the actual storage
1377 * instead of potentially using a temporary like we might with the
1378 * ir_dereference handler.
1381 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1383 /* The LHS must be a dereference. If the LHS is a variable indexed array
1384 * access of a vector, it must be separated into a series conditional moves
1385 * before reaching this point (see ir_vec_index_to_cond_assign).
1387 assert(ir
->as_dereference());
1388 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1390 assert(!deref_array
->array
->type
->is_vector());
1393 /* Use the rvalue deref handler for the most part. We'll ignore
1394 * swizzles in it and write swizzles using writemask, though.
1397 return dst_reg(v
->result
);
1401 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1402 const struct glsl_type
*type
, bool predicated
)
1404 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1405 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1406 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicated
);
1411 if (type
->is_array()) {
1412 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1413 emit_block_move(dst
, src
, type
->fields
.array
, predicated
);
1418 if (type
->is_matrix()) {
1419 const struct glsl_type
*vec_type
;
1421 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1422 type
->vector_elements
, 1);
1424 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1425 emit_block_move(dst
, src
, vec_type
, predicated
);
1430 assert(type
->is_scalar() || type
->is_vector());
1432 dst
->type
= brw_type_for_base_type(type
);
1433 src
->type
= dst
->type
;
1435 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1437 /* Do we need to worry about swizzling a swizzle? */
1438 assert(src
->swizzle
= BRW_SWIZZLE_NOOP
);
1439 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1441 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, *dst
, *src
);
1443 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1450 /* If the RHS processing resulted in an instruction generating a
1451 * temporary value, and it would be easy to rewrite the instruction to
1452 * generate its result right into the LHS instead, do so. This ends
1453 * up reliably removing instructions where it can be tricky to do so
1454 * later without real UD chain information.
1457 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1460 vec4_instruction
*pre_rhs_inst
,
1461 vec4_instruction
*last_rhs_inst
)
1463 /* This could be supported, but it would take more smarts. */
1467 if (pre_rhs_inst
== last_rhs_inst
)
1468 return false; /* No instructions generated to work with. */
1470 /* Make sure the last instruction generated our source reg. */
1471 if (src
.file
!= GRF
||
1472 src
.file
!= last_rhs_inst
->dst
.file
||
1473 src
.reg
!= last_rhs_inst
->dst
.reg
||
1474 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
1478 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
1481 /* Check that that last instruction fully initialized the channels
1482 * we want to use, in the order we want to use them. We could
1483 * potentially reswizzle the operands of many instructions so that
1484 * we could handle out of order channels, but don't yet.
1486 for (int i
= 0; i
< 4; i
++) {
1487 if (dst
.writemask
& (1 << i
)) {
1488 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
1491 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
1496 /* Success! Rewrite the instruction. */
1497 last_rhs_inst
->dst
.file
= dst
.file
;
1498 last_rhs_inst
->dst
.reg
= dst
.reg
;
1499 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
1500 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
1501 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
1507 vec4_visitor::visit(ir_assignment
*ir
)
1509 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
1511 if (!ir
->lhs
->type
->is_scalar() &&
1512 !ir
->lhs
->type
->is_vector()) {
1513 ir
->rhs
->accept(this);
1514 src_reg src
= this->result
;
1516 if (ir
->condition
) {
1517 emit_bool_to_cond_code(ir
->condition
);
1520 emit_block_move(&dst
, &src
, ir
->rhs
->type
, ir
->condition
!= NULL
);
1524 /* Now we're down to just a scalar/vector with writemasks. */
1527 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
1528 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1530 ir
->rhs
->accept(this);
1532 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1534 src_reg src
= this->result
;
1537 int first_enabled_chan
= 0;
1540 assert(ir
->lhs
->type
->is_vector() ||
1541 ir
->lhs
->type
->is_scalar());
1542 dst
.writemask
= ir
->write_mask
;
1544 for (int i
= 0; i
< 4; i
++) {
1545 if (dst
.writemask
& (1 << i
)) {
1546 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
1551 /* Swizzle a small RHS vector into the channels being written.
1553 * glsl ir treats write_mask as dictating how many channels are
1554 * present on the RHS while in our instructions we need to make
1555 * those channels appear in the slots of the vec4 they're written to.
1557 for (int i
= 0; i
< 4; i
++) {
1558 if (dst
.writemask
& (1 << i
))
1559 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
1561 swizzles
[i
] = first_enabled_chan
;
1563 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
1564 swizzles
[2], swizzles
[3]);
1566 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
1570 if (ir
->condition
) {
1571 emit_bool_to_cond_code(ir
->condition
);
1574 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1575 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, dst
, src
);
1578 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1586 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
1588 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1589 foreach_list(node
, &ir
->components
) {
1590 ir_constant
*field_value
= (ir_constant
*)node
;
1592 emit_constant_values(dst
, field_value
);
1597 if (ir
->type
->is_array()) {
1598 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
1599 emit_constant_values(dst
, ir
->array_elements
[i
]);
1604 if (ir
->type
->is_matrix()) {
1605 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1606 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
1607 dst
->writemask
= 1 << j
;
1608 dst
->type
= BRW_REGISTER_TYPE_F
;
1610 emit(BRW_OPCODE_MOV
, *dst
,
1611 src_reg(ir
->value
.f
[i
* ir
->type
->vector_elements
+ j
]));
1618 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1619 dst
->writemask
= 1 << i
;
1620 dst
->type
= brw_type_for_base_type(ir
->type
);
1622 switch (ir
->type
->base_type
) {
1623 case GLSL_TYPE_FLOAT
:
1624 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.f
[i
]));
1627 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.i
[i
]));
1629 case GLSL_TYPE_UINT
:
1630 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.u
[i
]));
1632 case GLSL_TYPE_BOOL
:
1633 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.b
[i
]));
1636 assert(!"Non-float/uint/int/bool constant");
1644 vec4_visitor::visit(ir_constant
*ir
)
1646 dst_reg dst
= dst_reg(this, ir
->type
);
1647 this->result
= src_reg(dst
);
1649 emit_constant_values(&dst
, ir
);
1653 vec4_visitor::visit(ir_call
*ir
)
1655 assert(!"not reached");
1659 vec4_visitor::visit(ir_texture
*ir
)
1661 /* FINISHME: Implement vertex texturing.
1663 * With 0 vertex samplers available, the linker will reject
1664 * programs that do vertex texturing, but after our visitor has
1670 vec4_visitor::visit(ir_return
*ir
)
1672 assert(!"not reached");
1676 vec4_visitor::visit(ir_discard
*ir
)
1678 assert(!"not reached");
1682 vec4_visitor::visit(ir_if
*ir
)
1684 /* Don't point the annotation at the if statement, because then it plus
1685 * the then and else blocks get printed.
1687 this->base_ir
= ir
->condition
;
1689 if (intel
->gen
== 6) {
1692 emit_bool_to_cond_code(ir
->condition
);
1693 vec4_instruction
*inst
= emit(BRW_OPCODE_IF
);
1694 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1697 visit_instructions(&ir
->then_instructions
);
1699 if (!ir
->else_instructions
.is_empty()) {
1700 this->base_ir
= ir
->condition
;
1701 emit(BRW_OPCODE_ELSE
);
1703 visit_instructions(&ir
->else_instructions
);
1706 this->base_ir
= ir
->condition
;
1707 emit(BRW_OPCODE_ENDIF
);
1711 vec4_visitor::emit_vue_header_gen4(int header_mrf
)
1713 /* Get the position */
1714 src_reg pos
= src_reg(output_reg
[VERT_RESULT_HPOS
]);
1716 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
1717 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
1719 current_annotation
= "NDC";
1720 dst_reg ndc_w
= ndc
;
1721 ndc_w
.writemask
= WRITEMASK_W
;
1722 src_reg pos_w
= pos
;
1723 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
1724 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
1726 dst_reg ndc_xyz
= ndc
;
1727 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
1729 emit(BRW_OPCODE_MUL
, ndc_xyz
, pos
, src_reg(ndc_w
));
1731 if ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
1732 c
->key
.nr_userclip
|| brw
->has_negative_rhw_bug
) {
1733 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
1736 emit(BRW_OPCODE_MOV
, header1
, 0u);
1738 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1739 assert(!"finishme: psiz");
1742 header1
.writemask
= WRITEMASK_W
;
1743 emit(BRW_OPCODE_MUL
, header1
, psiz
, 1u << 11);
1744 emit(BRW_OPCODE_AND
, header1
, src_reg(header1
), 0x7ff << 8);
1747 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1748 vec4_instruction
*inst
;
1750 inst
= emit(BRW_OPCODE_DP4
, dst_reg(brw_null_reg()),
1751 pos
, src_reg(c
->userplane
[i
]));
1752 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1754 emit(BRW_OPCODE_OR
, header1
, src_reg(header1
), 1u << i
);
1755 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1758 /* i965 clipping workaround:
1759 * 1) Test for -ve rhw
1761 * set ndc = (0,0,0,0)
1764 * Later, clipping will detect ucp[6] and ensure the primitive is
1765 * clipped against all fixed planes.
1767 if (brw
->has_negative_rhw_bug
) {
1771 vec8(brw_null_reg()),
1773 brw_swizzle1(ndc
, 3),
1776 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1777 brw_MOV(p
, ndc
, brw_imm_f(0));
1778 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1782 header1
.writemask
= WRITEMASK_XYZW
;
1783 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(header1
));
1785 emit(BRW_OPCODE_MOV
, retype(brw_message_reg(header_mrf
++),
1786 BRW_REGISTER_TYPE_UD
), 0u);
1789 if (intel
->gen
== 5) {
1790 /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
1791 * dword 0-3 (m1) of the header is indices, point width, clip flags.
1792 * dword 4-7 (m2) is the ndc position (set above)
1793 * dword 8-11 (m3) of the vertex header is the 4D space position
1794 * dword 12-19 (m4,m5) of the vertex header is the user clip distance.
1795 * m6 is a pad so that the vertex element data is aligned
1796 * m7 is the first vertex data we fill.
1798 current_annotation
= "NDC";
1799 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(ndc
));
1801 current_annotation
= "gl_Position";
1802 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), pos
);
1804 /* user clip distance. */
1807 /* Pad so that vertex element data is aligned. */
1810 /* There are 8 dwords in VUE header pre-Ironlake:
1811 * dword 0-3 (m1) is indices, point width, clip flags.
1812 * dword 4-7 (m2) is ndc position (set above)
1814 * dword 8-11 (m3) is the first vertex data.
1816 current_annotation
= "NDC";
1817 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(ndc
));
1819 current_annotation
= "gl_Position";
1820 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), pos
);
1827 vec4_visitor::emit_vue_header_gen6(int header_mrf
)
1831 /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
1832 * dword 0-3 (m2) of the header is indices, point width, clip flags.
1833 * dword 4-7 (m3) is the 4D space position
1834 * dword 8-15 (m4,m5) of the vertex header is the user clip distance if
1837 * m4 or 6 is the first vertex element data we fill.
1840 current_annotation
= "indices, point width, clip flags";
1841 reg
= brw_message_reg(header_mrf
++);
1842 emit(BRW_OPCODE_MOV
, retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0));
1843 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1844 emit(BRW_OPCODE_MOV
, brw_writemask(reg
, WRITEMASK_W
),
1845 src_reg(output_reg
[VERT_RESULT_PSIZ
]));
1848 current_annotation
= "gl_Position";
1849 emit(BRW_OPCODE_MOV
,
1850 brw_message_reg(header_mrf
++), src_reg(output_reg
[VERT_RESULT_HPOS
]));
1852 current_annotation
= "user clip distances";
1853 if (c
->key
.nr_userclip
) {
1854 for (int i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1857 m
= brw_message_reg(header_mrf
);
1859 m
= brw_message_reg(header_mrf
+ 1);
1861 emit(DP4(dst_reg(brw_writemask(m
, 1 << (i
& 3))),
1862 src_reg(output_reg
[VERT_RESULT_HPOS
]),
1863 src_reg(c
->userplane
[i
])));
1868 current_annotation
= NULL
;
1874 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
1876 struct intel_context
*intel
= &brw
->intel
;
1878 if (intel
->gen
>= 6) {
1879 /* URB data written (does not include the message header reg) must
1880 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
1881 * section 5.4.3.2.2: URB_INTERLEAVED.
1883 * URB entries are allocated on a multiple of 1024 bits, so an
1884 * extra 128 bits written here to make the end align to 256 is
1887 if ((mlen
% 2) != 1)
1895 * Generates the VUE payload plus the 1 or 2 URB write instructions to
1896 * complete the VS thread.
1898 * The VUE layout is documented in Volume 2a.
1901 vec4_visitor::emit_urb_writes()
1903 /* MRF 0 is reserved for the debugger, so start with message header
1909 uint64_t outputs_remaining
= c
->prog_data
.outputs_written
;
1910 /* In the process of generating our URB write message contents, we
1911 * may need to unspill a register or load from an array. Those
1912 * reads would use MRFs 14-15.
1914 int max_usable_mrf
= 13;
1916 /* FINISHME: edgeflag */
1918 /* First mrf is the g0-based message header containing URB handles and such,
1919 * which is implied in VS_OPCODE_URB_WRITE.
1923 if (intel
->gen
>= 6) {
1924 mrf
= emit_vue_header_gen6(mrf
);
1926 mrf
= emit_vue_header_gen4(mrf
);
1929 /* Set up the VUE data for the first URB write */
1931 for (attr
= 0; attr
< VERT_RESULT_MAX
; attr
++) {
1932 if (!(c
->prog_data
.outputs_written
& BITFIELD64_BIT(attr
)))
1935 outputs_remaining
&= ~BITFIELD64_BIT(attr
);
1937 /* This is set up in the VUE header. */
1938 if (attr
== VERT_RESULT_HPOS
)
1941 /* This is loaded into the VUE header, and thus doesn't occupy
1942 * an attribute slot.
1944 if (attr
== VERT_RESULT_PSIZ
)
1947 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, brw_message_reg(mrf
++),
1948 src_reg(output_reg
[attr
]));
1950 if ((attr
== VERT_RESULT_COL0
||
1951 attr
== VERT_RESULT_COL1
||
1952 attr
== VERT_RESULT_BFC0
||
1953 attr
== VERT_RESULT_BFC1
) &&
1954 c
->key
.clamp_vertex_color
) {
1955 inst
->saturate
= true;
1958 /* If this was MRF 15, we can't fit anything more into this URB
1959 * WRITE. Note that base_mrf of 1 means that MRF 15 is an
1960 * even-numbered amount of URB write data, which will meet
1961 * gen6's requirements for length alignment.
1963 if (mrf
> max_usable_mrf
) {
1969 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
1970 inst
->base_mrf
= base_mrf
;
1971 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
1972 inst
->eot
= !outputs_remaining
;
1974 urb_entry_size
= mrf
- base_mrf
;
1976 /* Optional second URB write */
1977 if (outputs_remaining
) {
1980 for (; attr
< VERT_RESULT_MAX
; attr
++) {
1981 if (!(c
->prog_data
.outputs_written
& BITFIELD64_BIT(attr
)))
1984 assert(mrf
< max_usable_mrf
);
1986 emit(BRW_OPCODE_MOV
, brw_message_reg(mrf
++), src_reg(output_reg
[attr
]));
1989 inst
= emit(VS_OPCODE_URB_WRITE
);
1990 inst
->base_mrf
= base_mrf
;
1991 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
1993 /* URB destination offset. In the previous write, we got MRFs
1994 * 2-13 minus the one header MRF, so 12 regs. URB offset is in
1995 * URB row increments, and each of our MRFs is half of one of
1996 * those, since we're doing interleaved writes.
1998 inst
->offset
= (max_usable_mrf
- base_mrf
) / 2;
2000 urb_entry_size
+= mrf
- base_mrf
;
2003 if (intel
->gen
== 6)
2004 c
->prog_data
.urb_entry_size
= ALIGN(urb_entry_size
, 8) / 8;
2006 c
->prog_data
.urb_entry_size
= ALIGN(urb_entry_size
, 4) / 4;
2010 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
2011 src_reg
*reladdr
, int reg_offset
)
2013 /* Because we store the values to scratch interleaved like our
2014 * vertex data, we need to scale the vec4 index by 2.
2016 int message_header_scale
= 2;
2018 /* Pre-gen6, the message header uses byte offsets instead of vec4
2019 * (16-byte) offset units.
2022 message_header_scale
*= 16;
2025 src_reg index
= src_reg(this, glsl_type::int_type
);
2027 vec4_instruction
*add
= emit(BRW_OPCODE_ADD
,
2030 src_reg(reg_offset
));
2031 /* Move our new instruction from the tail to its correct place. */
2033 inst
->insert_before(add
);
2035 vec4_instruction
*mul
= emit(BRW_OPCODE_MUL
, dst_reg(index
),
2036 index
, src_reg(message_header_scale
));
2038 inst
->insert_before(mul
);
2042 return src_reg(reg_offset
* message_header_scale
);
2047 vec4_visitor::get_pull_constant_offset(vec4_instruction
*inst
,
2048 src_reg
*reladdr
, int reg_offset
)
2051 src_reg index
= src_reg(this, glsl_type::int_type
);
2053 vec4_instruction
*add
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_ADD
,
2056 src_reg(reg_offset
));
2058 add
->annotation
= inst
->annotation
;
2059 inst
->insert_before(add
);
2061 /* Pre-gen6, the message header uses byte offsets instead of vec4
2062 * (16-byte) offset units.
2064 if (intel
->gen
< 6) {
2065 vec4_instruction
*mul
= new(mem_ctx
) vec4_instruction(this,
2071 mul
->annotation
= inst
->annotation
;
2072 inst
->insert_before(mul
);
2077 int message_header_scale
= intel
->gen
< 6 ? 16 : 1;
2078 return src_reg(reg_offset
* message_header_scale
);
2083 * Emits an instruction before @inst to load the value named by @orig_src
2084 * from scratch space at @base_offset to @temp.
2087 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
2088 dst_reg temp
, src_reg orig_src
,
2091 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2092 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
2094 vec4_instruction
*scratch_read_inst
= emit(VS_OPCODE_SCRATCH_READ
,
2097 scratch_read_inst
->base_mrf
= 14;
2098 scratch_read_inst
->mlen
= 1;
2099 /* Move our instruction from the tail to its correct place. */
2100 scratch_read_inst
->remove();
2101 inst
->insert_before(scratch_read_inst
);
2105 * Emits an instruction after @inst to store the value to be written
2106 * to @orig_dst to scratch space at @base_offset, from @temp.
2109 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
,
2110 src_reg temp
, dst_reg orig_dst
,
2113 int reg_offset
= base_offset
+ orig_dst
.reg_offset
;
2114 src_reg index
= get_scratch_offset(inst
, orig_dst
.reladdr
, reg_offset
);
2116 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
2117 orig_dst
.writemask
));
2118 vec4_instruction
*scratch_write_inst
= emit(VS_OPCODE_SCRATCH_WRITE
,
2120 scratch_write_inst
->base_mrf
= 13;
2121 scratch_write_inst
->mlen
= 2;
2122 scratch_write_inst
->predicate
= inst
->predicate
;
2123 /* Move our instruction from the tail to its correct place. */
2124 scratch_write_inst
->remove();
2125 inst
->insert_after(scratch_write_inst
);
2129 * We can't generally support array access in GRF space, because a
2130 * single instruction's destination can only span 2 contiguous
2131 * registers. So, we send all GRF arrays that get variable index
2132 * access to scratch space.
2135 vec4_visitor::move_grf_array_access_to_scratch()
2137 int scratch_loc
[this->virtual_grf_count
];
2139 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
2140 scratch_loc
[i
] = -1;
2143 /* First, calculate the set of virtual GRFs that need to be punted
2144 * to scratch due to having any array access on them, and where in
2147 foreach_list(node
, &this->instructions
) {
2148 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2150 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
2151 scratch_loc
[inst
->dst
.reg
] == -1) {
2152 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
2153 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
] * 8 * 4;
2156 for (int i
= 0 ; i
< 3; i
++) {
2157 src_reg
*src
= &inst
->src
[i
];
2159 if (src
->file
== GRF
&& src
->reladdr
&&
2160 scratch_loc
[src
->reg
] == -1) {
2161 scratch_loc
[src
->reg
] = c
->last_scratch
;
2162 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
] * 8 * 4;
2167 /* Now, for anything that will be accessed through scratch, rewrite
2168 * it to load/store. Note that this is a _safe list walk, because
2169 * we may generate a new scratch_write instruction after the one
2172 foreach_list_safe(node
, &this->instructions
) {
2173 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2175 /* Set up the annotation tracking for new generated instructions. */
2177 current_annotation
= inst
->annotation
;
2179 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
2180 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
2182 emit_scratch_write(inst
, temp
, inst
->dst
, scratch_loc
[inst
->dst
.reg
]);
2184 inst
->dst
.file
= temp
.file
;
2185 inst
->dst
.reg
= temp
.reg
;
2186 inst
->dst
.reg_offset
= temp
.reg_offset
;
2187 inst
->dst
.reladdr
= NULL
;
2190 for (int i
= 0 ; i
< 3; i
++) {
2191 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
2194 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2196 emit_scratch_read(inst
, temp
, inst
->src
[i
],
2197 scratch_loc
[inst
->src
[i
].reg
]);
2199 inst
->src
[i
].file
= temp
.file
;
2200 inst
->src
[i
].reg
= temp
.reg
;
2201 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2202 inst
->src
[i
].reladdr
= NULL
;
2208 * Emits an instruction before @inst to load the value named by @orig_src
2209 * from the pull constant buffer (surface) at @base_offset to @temp.
2212 vec4_visitor::emit_pull_constant_load(vec4_instruction
*inst
,
2213 dst_reg temp
, src_reg orig_src
,
2216 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2217 src_reg index
= get_pull_constant_offset(inst
, orig_src
.reladdr
, reg_offset
);
2218 vec4_instruction
*load
;
2220 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
2222 load
->annotation
= inst
->annotation
;
2223 load
->ir
= inst
->ir
;
2224 load
->base_mrf
= 14;
2226 inst
->insert_before(load
);
2230 * Implements array access of uniforms by inserting a
2231 * PULL_CONSTANT_LOAD instruction.
2233 * Unlike temporary GRF array access (where we don't support it due to
2234 * the difficulty of doing relative addressing on instruction
2235 * destinations), we could potentially do array access of uniforms
2236 * that were loaded in GRF space as push constants. In real-world
2237 * usage we've seen, though, the arrays being used are always larger
2238 * than we could load as push constants, so just always move all
2239 * uniform array access out to a pull constant buffer.
2242 vec4_visitor::move_uniform_array_access_to_pull_constants()
2244 int pull_constant_loc
[this->uniforms
];
2246 for (int i
= 0; i
< this->uniforms
; i
++) {
2247 pull_constant_loc
[i
] = -1;
2250 /* Walk through and find array access of uniforms. Put a copy of that
2251 * uniform in the pull constant buffer.
2253 * Note that we don't move constant-indexed accesses to arrays. No
2254 * testing has been done of the performance impact of this choice.
2256 foreach_list_safe(node
, &this->instructions
) {
2257 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2259 for (int i
= 0 ; i
< 3; i
++) {
2260 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
2263 int uniform
= inst
->src
[i
].reg
;
2265 /* If this array isn't already present in the pull constant buffer,
2268 if (pull_constant_loc
[uniform
] == -1) {
2269 const float **values
= &prog_data
->param
[uniform
* 4];
2271 pull_constant_loc
[uniform
] = prog_data
->nr_pull_params
;
2273 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
2274 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
2278 /* Set up the annotation tracking for new generated instructions. */
2280 current_annotation
= inst
->annotation
;
2282 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2284 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
2285 pull_constant_loc
[uniform
]);
2287 inst
->src
[i
].file
= temp
.file
;
2288 inst
->src
[i
].reg
= temp
.reg
;
2289 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2290 inst
->src
[i
].reladdr
= NULL
;
2294 /* Now there are no accesses of the UNIFORM file with a reladdr, so
2295 * no need to track them as larger-than-vec4 objects. This will be
2296 * relied on in cutting out unused uniform vectors from push
2299 split_uniform_registers();
2302 vec4_visitor::vec4_visitor(struct brw_vs_compile
*c
,
2303 struct gl_shader_program
*prog
,
2304 struct brw_shader
*shader
)
2309 this->intel
= &brw
->intel
;
2310 this->ctx
= &intel
->ctx
;
2312 this->shader
= shader
;
2314 this->mem_ctx
= ralloc_context(NULL
);
2315 this->failed
= false;
2317 this->base_ir
= NULL
;
2318 this->current_annotation
= NULL
;
2321 this->vp
= prog
->VertexProgram
;
2322 this->prog_data
= &c
->prog_data
;
2324 this->variable_ht
= hash_table_ctor(0,
2325 hash_table_pointer_hash
,
2326 hash_table_pointer_compare
);
2328 this->virtual_grf_def
= NULL
;
2329 this->virtual_grf_use
= NULL
;
2330 this->virtual_grf_sizes
= NULL
;
2331 this->virtual_grf_count
= 0;
2332 this->virtual_grf_array_size
= 0;
2333 this->live_intervals_valid
= false;
2337 this->variable_ht
= hash_table_ctor(0,
2338 hash_table_pointer_hash
,
2339 hash_table_pointer_compare
);
2342 vec4_visitor::~vec4_visitor()
2344 ralloc_free(this->mem_ctx
);
2345 hash_table_dtor(this->variable_ht
);
2350 vec4_visitor::fail(const char *format
, ...)
2360 va_start(va
, format
);
2361 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
2363 msg
= ralloc_asprintf(mem_ctx
, "VS compile failed: %s\n", msg
);
2365 this->fail_msg
= msg
;
2367 if (INTEL_DEBUG
& DEBUG_VS
) {
2368 fprintf(stderr
, "%s", msg
);
2372 } /* namespace brw */