2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_program.h"
27 #include "glsl/ir_uniform.h"
28 #include "program/sampler.h"
32 vec4_instruction::vec4_instruction(enum opcode opcode
, const dst_reg
&dst
,
33 const src_reg
&src0
, const src_reg
&src1
,
36 this->opcode
= opcode
;
41 this->saturate
= false;
42 this->force_writemask_all
= false;
43 this->no_dd_clear
= false;
44 this->no_dd_check
= false;
45 this->writes_accumulator
= false;
46 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
47 this->predicate
= BRW_PREDICATE_NONE
;
48 this->predicate_inverse
= false;
50 this->regs_written
= (dst
.file
== BAD_FILE
? 0 : 1);
51 this->shadow_compare
= false;
53 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
54 this->header_size
= 0;
55 this->flag_subreg
= 0;
59 this->annotation
= NULL
;
63 vec4_visitor::emit(vec4_instruction
*inst
)
65 inst
->ir
= this->base_ir
;
66 inst
->annotation
= this->current_annotation
;
68 this->instructions
.push_tail(inst
);
74 vec4_visitor::emit_before(bblock_t
*block
, vec4_instruction
*inst
,
75 vec4_instruction
*new_inst
)
77 new_inst
->ir
= inst
->ir
;
78 new_inst
->annotation
= inst
->annotation
;
80 inst
->insert_before(block
, new_inst
);
86 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
87 const src_reg
&src1
, const src_reg
&src2
)
89 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
, src2
));
94 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
97 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
));
101 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
)
103 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
));
107 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
)
109 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
));
113 vec4_visitor::emit(enum opcode opcode
)
115 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst_reg()));
120 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
122 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, src0); \
127 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
128 const src_reg &src1) \
130 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
134 #define ALU2_ACC(op) \
136 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
137 const src_reg &src1) \
139 vec4_instruction *inst = new(mem_ctx) vec4_instruction( \
140 BRW_OPCODE_##op, dst, src0, src1); \
141 inst->writes_accumulator = true; \
147 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
148 const src_reg &src1, const src_reg &src2) \
150 assert(devinfo->gen >= 6); \
151 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
188 /** Gen4 predicated IF. */
190 vec4_visitor::IF(enum brw_predicate predicate
)
192 vec4_instruction
*inst
;
194 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
);
195 inst
->predicate
= predicate
;
200 /** Gen6 IF with embedded comparison. */
202 vec4_visitor::IF(src_reg src0
, src_reg src1
,
203 enum brw_conditional_mod condition
)
205 assert(devinfo
->gen
== 6);
207 vec4_instruction
*inst
;
209 resolve_ud_negate(&src0
);
210 resolve_ud_negate(&src1
);
212 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
, dst_null_d(),
214 inst
->conditional_mod
= condition
;
220 * CMP: Sets the low bit of the destination channels with the result
221 * of the comparison, while the upper bits are undefined, and updates
222 * the flag register with the packed 16 bits of the result.
225 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
226 enum brw_conditional_mod condition
)
228 vec4_instruction
*inst
;
230 /* Take the instruction:
232 * CMP null<d> src0<f> src1<f>
234 * Original gen4 does type conversion to the destination type before
235 * comparison, producing garbage results for floating point comparisons.
237 * The destination type doesn't matter on newer generations, so we set the
238 * type to match src0 so we can compact the instruction.
240 dst
.type
= src0
.type
;
242 resolve_ud_negate(&src0
);
243 resolve_ud_negate(&src1
);
245 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_CMP
, dst
, src0
, src1
);
246 inst
->conditional_mod
= condition
;
252 vec4_visitor::SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
)
254 vec4_instruction
*inst
;
256 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ
,
258 inst
->base_mrf
= FIRST_SPILL_MRF(devinfo
->gen
) + 1;
265 vec4_visitor::SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
266 const src_reg
&index
)
268 vec4_instruction
*inst
;
270 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
272 inst
->base_mrf
= FIRST_SPILL_MRF(devinfo
->gen
);
279 vec4_visitor::fix_3src_operand(const src_reg
&src
)
281 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
282 * able to use vertical stride of zero to replicate the vec4 uniform, like
284 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
286 * But you can't, since vertical stride is always four in three-source
287 * instructions. Instead, insert a MOV instruction to do the replication so
288 * that the three-source instruction can consume it.
291 /* The MOV is only needed if the source is a uniform or immediate. */
292 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
295 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
298 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
299 expanded
.type
= src
.type
;
300 emit(VEC4_OPCODE_UNPACK_UNIFORM
, expanded
, src
);
301 return src_reg(expanded
);
305 vec4_visitor::resolve_source_modifiers(const src_reg
&src
)
307 if (!src
.abs
&& !src
.negate
)
310 dst_reg resolved
= dst_reg(this, glsl_type::ivec4_type
);
311 resolved
.type
= src
.type
;
312 emit(MOV(resolved
, src
));
314 return src_reg(resolved
);
318 vec4_visitor::fix_math_operand(const src_reg
&src
)
320 if (devinfo
->gen
< 6 || devinfo
->gen
>= 8 || src
.file
== BAD_FILE
)
323 /* The gen6 math instruction ignores the source modifiers --
324 * swizzle, abs, negate, and at least some parts of the register
325 * region description.
327 * Rather than trying to enumerate all these cases, *always* expand the
328 * operand to a temp GRF for gen6.
330 * For gen7, keep the operand as-is, except if immediate, which gen7 still
334 if (devinfo
->gen
== 7 && src
.file
!= IMM
)
337 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
338 expanded
.type
= src
.type
;
339 emit(MOV(expanded
, src
));
340 return src_reg(expanded
);
344 vec4_visitor::emit_math(enum opcode opcode
,
346 const src_reg
&src0
, const src_reg
&src1
)
348 vec4_instruction
*math
=
349 emit(opcode
, dst
, fix_math_operand(src0
), fix_math_operand(src1
));
351 if (devinfo
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
352 /* MATH on Gen6 must be align1, so we can't do writemasks. */
353 math
->dst
= dst_reg(this, glsl_type::vec4_type
);
354 math
->dst
.type
= dst
.type
;
355 math
= emit(MOV(dst
, src_reg(math
->dst
)));
356 } else if (devinfo
->gen
< 6) {
358 math
->mlen
= src1
.file
== BAD_FILE
? 1 : 2;
365 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
367 if (devinfo
->gen
< 7) {
368 unreachable("ir_unop_pack_half_2x16 should be lowered");
371 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
372 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
374 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
376 * Because this instruction does not have a 16-bit floating-point type,
377 * the destination data type must be Word (W).
379 * The destination must be DWord-aligned and specify a horizontal stride
380 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
381 * each destination channel and the upper word is not modified.
383 * The above restriction implies that the f32to16 instruction must use
384 * align1 mode, because only in align1 mode is it possible to specify
385 * horizontal stride. We choose here to defy the hardware docs and emit
386 * align16 instructions.
388 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
389 * instructions. I was partially successful in that the code passed all
390 * tests. However, the code was dubiously correct and fragile, and the
391 * tests were not harsh enough to probe that frailty. Not trusting the
392 * code, I chose instead to remain in align16 mode in defiance of the hw
395 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
396 * simulator, emitting a f32to16 in align16 mode with UD as destination
397 * data type is safe. The behavior differs from that specified in the PRM
398 * in that the upper word of each destination channel is cleared to 0.
401 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
402 src_reg
tmp_src(tmp_dst
);
405 /* Verify the undocumented behavior on which the following instructions
406 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
407 * then the result of the bit-or instruction below will be incorrect.
409 * You should inspect the disasm output in order to verify that the MOV is
410 * not optimized away.
412 emit(MOV(tmp_dst
, brw_imm_ud(0x12345678u
)));
415 /* Give tmp the form below, where "." means untouched.
418 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
420 * That the upper word of each write-channel be 0 is required for the
421 * following bit-shift and bit-or instructions to work. Note that this
422 * relies on the undocumented hardware behavior mentioned above.
424 tmp_dst
.writemask
= WRITEMASK_XY
;
425 emit(F32TO16(tmp_dst
, src0
));
427 /* Give the write-channels of dst the form:
430 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
431 emit(SHL(dst
, tmp_src
, brw_imm_ud(16u)));
433 /* Finally, give the write-channels of dst the form of packHalf2x16's
437 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
438 emit(OR(dst
, src_reg(dst
), tmp_src
));
442 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
444 if (devinfo
->gen
< 7) {
445 unreachable("ir_unop_unpack_half_2x16 should be lowered");
448 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
449 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
451 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
453 * Because this instruction does not have a 16-bit floating-point type,
454 * the source data type must be Word (W). The destination type must be
457 * To use W as the source data type, we must adjust horizontal strides,
458 * which is only possible in align1 mode. All my [chadv] attempts at
459 * emitting align1 instructions for unpackHalf2x16 failed to pass the
460 * Piglit tests, so I gave up.
462 * I've verified that, on gen7 hardware and the simulator, it is safe to
463 * emit f16to32 in align16 mode with UD as source data type.
466 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
467 src_reg
tmp_src(tmp_dst
);
469 tmp_dst
.writemask
= WRITEMASK_X
;
470 emit(AND(tmp_dst
, src0
, brw_imm_ud(0xffffu
)));
472 tmp_dst
.writemask
= WRITEMASK_Y
;
473 emit(SHR(tmp_dst
, src0
, brw_imm_ud(16u)));
475 dst
.writemask
= WRITEMASK_XY
;
476 emit(F16TO32(dst
, tmp_src
));
480 vec4_visitor::emit_unpack_unorm_4x8(const dst_reg
&dst
, src_reg src0
)
482 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
483 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
484 * is not suitable to generate the shift values, but we can use the packed
485 * vector float and a type-converting MOV.
487 dst_reg
shift(this, glsl_type::uvec4_type
);
488 emit(MOV(shift
, brw_imm_vf4(0x00, 0x60, 0x70, 0x78)));
490 dst_reg
shifted(this, glsl_type::uvec4_type
);
491 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
492 emit(SHR(shifted
, src0
, src_reg(shift
)));
494 shifted
.type
= BRW_REGISTER_TYPE_UB
;
495 dst_reg
f(this, glsl_type::vec4_type
);
496 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
498 emit(MUL(dst
, src_reg(f
), brw_imm_f(1.0f
/ 255.0f
)));
502 vec4_visitor::emit_unpack_snorm_4x8(const dst_reg
&dst
, src_reg src0
)
504 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
505 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
506 * is not suitable to generate the shift values, but we can use the packed
507 * vector float and a type-converting MOV.
509 dst_reg
shift(this, glsl_type::uvec4_type
);
510 emit(MOV(shift
, brw_imm_vf4(0x00, 0x60, 0x70, 0x78)));
512 dst_reg
shifted(this, glsl_type::uvec4_type
);
513 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
514 emit(SHR(shifted
, src0
, src_reg(shift
)));
516 shifted
.type
= BRW_REGISTER_TYPE_B
;
517 dst_reg
f(this, glsl_type::vec4_type
);
518 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
520 dst_reg
scaled(this, glsl_type::vec4_type
);
521 emit(MUL(scaled
, src_reg(f
), brw_imm_f(1.0f
/ 127.0f
)));
523 dst_reg
max(this, glsl_type::vec4_type
);
524 emit_minmax(BRW_CONDITIONAL_GE
, max
, src_reg(scaled
), brw_imm_f(-1.0f
));
525 emit_minmax(BRW_CONDITIONAL_L
, dst
, src_reg(max
), brw_imm_f(1.0f
));
529 vec4_visitor::emit_pack_unorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
531 dst_reg
saturated(this, glsl_type::vec4_type
);
532 vec4_instruction
*inst
= emit(MOV(saturated
, src0
));
533 inst
->saturate
= true;
535 dst_reg
scaled(this, glsl_type::vec4_type
);
536 emit(MUL(scaled
, src_reg(saturated
), brw_imm_f(255.0f
)));
538 dst_reg
rounded(this, glsl_type::vec4_type
);
539 emit(RNDE(rounded
, src_reg(scaled
)));
541 dst_reg
u(this, glsl_type::uvec4_type
);
542 emit(MOV(u
, src_reg(rounded
)));
545 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
549 vec4_visitor::emit_pack_snorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
551 dst_reg
max(this, glsl_type::vec4_type
);
552 emit_minmax(BRW_CONDITIONAL_GE
, max
, src0
, brw_imm_f(-1.0f
));
554 dst_reg
min(this, glsl_type::vec4_type
);
555 emit_minmax(BRW_CONDITIONAL_L
, min
, src_reg(max
), brw_imm_f(1.0f
));
557 dst_reg
scaled(this, glsl_type::vec4_type
);
558 emit(MUL(scaled
, src_reg(min
), brw_imm_f(127.0f
)));
560 dst_reg
rounded(this, glsl_type::vec4_type
);
561 emit(RNDE(rounded
, src_reg(scaled
)));
563 dst_reg
i(this, glsl_type::ivec4_type
);
564 emit(MOV(i
, src_reg(rounded
)));
567 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
571 * Returns the minimum number of vec4 elements needed to pack a type.
573 * For simple types, it will return 1 (a single vec4); for matrices, the
574 * number of columns; for array and struct, the sum of the vec4_size of
575 * each of its elements; and for sampler and atomic, zero.
577 * This method is useful to calculate how much register space is needed to
578 * store a particular type.
581 type_size_vec4(const struct glsl_type
*type
)
586 switch (type
->base_type
) {
589 case GLSL_TYPE_FLOAT
:
591 if (type
->is_matrix()) {
592 return type
->matrix_columns
;
594 /* Regardless of size of vector, it gets a vec4. This is bad
595 * packing for things like floats, but otherwise arrays become a
596 * mess. Hopefully a later pass over the code can pack scalars
597 * down if appropriate.
601 case GLSL_TYPE_ARRAY
:
602 assert(type
->length
> 0);
603 return type_size_vec4(type
->fields
.array
) * type
->length
;
604 case GLSL_TYPE_STRUCT
:
606 for (i
= 0; i
< type
->length
; i
++) {
607 size
+= type_size_vec4(type
->fields
.structure
[i
].type
);
610 case GLSL_TYPE_SUBROUTINE
:
613 case GLSL_TYPE_SAMPLER
:
614 /* Samplers take up no register space, since they're baked in at
618 case GLSL_TYPE_ATOMIC_UINT
:
620 case GLSL_TYPE_IMAGE
:
621 return DIV_ROUND_UP(BRW_IMAGE_PARAM_SIZE
, 4);
623 case GLSL_TYPE_DOUBLE
:
624 case GLSL_TYPE_ERROR
:
625 case GLSL_TYPE_INTERFACE
:
626 unreachable("not reached");
632 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
637 this->nr
= v
->alloc
.allocate(type_size_vec4(type
));
639 if (type
->is_array() || type
->is_record()) {
640 this->swizzle
= BRW_SWIZZLE_NOOP
;
642 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
645 this->type
= brw_type_for_base_type(type
);
648 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
)
655 this->nr
= v
->alloc
.allocate(type_size_vec4(type
) * size
);
657 this->swizzle
= BRW_SWIZZLE_NOOP
;
659 this->type
= brw_type_for_base_type(type
);
662 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
667 this->nr
= v
->alloc
.allocate(type_size_vec4(type
));
669 if (type
->is_array() || type
->is_record()) {
670 this->writemask
= WRITEMASK_XYZW
;
672 this->writemask
= (1 << type
->vector_elements
) - 1;
675 this->type
= brw_type_for_base_type(type
);
679 vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
680 src_reg src0
, src_reg src1
)
682 vec4_instruction
*inst
;
684 if (devinfo
->gen
>= 6) {
685 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
686 inst
->conditional_mod
= conditionalmod
;
688 emit(CMP(dst
, src0
, src1
, conditionalmod
));
690 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
691 inst
->predicate
= BRW_PREDICATE_NORMAL
;
698 vec4_visitor::emit_lrp(const dst_reg
&dst
,
699 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
701 if (devinfo
->gen
>= 6) {
702 /* Note that the instruction's argument order is reversed from GLSL
705 return emit(LRP(dst
, fix_3src_operand(a
), fix_3src_operand(y
),
706 fix_3src_operand(x
)));
708 /* Earlier generations don't support three source operations, so we
709 * need to emit x*(1-a) + y*a.
711 dst_reg y_times_a
= dst_reg(this, glsl_type::vec4_type
);
712 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
713 dst_reg x_times_one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
714 y_times_a
.writemask
= dst
.writemask
;
715 one_minus_a
.writemask
= dst
.writemask
;
716 x_times_one_minus_a
.writemask
= dst
.writemask
;
718 emit(MUL(y_times_a
, y
, a
));
719 emit(ADD(one_minus_a
, negate(a
), brw_imm_f(1.0f
)));
720 emit(MUL(x_times_one_minus_a
, x
, src_reg(one_minus_a
)));
721 return emit(ADD(dst
, src_reg(x_times_one_minus_a
), src_reg(y_times_a
)));
726 * Emits the instructions needed to perform a pull constant load. before_block
727 * and before_inst can be NULL in which case the instruction will be appended
728 * to the end of the instruction list.
731 vec4_visitor::emit_pull_constant_load_reg(dst_reg dst
,
734 bblock_t
*before_block
,
735 vec4_instruction
*before_inst
)
737 assert((before_inst
== NULL
&& before_block
== NULL
) ||
738 (before_inst
&& before_block
));
740 vec4_instruction
*pull
;
742 if (devinfo
->gen
>= 9) {
743 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
744 src_reg
header(this, glsl_type::uvec4_type
, 2);
747 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
751 emit_before(before_block
, before_inst
, pull
);
755 dst_reg index_reg
= retype(offset(dst_reg(header
), 1),
757 pull
= MOV(writemask(index_reg
, WRITEMASK_X
), offset_reg
);
760 emit_before(before_block
, before_inst
, pull
);
764 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
769 pull
->header_size
= 1;
770 } else if (devinfo
->gen
>= 7) {
771 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
773 grf_offset
.type
= offset_reg
.type
;
775 pull
= MOV(grf_offset
, offset_reg
);
778 emit_before(before_block
, before_inst
, pull
);
782 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
785 src_reg(grf_offset
));
788 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD
,
792 pull
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
797 emit_before(before_block
, before_inst
, pull
);
803 vec4_visitor::emit_uniformize(const src_reg
&src
)
805 const src_reg
chan_index(this, glsl_type::uint_type
);
806 const dst_reg dst
= retype(dst_reg(this, glsl_type::uint_type
),
809 emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, dst_reg(chan_index
))
810 ->force_writemask_all
= true;
811 emit(SHADER_OPCODE_BROADCAST
, dst
, src
, chan_index
)
812 ->force_writemask_all
= true;
818 vec4_visitor::emit_mcs_fetch(const glsl_type
*coordinate_type
,
819 src_reg coordinate
, src_reg sampler
)
821 vec4_instruction
*inst
=
822 new(mem_ctx
) vec4_instruction(SHADER_OPCODE_TXF_MCS
,
823 dst_reg(this, glsl_type::uvec4_type
));
825 inst
->src
[1] = sampler
;
829 if (devinfo
->gen
>= 9) {
830 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
831 vec4_instruction
*header_inst
= new(mem_ctx
)
832 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
833 dst_reg(MRF
, inst
->base_mrf
));
838 inst
->header_size
= 1;
839 param_base
= inst
->base_mrf
+ 1;
842 param_base
= inst
->base_mrf
;
845 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
846 int coord_mask
= (1 << coordinate_type
->vector_elements
) - 1;
847 int zero_mask
= 0xf & ~coord_mask
;
849 emit(MOV(dst_reg(MRF
, param_base
, coordinate_type
, coord_mask
),
852 emit(MOV(dst_reg(MRF
, param_base
, coordinate_type
, zero_mask
),
856 return src_reg(inst
->dst
);
860 vec4_visitor::is_high_sampler(src_reg sampler
)
862 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
865 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
869 vec4_visitor::emit_texture(ir_texture_opcode op
,
871 const glsl_type
*dest_type
,
873 int coord_components
,
874 src_reg shadow_comparitor
,
875 src_reg lod
, src_reg lod2
,
876 src_reg sample_index
,
877 uint32_t constant_offset
,
878 src_reg offset_value
,
884 /* The sampler can only meaningfully compute LOD for fragment shader
885 * messages. For all other stages, we change the opcode to TXL and hardcode
888 * textureQueryLevels() is implemented in terms of TXS so we need to pass a
889 * valid LOD argument.
891 if (op
== ir_tex
|| op
== ir_query_levels
) {
892 assert(lod
.file
== BAD_FILE
);
893 lod
= brw_imm_f(0.0f
);
898 case ir_tex
: opcode
= SHADER_OPCODE_TXL
; break;
899 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
900 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
901 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
902 case ir_txf_ms
: opcode
= (devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W
:
903 SHADER_OPCODE_TXF_CMS
); break;
904 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
905 case ir_tg4
: opcode
= offset_value
.file
!= BAD_FILE
906 ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4
; break;
907 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
908 case ir_texture_samples
: opcode
= SHADER_OPCODE_SAMPLEINFO
; break;
910 unreachable("TXB is not valid for vertex shaders.");
912 unreachable("LOD is not valid for vertex shaders.");
913 case ir_samples_identical
: {
914 /* There are some challenges implementing this for vec4, and it seems
915 * unlikely to be used anyway. For now, just return false ways.
917 emit(MOV(dest
, brw_imm_ud(0u)));
921 unreachable("Unrecognized tex op");
924 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(opcode
, dest
);
926 inst
->offset
= constant_offset
;
928 /* The message header is necessary for:
930 * - Gen9+ for selecting SIMD4x2
932 * - Gather channel selection
933 * - Sampler indices too large to fit in a 4-bit value.
934 * - Sampleinfo message - takes no parameters, but mlen = 0 is illegal
937 (devinfo
->gen
< 5 || devinfo
->gen
>= 9 ||
938 inst
->offset
!= 0 || op
== ir_tg4
||
939 op
== ir_texture_samples
||
940 is_high_sampler(sampler_reg
)) ? 1 : 0;
942 inst
->mlen
= inst
->header_size
;
943 inst
->dst
.writemask
= WRITEMASK_XYZW
;
944 inst
->shadow_compare
= shadow_comparitor
.file
!= BAD_FILE
;
946 inst
->src
[1] = sampler_reg
;
948 /* MRF for the first parameter */
949 int param_base
= inst
->base_mrf
+ inst
->header_size
;
951 if (op
== ir_txs
|| op
== ir_query_levels
) {
952 int writemask
= devinfo
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
953 emit(MOV(dst_reg(MRF
, param_base
, lod
.type
, writemask
), lod
));
955 } else if (op
== ir_texture_samples
) {
956 inst
->dst
.writemask
= WRITEMASK_X
;
958 /* Load the coordinate */
959 /* FINISHME: gl_clamp_mask and saturate */
960 int coord_mask
= (1 << coord_components
) - 1;
961 int zero_mask
= 0xf & ~coord_mask
;
963 emit(MOV(dst_reg(MRF
, param_base
, coordinate
.type
, coord_mask
),
967 if (zero_mask
!= 0) {
968 emit(MOV(dst_reg(MRF
, param_base
, coordinate
.type
, zero_mask
),
971 /* Load the shadow comparitor */
972 if (shadow_comparitor
.file
!= BAD_FILE
&& op
!= ir_txd
&& (op
!= ir_tg4
|| offset_value
.file
== BAD_FILE
)) {
973 emit(MOV(dst_reg(MRF
, param_base
+ 1, shadow_comparitor
.type
,
979 /* Load the LOD info */
980 if (op
== ir_tex
|| op
== ir_txl
) {
982 if (devinfo
->gen
>= 5) {
983 mrf
= param_base
+ 1;
984 if (shadow_comparitor
.file
!= BAD_FILE
) {
985 writemask
= WRITEMASK_Y
;
986 /* mlen already incremented */
988 writemask
= WRITEMASK_X
;
991 } else /* devinfo->gen == 4 */ {
993 writemask
= WRITEMASK_W
;
995 emit(MOV(dst_reg(MRF
, mrf
, lod
.type
, writemask
), lod
));
996 } else if (op
== ir_txf
) {
997 emit(MOV(dst_reg(MRF
, param_base
, lod
.type
, WRITEMASK_W
), lod
));
998 } else if (op
== ir_txf_ms
) {
999 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index
.type
, WRITEMASK_X
),
1001 if (opcode
== SHADER_OPCODE_TXF_CMS_W
) {
1002 /* MCS data is stored in the first two channels of ‘mcs’, but we
1003 * need to get it into the .y and .z channels of the second vec4
1006 mcs
.swizzle
= BRW_SWIZZLE4(0, 0, 1, 1);
1007 emit(MOV(dst_reg(MRF
, param_base
+ 1,
1008 glsl_type::uint_type
, WRITEMASK_YZ
),
1010 } else if (devinfo
->gen
>= 7) {
1011 /* MCS data is in the first channel of `mcs`, but we need to get it into
1012 * the .y channel of the second vec4 of params, so replicate .x across
1013 * the whole vec4 and then mask off everything except .y
1015 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
1016 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
1020 } else if (op
== ir_txd
) {
1021 const brw_reg_type type
= lod
.type
;
1023 if (devinfo
->gen
>= 5) {
1024 lod
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
1025 lod2
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
1026 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), lod
));
1027 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), lod2
));
1030 if (dest_type
->vector_elements
== 3 || shadow_comparitor
.file
!= BAD_FILE
) {
1031 lod
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1032 lod2
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1033 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), lod
));
1034 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), lod2
));
1037 if (shadow_comparitor
.file
!= BAD_FILE
) {
1038 emit(MOV(dst_reg(MRF
, param_base
+ 2,
1039 shadow_comparitor
.type
, WRITEMASK_Z
),
1040 shadow_comparitor
));
1043 } else /* devinfo->gen == 4 */ {
1044 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), lod
));
1045 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), lod2
));
1048 } else if (op
== ir_tg4
&& offset_value
.file
!= BAD_FILE
) {
1049 if (shadow_comparitor
.file
!= BAD_FILE
) {
1050 emit(MOV(dst_reg(MRF
, param_base
, shadow_comparitor
.type
, WRITEMASK_W
),
1051 shadow_comparitor
));
1054 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
1062 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
1063 * spec requires layers.
1065 if (op
== ir_txs
&& is_cube_array
) {
1066 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
1067 writemask(inst
->dst
, WRITEMASK_Z
),
1068 src_reg(inst
->dst
), brw_imm_d(6));
1071 if (devinfo
->gen
== 6 && op
== ir_tg4
) {
1072 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], inst
->dst
);
1075 if (op
== ir_query_levels
) {
1076 /* # levels is in .w */
1077 src_reg
swizzled(dest
);
1078 swizzled
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
,
1079 SWIZZLE_W
, SWIZZLE_W
);
1080 emit(MOV(dest
, swizzled
));
1085 * Apply workarounds for Gen6 gather with UINT/SINT
1088 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
1093 int width
= (wa
& WA_8BIT
) ? 8 : 16;
1094 dst_reg dst_f
= dst
;
1095 dst_f
.type
= BRW_REGISTER_TYPE_F
;
1097 /* Convert from UNORM to UINT */
1098 emit(MUL(dst_f
, src_reg(dst_f
), brw_imm_f((float)((1 << width
) - 1))));
1099 emit(MOV(dst
, src_reg(dst_f
)));
1102 /* Reinterpret the UINT value as a signed INT value by
1103 * shifting the sign bit into place, then shifting back
1106 emit(SHL(dst
, src_reg(dst
), brw_imm_d(32 - width
)));
1107 emit(ASR(dst
, src_reg(dst
), brw_imm_d(32 - width
)));
1112 vec4_visitor::gs_emit_vertex(int stream_id
)
1114 unreachable("not reached");
1118 vec4_visitor::gs_end_primitive()
1120 unreachable("not reached");
1124 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
1125 dst_reg dst
, src_reg surf_offset
,
1126 src_reg src0
, src_reg src1
)
1128 unsigned mlen
= 1 + (src0
.file
!= BAD_FILE
) + (src1
.file
!= BAD_FILE
);
1129 src_reg
src_payload(this, glsl_type::uint_type
, mlen
);
1130 dst_reg
payload(src_payload
);
1131 payload
.writemask
= WRITEMASK_X
;
1133 /* Set the atomic operation offset. */
1134 emit(MOV(offset(payload
, 0), surf_offset
));
1137 /* Set the atomic operation arguments. */
1138 if (src0
.file
!= BAD_FILE
) {
1139 emit(MOV(offset(payload
, i
), src0
));
1143 if (src1
.file
!= BAD_FILE
) {
1144 emit(MOV(offset(payload
, i
), src1
));
1148 /* Emit the instruction. Note that this maps to the normal SIMD8
1149 * untyped atomic message on Ivy Bridge, but that's OK because
1150 * unused channels will be masked out.
1152 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
1154 brw_imm_ud(surf_index
), brw_imm_ud(atomic_op
));
1159 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
1160 src_reg surf_offset
)
1162 dst_reg
offset(this, glsl_type::uint_type
);
1163 offset
.writemask
= WRITEMASK_X
;
1165 /* Set the surface read offset. */
1166 emit(MOV(offset
, surf_offset
));
1168 /* Emit the instruction. Note that this maps to the normal SIMD8
1169 * untyped surface read message, but that's OK because unused
1170 * channels will be masked out.
1172 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
,
1174 brw_imm_ud(surf_index
), brw_imm_d(1));
1179 vec4_visitor::emit_ndc_computation()
1181 if (output_reg
[VARYING_SLOT_POS
].file
== BAD_FILE
)
1184 /* Get the position */
1185 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
1187 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
1188 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
1189 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
1191 current_annotation
= "NDC";
1192 dst_reg ndc_w
= ndc
;
1193 ndc_w
.writemask
= WRITEMASK_W
;
1194 src_reg pos_w
= pos
;
1195 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
1196 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
1198 dst_reg ndc_xyz
= ndc
;
1199 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
1201 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
1205 vec4_visitor::emit_psiz_and_flags(dst_reg reg
)
1207 if (devinfo
->gen
< 6 &&
1208 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
1209 output_reg
[VARYING_SLOT_CLIP_DIST0
].file
!= BAD_FILE
||
1210 devinfo
->has_negative_rhw_bug
)) {
1211 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
1212 dst_reg header1_w
= header1
;
1213 header1_w
.writemask
= WRITEMASK_W
;
1215 emit(MOV(header1
, brw_imm_ud(0u)));
1217 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
1218 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
1220 current_annotation
= "Point size";
1221 emit(MUL(header1_w
, psiz
, brw_imm_f((float)(1 << 11))));
1222 emit(AND(header1_w
, src_reg(header1_w
), brw_imm_d(0x7ff << 8)));
1225 if (output_reg
[VARYING_SLOT_CLIP_DIST0
].file
!= BAD_FILE
) {
1226 current_annotation
= "Clipping flags";
1227 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
1228 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
1230 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), brw_imm_f(0.0f
), BRW_CONDITIONAL_L
));
1231 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, brw_imm_d(0));
1232 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
1234 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), brw_imm_f(0.0f
), BRW_CONDITIONAL_L
));
1235 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, brw_imm_d(0));
1236 emit(SHL(flags1
, src_reg(flags1
), brw_imm_d(4)));
1237 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
1240 /* i965 clipping workaround:
1241 * 1) Test for -ve rhw
1243 * set ndc = (0,0,0,0)
1246 * Later, clipping will detect ucp[6] and ensure the primitive is
1247 * clipped against all fixed planes.
1249 if (devinfo
->has_negative_rhw_bug
&&
1250 output_reg
[BRW_VARYING_SLOT_NDC
].file
!= BAD_FILE
) {
1251 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
1252 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
1253 emit(CMP(dst_null_f(), ndc_w
, brw_imm_f(0.0f
), BRW_CONDITIONAL_L
));
1254 vec4_instruction
*inst
;
1255 inst
= emit(OR(header1_w
, src_reg(header1_w
), brw_imm_ud(1u << 6)));
1256 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1257 output_reg
[BRW_VARYING_SLOT_NDC
].type
= BRW_REGISTER_TYPE_F
;
1258 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], brw_imm_f(0.0f
)));
1259 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1262 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
1263 } else if (devinfo
->gen
< 6) {
1264 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u)));
1266 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), brw_imm_d(0)));
1267 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
1268 dst_reg reg_w
= reg
;
1269 reg_w
.writemask
= WRITEMASK_W
;
1270 src_reg reg_as_src
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
1271 reg_as_src
.type
= reg_w
.type
;
1272 reg_as_src
.swizzle
= brw_swizzle_for_size(1);
1273 emit(MOV(reg_w
, reg_as_src
));
1275 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
1276 dst_reg reg_y
= reg
;
1277 reg_y
.writemask
= WRITEMASK_Y
;
1278 reg_y
.type
= BRW_REGISTER_TYPE_D
;
1279 output_reg
[VARYING_SLOT_LAYER
].type
= reg_y
.type
;
1280 emit(MOV(reg_y
, src_reg(output_reg
[VARYING_SLOT_LAYER
])));
1282 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
1283 dst_reg reg_z
= reg
;
1284 reg_z
.writemask
= WRITEMASK_Z
;
1285 reg_z
.type
= BRW_REGISTER_TYPE_D
;
1286 output_reg
[VARYING_SLOT_VIEWPORT
].type
= reg_z
.type
;
1287 emit(MOV(reg_z
, src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
1293 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
1295 assert(varying
< VARYING_SLOT_MAX
);
1296 assert(output_reg
[varying
].type
== reg
.type
);
1297 current_annotation
= output_reg_annotation
[varying
];
1298 if (output_reg
[varying
].file
!= BAD_FILE
)
1299 return emit(MOV(reg
, src_reg(output_reg
[varying
])));
1305 vec4_visitor::emit_urb_slot(dst_reg reg
, int varying
)
1307 reg
.type
= BRW_REGISTER_TYPE_F
;
1308 output_reg
[varying
].type
= reg
.type
;
1311 case VARYING_SLOT_PSIZ
:
1313 /* PSIZ is always in slot 0, and is coupled with other flags. */
1314 current_annotation
= "indices, point width, clip flags";
1315 emit_psiz_and_flags(reg
);
1318 case BRW_VARYING_SLOT_NDC
:
1319 current_annotation
= "NDC";
1320 if (output_reg
[BRW_VARYING_SLOT_NDC
].file
!= BAD_FILE
)
1321 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
1323 case VARYING_SLOT_POS
:
1324 current_annotation
= "gl_Position";
1325 if (output_reg
[VARYING_SLOT_POS
].file
!= BAD_FILE
)
1326 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
1328 case VARYING_SLOT_EDGE
:
1329 /* This is present when doing unfilled polygons. We're supposed to copy
1330 * the edge flag from the user-provided vertex array
1331 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
1332 * of that attribute (starts as 1.0f). This is then used in clipping to
1333 * determine which edges should be drawn as wireframe.
1335 current_annotation
= "edge flag";
1336 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
1337 glsl_type::float_type
, WRITEMASK_XYZW
))));
1339 case BRW_VARYING_SLOT_PAD
:
1340 /* No need to write to this slot */
1343 emit_generic_urb_slot(reg
, varying
);
1349 align_interleaved_urb_mlen(const struct brw_device_info
*devinfo
, int mlen
)
1351 if (devinfo
->gen
>= 6) {
1352 /* URB data written (does not include the message header reg) must
1353 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
1354 * section 5.4.3.2.2: URB_INTERLEAVED.
1356 * URB entries are allocated on a multiple of 1024 bits, so an
1357 * extra 128 bits written here to make the end align to 256 is
1360 if ((mlen
% 2) != 1)
1369 * Generates the VUE payload plus the necessary URB write instructions to
1372 * The VUE layout is documented in Volume 2a.
1375 vec4_visitor::emit_vertex()
1377 /* MRF 0 is reserved for the debugger, so start with message header
1382 /* In the process of generating our URB write message contents, we
1383 * may need to unspill a register or load from an array. Those
1384 * reads would use MRFs 14-15.
1386 int max_usable_mrf
= FIRST_SPILL_MRF(devinfo
->gen
);
1388 /* The following assertion verifies that max_usable_mrf causes an
1389 * even-numbered amount of URB write data, which will meet gen6's
1390 * requirements for length alignment.
1392 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
1394 /* First mrf is the g0-based message header containing URB handles and
1397 emit_urb_write_header(mrf
++);
1399 if (devinfo
->gen
< 6) {
1400 emit_ndc_computation();
1403 /* We may need to split this up into several URB writes, so do them in a
1407 bool complete
= false;
1409 /* URB offset is in URB row increments, and each of our MRFs is half of
1410 * one of those, since we're doing interleaved writes.
1412 int offset
= slot
/ 2;
1415 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
1416 emit_urb_slot(dst_reg(MRF
, mrf
++),
1417 prog_data
->vue_map
.slot_to_varying
[slot
]);
1419 /* If this was max_usable_mrf, we can't fit anything more into this
1420 * URB WRITE. Same thing if we reached the maximum length available.
1422 if (mrf
> max_usable_mrf
||
1423 align_interleaved_urb_mlen(devinfo
, mrf
- base_mrf
+ 1) > BRW_MAX_MSG_LENGTH
) {
1429 complete
= slot
>= prog_data
->vue_map
.num_slots
;
1430 current_annotation
= "URB write";
1431 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
1432 inst
->base_mrf
= base_mrf
;
1433 inst
->mlen
= align_interleaved_urb_mlen(devinfo
, mrf
- base_mrf
);
1434 inst
->offset
+= offset
;
1440 vec4_visitor::get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
1441 src_reg
*reladdr
, int reg_offset
)
1443 /* Because we store the values to scratch interleaved like our
1444 * vertex data, we need to scale the vec4 index by 2.
1446 int message_header_scale
= 2;
1448 /* Pre-gen6, the message header uses byte offsets instead of vec4
1449 * (16-byte) offset units.
1451 if (devinfo
->gen
< 6)
1452 message_header_scale
*= 16;
1455 src_reg index
= src_reg(this, glsl_type::int_type
);
1457 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
1458 brw_imm_d(reg_offset
)));
1459 emit_before(block
, inst
, MUL(dst_reg(index
), index
,
1460 brw_imm_d(message_header_scale
)));
1464 return brw_imm_d(reg_offset
* message_header_scale
);
1469 vec4_visitor::get_pull_constant_offset(bblock_t
* block
, vec4_instruction
*inst
,
1470 src_reg
*reladdr
, int reg_offset
)
1473 src_reg index
= src_reg(this, glsl_type::int_type
);
1475 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
1476 brw_imm_d(reg_offset
)));
1478 /* Pre-gen6, the message header uses byte offsets instead of vec4
1479 * (16-byte) offset units.
1481 if (devinfo
->gen
< 6) {
1482 emit_before(block
, inst
, MUL(dst_reg(index
), index
, brw_imm_d(16)));
1486 } else if (devinfo
->gen
>= 8) {
1487 /* Store the offset in a GRF so we can send-from-GRF. */
1488 src_reg offset
= src_reg(this, glsl_type::int_type
);
1489 emit_before(block
, inst
, MOV(dst_reg(offset
), brw_imm_d(reg_offset
)));
1492 int message_header_scale
= devinfo
->gen
< 6 ? 16 : 1;
1493 return brw_imm_d(reg_offset
* message_header_scale
);
1498 * Emits an instruction before @inst to load the value named by @orig_src
1499 * from scratch space at @base_offset to @temp.
1501 * @base_offset is measured in 32-byte units (the size of a register).
1504 vec4_visitor::emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
1505 dst_reg temp
, src_reg orig_src
,
1508 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
1509 src_reg index
= get_scratch_offset(block
, inst
, orig_src
.reladdr
,
1512 emit_before(block
, inst
, SCRATCH_READ(temp
, index
));
1516 * Emits an instruction after @inst to store the value to be written
1517 * to @orig_dst to scratch space at @base_offset, from @temp.
1519 * @base_offset is measured in 32-byte units (the size of a register).
1522 vec4_visitor::emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
1525 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
1526 src_reg index
= get_scratch_offset(block
, inst
, inst
->dst
.reladdr
,
1529 /* Create a temporary register to store *inst's result in.
1531 * We have to be careful in MOVing from our temporary result register in
1532 * the scratch write. If we swizzle from channels of the temporary that
1533 * weren't initialized, it will confuse live interval analysis, which will
1534 * make spilling fail to make progress.
1536 const src_reg temp
= swizzle(retype(src_reg(this, glsl_type::vec4_type
),
1538 brw_swizzle_for_mask(inst
->dst
.writemask
));
1539 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
1540 inst
->dst
.writemask
));
1541 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
1542 if (inst
->opcode
!= BRW_OPCODE_SEL
)
1543 write
->predicate
= inst
->predicate
;
1544 write
->ir
= inst
->ir
;
1545 write
->annotation
= inst
->annotation
;
1546 inst
->insert_after(block
, write
);
1548 inst
->dst
.file
= temp
.file
;
1549 inst
->dst
.nr
= temp
.nr
;
1550 inst
->dst
.reg_offset
= temp
.reg_offset
;
1551 inst
->dst
.reladdr
= NULL
;
1555 * Checks if \p src and/or \p src.reladdr require a scratch read, and if so,
1556 * adds the scratch read(s) before \p inst. The function also checks for
1557 * recursive reladdr scratch accesses, issuing the corresponding scratch
1558 * loads and rewriting reladdr references accordingly.
1560 * \return \p src if it did not require a scratch load, otherwise, the
1561 * register holding the result of the scratch load that the caller should
1562 * use to rewrite src.
1565 vec4_visitor::emit_resolve_reladdr(int scratch_loc
[], bblock_t
*block
,
1566 vec4_instruction
*inst
, src_reg src
)
1568 /* Resolve recursive reladdr scratch access by calling ourselves
1572 *src
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
1575 /* Now handle scratch access on src */
1576 if (src
.file
== VGRF
&& scratch_loc
[src
.nr
] != -1) {
1577 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
1578 emit_scratch_read(block
, inst
, temp
, src
, scratch_loc
[src
.nr
]);
1580 src
.reg_offset
= temp
.reg_offset
;
1588 * We can't generally support array access in GRF space, because a
1589 * single instruction's destination can only span 2 contiguous
1590 * registers. So, we send all GRF arrays that get variable index
1591 * access to scratch space.
1594 vec4_visitor::move_grf_array_access_to_scratch()
1596 int scratch_loc
[this->alloc
.count
];
1597 memset(scratch_loc
, -1, sizeof(scratch_loc
));
1599 /* First, calculate the set of virtual GRFs that need to be punted
1600 * to scratch due to having any array access on them, and where in
1603 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1604 if (inst
->dst
.file
== VGRF
&& inst
->dst
.reladdr
) {
1605 if (scratch_loc
[inst
->dst
.nr
] == -1) {
1606 scratch_loc
[inst
->dst
.nr
] = last_scratch
;
1607 last_scratch
+= this->alloc
.sizes
[inst
->dst
.nr
];
1610 for (src_reg
*iter
= inst
->dst
.reladdr
;
1612 iter
= iter
->reladdr
) {
1613 if (iter
->file
== VGRF
&& scratch_loc
[iter
->nr
] == -1) {
1614 scratch_loc
[iter
->nr
] = last_scratch
;
1615 last_scratch
+= this->alloc
.sizes
[iter
->nr
];
1620 for (int i
= 0 ; i
< 3; i
++) {
1621 for (src_reg
*iter
= &inst
->src
[i
];
1623 iter
= iter
->reladdr
) {
1624 if (iter
->file
== VGRF
&& scratch_loc
[iter
->nr
] == -1) {
1625 scratch_loc
[iter
->nr
] = last_scratch
;
1626 last_scratch
+= this->alloc
.sizes
[iter
->nr
];
1632 /* Now, for anything that will be accessed through scratch, rewrite
1633 * it to load/store. Note that this is a _safe list walk, because
1634 * we may generate a new scratch_write instruction after the one
1637 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1638 /* Set up the annotation tracking for new generated instructions. */
1640 current_annotation
= inst
->annotation
;
1642 /* First handle scratch access on the dst. Notice we have to handle
1643 * the case where the dst's reladdr also points to scratch space.
1645 if (inst
->dst
.reladdr
)
1646 *inst
->dst
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
1647 *inst
->dst
.reladdr
);
1649 /* Now that we have handled any (possibly recursive) reladdr scratch
1650 * accesses for dst we can safely do the scratch write for dst itself
1652 if (inst
->dst
.file
== VGRF
&& scratch_loc
[inst
->dst
.nr
] != -1)
1653 emit_scratch_write(block
, inst
, scratch_loc
[inst
->dst
.nr
]);
1655 /* Now handle scratch access on any src. In this case, since inst->src[i]
1656 * already is a src_reg, we can just call emit_resolve_reladdr with
1657 * inst->src[i] and it will take care of handling scratch loads for
1658 * both src and src.reladdr (recursively).
1660 for (int i
= 0 ; i
< 3; i
++) {
1661 inst
->src
[i
] = emit_resolve_reladdr(scratch_loc
, block
, inst
,
1668 * Emits an instruction before @inst to load the value named by @orig_src
1669 * from the pull constant buffer (surface) at @base_offset to @temp.
1672 vec4_visitor::emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
1673 dst_reg temp
, src_reg orig_src
,
1676 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
1677 const unsigned index
= prog_data
->base
.binding_table
.pull_constants_start
;
1678 src_reg offset
= get_pull_constant_offset(block
, inst
, orig_src
.reladdr
,
1681 emit_pull_constant_load_reg(temp
,
1686 brw_mark_surface_used(&prog_data
->base
, index
);
1690 * Implements array access of uniforms by inserting a
1691 * PULL_CONSTANT_LOAD instruction.
1693 * Unlike temporary GRF array access (where we don't support it due to
1694 * the difficulty of doing relative addressing on instruction
1695 * destinations), we could potentially do array access of uniforms
1696 * that were loaded in GRF space as push constants. In real-world
1697 * usage we've seen, though, the arrays being used are always larger
1698 * than we could load as push constants, so just always move all
1699 * uniform array access out to a pull constant buffer.
1702 vec4_visitor::move_uniform_array_access_to_pull_constants()
1704 int pull_constant_loc
[this->uniforms
];
1705 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
));
1706 bool nested_reladdr
;
1708 /* Walk through and find array access of uniforms. Put a copy of that
1709 * uniform in the pull constant buffer.
1711 * Note that we don't move constant-indexed accesses to arrays. No
1712 * testing has been done of the performance impact of this choice.
1715 nested_reladdr
= false;
1717 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1718 for (int i
= 0 ; i
< 3; i
++) {
1719 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1722 int uniform
= inst
->src
[i
].nr
;
1724 if (inst
->src
[i
].reladdr
->reladdr
)
1725 nested_reladdr
= true; /* will need another pass */
1727 /* If this array isn't already present in the pull constant buffer,
1730 if (pull_constant_loc
[uniform
] == -1) {
1731 const gl_constant_value
**values
=
1732 &stage_prog_data
->param
[uniform
* 4];
1734 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
1736 assert(uniform
< uniform_array_size
);
1737 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
1738 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
1743 /* Set up the annotation tracking for new generated instructions. */
1745 current_annotation
= inst
->annotation
;
1747 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
1749 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
1750 pull_constant_loc
[uniform
]);
1752 inst
->src
[i
].file
= temp
.file
;
1753 inst
->src
[i
].nr
= temp
.nr
;
1754 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
1755 inst
->src
[i
].reladdr
= NULL
;
1758 } while (nested_reladdr
);
1760 /* Now there are no accesses of the UNIFORM file with a reladdr, so
1761 * no need to track them as larger-than-vec4 objects. This will be
1762 * relied on in cutting out unused uniform vectors from push
1765 split_uniform_registers();
1769 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
1771 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
1775 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
1776 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
1780 vec4_visitor::vec4_visitor(const struct brw_compiler
*compiler
,
1782 const struct brw_sampler_prog_key_data
*key_tex
,
1783 struct brw_vue_prog_data
*prog_data
,
1784 const nir_shader
*shader
,
1787 int shader_time_index
)
1788 : backend_shader(compiler
, log_data
, mem_ctx
, shader
, &prog_data
->base
),
1790 prog_data(prog_data
),
1792 first_non_payload_grf(0),
1793 need_all_constants_in_pull_buffer(false),
1794 no_spills(no_spills
),
1795 shader_time_index(shader_time_index
),
1798 this->failed
= false;
1800 this->base_ir
= NULL
;
1801 this->current_annotation
= NULL
;
1802 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
1804 this->virtual_grf_start
= NULL
;
1805 this->virtual_grf_end
= NULL
;
1806 this->live_intervals
= NULL
;
1808 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1812 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
1813 * at least one. See setup_uniforms() in brw_vec4.cpp.
1815 this->uniform_array_size
= 1;
1817 this->uniform_array_size
=
1818 MAX2(DIV_ROUND_UP(stage_prog_data
->nr_params
, 4), 1);
1821 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
1824 vec4_visitor::~vec4_visitor()
1830 vec4_visitor::fail(const char *format
, ...)
1840 va_start(va
, format
);
1841 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
1843 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
1845 this->fail_msg
= msg
;
1847 if (debug_enabled
) {
1848 fprintf(stderr
, "%s", msg
);
1852 } /* namespace brw */