src/mesa/drivers/dri/i965/brw_vs.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/compiler.h"
  34 #include "brw_context.h"
  35 #include "brw_vs.h"
  36 #include "brw_util.h"
  37 #include "brw_state.h"
  38 #include "program/prog_print.h"
  39 #include "program/prog_parameter.h"
  40
  41 #include "glsl/ralloc.h"
  42
  43 static inline void assign_vue_slot(struct brw_vue_map *vue_map,
  44                                    int varying)
  45 {
  46    /* Make sure this varying hasn't been assigned a slot already */
  47    assert (vue_map->varying_to_slot[varying] == -1);
  48
  49    vue_map->varying_to_slot[varying] = vue_map->num_slots;
  50    vue_map->slot_to_varying[vue_map->num_slots++] = varying;
  51 }
  52
  53 /**
  54  * Compute the VUE map for vertex shader program.
  55  *
  56  * Note that consumers of this map using cache keys must include
  57  * prog_data->userclip and prog_data->outputs_written in their key
  58  * (generated by CACHE_NEW_VS_PROG).
  59  */
  60 void
  61 brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
  62                     GLbitfield64 slots_valid, bool userclip_active)
  63 {
  64    const struct intel_context *intel = &brw->intel;
  65
  66    vue_map->slots_valid = slots_valid;
  67    int i;
  68
  69    /* Make sure that the values we store in vue_map->varying_to_slot and
  70     * vue_map->slot_to_varying won't overflow the signed chars that are used
  71     * to store them.  Note that since vue_map->slot_to_varying sometimes holds
  72     * values equal to BRW_VARYING_SLOT_COUNT, we need to ensure that
  73     * BRW_VARYING_SLOT_COUNT is <= 127, not 128.
  74     */
  75    STATIC_ASSERT(BRW_VARYING_SLOT_COUNT <= 127);
  76
  77    vue_map->num_slots = 0;
  78    for (i = 0; i < BRW_VARYING_SLOT_COUNT; ++i) {
  79       vue_map->varying_to_slot[i] = -1;
  80       vue_map->slot_to_varying[i] = BRW_VARYING_SLOT_COUNT;
  81    }
  82
  83    /* VUE header: format depends on chip generation and whether clipping is
  84     * enabled.
  85     */
  86    switch (intel->gen) {
  87    case 4:
  88    case 5:
  89       /* There are 8 dwords in VUE header pre-Ironlake:
  90        * dword 0-3 is indices, point width, clip flags.
  91        * dword 4-7 is ndc position
  92        * dword 8-11 is the first vertex data.
  93        *
  94        * On Ironlake the VUE header is nominally 20 dwords, but the hardware
  95        * will accept the same header layout as Gen4 [and should be a bit faster]
  96        */
  97       assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
  98       assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC);
  99       assign_vue_slot(vue_map, VARYING_SLOT_POS);
 100       break;
 101    case 6:
 102    case 7:
 103       /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
 104        * dword 0-3 of the header is indices, point width, clip flags.
 105        * dword 4-7 is the 4D space position
 106        * dword 8-15 of the vertex header is the user clip distance if
 107        * enabled.
 108        * dword 8-11 or 16-19 is the first vertex element data we fill.
 109        */
 110       assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
 111       assign_vue_slot(vue_map, VARYING_SLOT_POS);
 112       if (userclip_active) {
 113          assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0);
 114          assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1);
 115       }
 116       /* front and back colors need to be consecutive so that we can use
 117        * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing
 118        * two-sided color.
 119        */
 120       if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL0))
 121          assign_vue_slot(vue_map, VARYING_SLOT_COL0);
 122       if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC0))
 123          assign_vue_slot(vue_map, VARYING_SLOT_BFC0);
 124       if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL1))
 125          assign_vue_slot(vue_map, VARYING_SLOT_COL1);
 126       if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC1))
 127          assign_vue_slot(vue_map, VARYING_SLOT_BFC1);
 128       break;
 129    default:
 130       assert (!"VUE map not known for this chip generation");
 131       break;
 132    }
 133
 134    /* The hardware doesn't care about the rest of the vertex outputs, so just
 135     * assign them contiguously.  Don't reassign outputs that already have a
 136     * slot.
 137     *
 138     * We generally don't need to assign a slot for VARYING_SLOT_CLIP_VERTEX,
 139     * since it's encoded as the clip distances by emit_clip_distances().
 140     * However, it may be output by transform feedback, and we'd rather not
 141     * recompute state when TF changes, so we just always include it.
 142     */
 143    for (int i = 0; i < VARYING_SLOT_MAX; ++i) {
 144       if ((slots_valid & BITFIELD64_BIT(i)) &&
 145           vue_map->varying_to_slot[i] == -1) {
 146          assign_vue_slot(vue_map, i);
 147       }
 148    }
 149 }
 150
 151
 152 /**
 153  * Decide which set of clip planes should be used when clipping via
 154  * gl_Position or gl_ClipVertex.
 155  */
 156 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
 157 {
 158    if (ctx->Shader.CurrentVertexProgram) {
 159       /* There is currently a GLSL vertex shader, so clip according to GLSL
 160        * rules, which means compare gl_ClipVertex (or gl_Position, if
 161        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
 162        * that were stored in EyeUserPlane at the time the clip planes were
 163        * specified.
 164        */
 165       return ctx->Transform.EyeUserPlane;
 166    } else {
 167       /* Either we are using fixed function or an ARB vertex program.  In
 168        * either case the clip planes are going to be compared against
 169        * gl_Position (which is in clip coordinates) so we have to clip using
 170        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
 171        * core.
 172        */
 173       return ctx->Transform._ClipUserPlane;
 174    }
 175 }
 176
 177
 178 bool
 179 brw_vec4_prog_data_compare(const struct brw_vec4_prog_data *a,
 180                            const struct brw_vec4_prog_data *b)
 181 {
 182    /* Compare all the struct up to the pointers. */
 183    if (memcmp(a, b, offsetof(struct brw_vec4_prog_data, param)))
 184       return false;
 185
 186    if (memcmp(a->param, b->param, a->nr_params * sizeof(void *)))
 187       return false;
 188
 189    if (memcmp(a->pull_param, b->pull_param, a->nr_pull_params * sizeof(void *)))
 190       return false;
 191
 192    return true;
 193 }
 194
 195
 196 bool
 197 brw_vs_prog_data_compare(const void *in_a, const void *in_b,
 198                          int aux_size, const void *in_key)
 199 {
 200    const struct brw_vs_prog_data *a = in_a;
 201    const struct brw_vs_prog_data *b = in_b;
 202
 203    /* Compare the base vec4 structure. */
 204    if (!brw_vec4_prog_data_compare(&a->base, &b->base))
 205       return false;
 206
 207    /* Compare the rest of the struct. */
 208    const unsigned offset = sizeof(struct brw_vec4_prog_data);
 209    if (memcmp(((char *) &a) + offset, ((char *) &b) + offset,
 210               sizeof(struct brw_vs_prog_data) - offset)) {
 211       return false;
 212    }
 213
 214    return true;
 215 }
 216
 217 static bool
 218 do_vs_prog(struct brw_context *brw,
 219            struct gl_shader_program *prog,
 220            struct brw_vertex_program *vp,
 221            struct brw_vs_prog_key *key)
 222 {
 223    struct intel_context *intel = &brw->intel;
 224    GLuint program_size;
 225    const GLuint *program;
 226    struct brw_vs_compile c;
 227    struct brw_vs_prog_data prog_data;
 228    void *mem_ctx;
 229    int i;
 230    struct gl_shader *vs = NULL;
 231
 232    if (prog)
 233       vs = prog->_LinkedShaders[MESA_SHADER_VERTEX];
 234
 235    memset(&c, 0, sizeof(c));
 236    memcpy(&c.key, key, sizeof(*key));
 237    memset(&prog_data, 0, sizeof(prog_data));
 238
 239    mem_ctx = ralloc_context(NULL);
 240
 241    c.vp = vp;
 242
 243    /* Allocate the references to the uniforms that will end up in the
 244     * prog_data associated with the compiled program, and which will be freed
 245     * by the state cache.
 246     */
 247    int param_count;
 248    if (vs) {
 249       /* We add padding around uniform values below vec4 size, with the worst
 250        * case being a float value that gets blown up to a vec4, so be
 251        * conservative here.
 252        */
 253       param_count = vs->num_uniform_components * 4;
 254
 255    } else {
 256       param_count = vp->program.Base.Parameters->NumParameters * 4;
 257    }
 258    /* We also upload clip plane data as uniforms */
 259    param_count += MAX_CLIP_PLANES * 4;
 260
 261    prog_data.base.param = rzalloc_array(NULL, const float *, param_count);
 262    prog_data.base.pull_param = rzalloc_array(NULL, const float *, param_count);
 263
 264    GLbitfield64 outputs_written = vp->program.Base.OutputsWritten;
 265    prog_data.inputs_read = vp->program.Base.InputsRead;
 266
 267    if (c.key.copy_edgeflag) {
 268       outputs_written |= BITFIELD64_BIT(VARYING_SLOT_EDGE);
 269       prog_data.inputs_read |= VERT_BIT_EDGEFLAG;
 270    }
 271
 272    if (intel->gen < 6) {
 273       /* Put dummy slots into the VUE for the SF to put the replaced
 274        * point sprite coords in.  We shouldn't need these dummy slots,
 275        * which take up precious URB space, but it would mean that the SF
 276        * doesn't get nice aligned pairs of input coords into output
 277        * coords, which would be a pain to handle.
 278        */
 279       for (i = 0; i < 8; i++) {
 280          if (c.key.point_coord_replace & (1 << i))
 281             outputs_written |= BITFIELD64_BIT(VARYING_SLOT_TEX0 + i);
 282       }
 283    }
 284
 285    brw_compute_vue_map(brw, &prog_data.base.vue_map, outputs_written,
 286                        c.key.base.userclip_active);
 287
 288    if (0) {
 289       _mesa_fprint_program_opt(stdout, &c.vp->program.Base, PROG_PRINT_DEBUG,
 290                                true);
 291    }
 292
 293    /* Emit GEN4 code.
 294     */
 295    program = brw_vs_emit(brw, prog, &c, &prog_data, mem_ctx, &program_size);
 296    if (program == NULL) {
 297       ralloc_free(mem_ctx);
 298       return false;
 299    }
 300
 301    if (prog_data.base.nr_pull_params)
 302       prog_data.base.num_surfaces = 1;
 303    if (c.vp->program.Base.SamplersUsed)
 304       prog_data.base.num_surfaces = SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT);
 305    if (prog &&
 306        prog->_LinkedShaders[MESA_SHADER_VERTEX]->NumUniformBlocks) {
 307       prog_data.base.num_surfaces =
 308          SURF_INDEX_VS_UBO(prog->_LinkedShaders[MESA_SHADER_VERTEX]->NumUniformBlocks);
 309    }
 310
 311    /* Scratch space is used for register spilling */
 312    if (c.base.last_scratch) {
 313       perf_debug("Vertex shader triggered register spilling.  "
 314                  "Try reducing the number of live vec4 values to "
 315                  "improve performance.\n");
 316
 317       prog_data.base.total_scratch
 318          = brw_get_scratch_size(c.base.last_scratch*REG_SIZE);
 319
 320       brw_get_scratch_bo(intel, &brw->vs.scratch_bo,
 321                          prog_data.base.total_scratch * brw->max_vs_threads);
 322    }
 323
 324    brw_upload_cache(&brw->cache, BRW_VS_PROG,
 325                     &c.key, sizeof(c.key),
 326                     program, program_size,
 327                     &prog_data, sizeof(prog_data),
 328                     &brw->vs.prog_offset, &brw->vs.prog_data);
 329    ralloc_free(mem_ctx);
 330
 331    return true;
 332 }
 333
 334 static bool
 335 key_debug(struct intel_context *intel, const char *name, int a, int b)
 336 {
 337    if (a != b) {
 338       perf_debug("  %s %d->%d\n", name, a, b);
 339       return true;
 340    }
 341    return false;
 342 }
 343
 344 void
 345 brw_vs_debug_recompile(struct brw_context *brw,
 346                        struct gl_shader_program *prog,
 347                        const struct brw_vs_prog_key *key)
 348 {
 349    struct intel_context *intel = &brw->intel;
 350    struct brw_cache_item *c = NULL;
 351    const struct brw_vs_prog_key *old_key = NULL;
 352    bool found = false;
 353
 354    perf_debug("Recompiling vertex shader for program %d\n", prog->Name);
 355
 356    for (unsigned int i = 0; i < brw->cache.size; i++) {
 357       for (c = brw->cache.items[i]; c; c = c->next) {
 358          if (c->cache_id == BRW_VS_PROG) {
 359             old_key = c->key;
 360
 361             if (old_key->base.program_string_id == key->base.program_string_id)
 362                break;
 363          }
 364       }
 365       if (c)
 366          break;
 367    }
 368
 369    if (!c) {
 370       perf_debug("  Didn't find previous compile in the shader cache for "
 371                  "debug\n");
 372       return;
 373    }
 374
 375    for (unsigned int i = 0; i < VERT_ATTRIB_MAX; i++) {
 376       found |= key_debug(intel, "Vertex attrib w/a flags",
 377                          old_key->gl_attrib_wa_flags[i],
 378                          key->gl_attrib_wa_flags[i]);
 379    }
 380
 381    found |= key_debug(intel, "user clip flags",
 382                       old_key->base.userclip_active, key->base.userclip_active);
 383
 384    found |= key_debug(intel, "user clipping planes as push constants",
 385                       old_key->base.nr_userclip_plane_consts,
 386                       key->base.nr_userclip_plane_consts);
 387
 388    found |= key_debug(intel, "clip distance enable",
 389                       old_key->base.uses_clip_distance, key->base.uses_clip_distance);
 390    found |= key_debug(intel, "clip plane enable bitfield",
 391                       old_key->base.userclip_planes_enabled_gen_4_5,
 392                       key->base.userclip_planes_enabled_gen_4_5);
 393    found |= key_debug(intel, "copy edgeflag",
 394                       old_key->copy_edgeflag, key->copy_edgeflag);
 395    found |= key_debug(intel, "PointCoord replace",
 396                       old_key->point_coord_replace, key->point_coord_replace);
 397    found |= key_debug(intel, "vertex color clamping",
 398                       old_key->base.clamp_vertex_color, key->base.clamp_vertex_color);
 399
 400    found |= brw_debug_recompile_sampler_key(intel, &old_key->base.tex,
 401                                             &key->base.tex);
 402
 403    if (!found) {
 404       perf_debug("  Something else\n");
 405    }
 406 }
 407
 408 static void brw_upload_vs_prog(struct brw_context *brw)
 409 {
 410    struct intel_context *intel = &brw->intel;
 411    struct gl_context *ctx = &intel->ctx;
 412    struct brw_vs_prog_key key;
 413    /* BRW_NEW_VERTEX_PROGRAM */
 414    struct brw_vertex_program *vp =
 415       (struct brw_vertex_program *)brw->vertex_program;
 416    struct gl_program *prog = (struct gl_program *) brw->vertex_program;
 417    int i;
 418
 419    memset(&key, 0, sizeof(key));
 420
 421    /* Just upload the program verbatim for now.  Always send it all
 422     * the inputs it asks for, whether they are varying or not.
 423     */
 424    key.base.program_string_id = vp->id;
 425    key.base.userclip_active = (ctx->Transform.ClipPlanesEnabled != 0);
 426    key.base.uses_clip_distance = vp->program.UsesClipDistance;
 427    if (key.base.userclip_active && !key.base.uses_clip_distance) {
 428       if (intel->gen < 6) {
 429          key.base.nr_userclip_plane_consts
 430             = _mesa_bitcount_64(ctx->Transform.ClipPlanesEnabled);
 431          key.base.userclip_planes_enabled_gen_4_5
 432             = ctx->Transform.ClipPlanesEnabled;
 433       } else {
 434          key.base.nr_userclip_plane_consts
 435             = _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1;
 436       }
 437    }
 438
 439    /* _NEW_POLYGON */
 440    if (intel->gen < 6) {
 441       key.copy_edgeflag = (ctx->Polygon.FrontMode != GL_FILL ||
 442                            ctx->Polygon.BackMode != GL_FILL);
 443    }
 444
 445    /* _NEW_LIGHT | _NEW_BUFFERS */
 446    key.base.clamp_vertex_color = ctx->Light._ClampVertexColor;
 447
 448    /* _NEW_POINT */
 449    if (intel->gen < 6 && ctx->Point.PointSprite) {
 450       for (i = 0; i < 8; i++) {
 451          if (ctx->Point.CoordReplace[i])
 452             key.point_coord_replace |= (1 << i);
 453       }
 454    }
 455
 456    /* _NEW_TEXTURE */
 457    brw_populate_sampler_prog_key_data(ctx, prog, &key.base.tex);
 458
 459    /* BRW_NEW_VERTICES */
 460    if (intel->gen < 8 && !intel->is_haswell) {
 461       /* Prior to Haswell, the hardware can't natively support GL_FIXED or
 462        * 2_10_10_10_REV vertex formats.  Set appropriate workaround flags.
 463        */
 464       for (i = 0; i < VERT_ATTRIB_MAX; i++) {
 465          if (!(vp->program.Base.InputsRead & BITFIELD64_BIT(i)))
 466             continue;
 467
 468          uint8_t wa_flags = 0;
 469
 470          switch (brw->vb.inputs[i].glarray->Type) {
 471
 472          case GL_FIXED:
 473             wa_flags = brw->vb.inputs[i].glarray->Size;
 474             break;
 475
 476          case GL_INT_2_10_10_10_REV:
 477             wa_flags |= BRW_ATTRIB_WA_SIGN;
 478             /* fallthough */
 479
 480          case GL_UNSIGNED_INT_2_10_10_10_REV:
 481             if (brw->vb.inputs[i].glarray->Format == GL_BGRA)
 482                wa_flags |= BRW_ATTRIB_WA_BGRA;
 483
 484             if (brw->vb.inputs[i].glarray->Normalized)
 485                wa_flags |= BRW_ATTRIB_WA_NORMALIZE;
 486             else if (!brw->vb.inputs[i].glarray->Integer)
 487                wa_flags |= BRW_ATTRIB_WA_SCALE;
 488
 489             break;
 490          }
 491
 492          key.gl_attrib_wa_flags[i] = wa_flags;
 493       }
 494    }
 495
 496    if (!brw_search_cache(&brw->cache, BRW_VS_PROG,
 497                          &key, sizeof(key),
 498                          &brw->vs.prog_offset, &brw->vs.prog_data)) {
 499       bool success = do_vs_prog(brw, ctx->Shader.CurrentVertexProgram,
 500                                 vp, &key);
 501
 502       assert(success);
 503    }
 504    if (memcmp(&brw->vs.prog_data->base.vue_map, &brw->vue_map_geom_out,
 505               sizeof(brw->vue_map_geom_out)) != 0) {
 506       brw->vue_map_geom_out = brw->vs.prog_data->base.vue_map;
 507       brw->state.dirty.brw |= BRW_NEW_VUE_MAP_GEOM_OUT;
 508    }
 509 }
 510
 511 /* See brw_vs.c:
 512  */
 513 const struct brw_tracked_state brw_vs_prog = {
 514    .dirty = {
 515       .mesa  = (_NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT | _NEW_LIGHT |
 516                 _NEW_TEXTURE |
 517                 _NEW_BUFFERS),
 518       .brw   = (BRW_NEW_VERTEX_PROGRAM |
 519                 BRW_NEW_VERTICES),
 520       .cache = 0
 521    },
 522    .emit = brw_upload_vs_prog
 523 };
 524
 525 bool
 526 brw_vs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
 527 {
 528    struct brw_context *brw = brw_context(ctx);
 529    struct brw_vs_prog_key key;
 530    uint32_t old_prog_offset = brw->vs.prog_offset;
 531    struct brw_vs_prog_data *old_prog_data = brw->vs.prog_data;
 532    bool success;
 533
 534    if (!prog->_LinkedShaders[MESA_SHADER_VERTEX])
 535       return true;
 536
 537    struct gl_vertex_program *vp = (struct gl_vertex_program *)
 538       prog->_LinkedShaders[MESA_SHADER_VERTEX]->Program;
 539    struct brw_vertex_program *bvp = brw_vertex_program(vp);
 540
 541    memset(&key, 0, sizeof(key));
 542
 543    key.base.program_string_id = bvp->id;
 544    key.base.clamp_vertex_color = ctx->API == API_OPENGL_COMPAT;
 545
 546    for (int i = 0; i < MAX_SAMPLERS; i++) {
 547       if (vp->Base.ShadowSamplers & (1 << i)) {
 548          /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
 549          key.base.tex.swizzles[i] =
 550             MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_ONE);
 551       } else {
 552          /* Color sampler: assume no swizzling. */
 553          key.base.tex.swizzles[i] = SWIZZLE_XYZW;
 554       }
 555    }
 556
 557    success = do_vs_prog(brw, prog, bvp, &key);
 558
 559    brw->vs.prog_offset = old_prog_offset;
 560    brw->vs.prog_data = old_prog_data;
 561
 562    return success;
 563 }
 564
 565
 566 void
 567 brw_vec4_prog_data_free(const struct brw_vec4_prog_data *prog_data)
 568 {
 569    ralloc_free((void *)prog_data->param);
 570    ralloc_free((void *)prog_data->pull_param);
 571 }
 572
 573
 574 void
 575 brw_vs_prog_data_free(const void *in_prog_data)
 576 {
 577    const struct brw_vs_prog_data *prog_data = in_prog_data;
 578
 579    brw_vec4_prog_data_free(&prog_data->base);
 580 }