src/mesa/drivers/dri/i965/brw_vs.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/compiler.h"
  34 #include "brw_context.h"
  35 #include "brw_vs.h"
  36 #include "brw_util.h"
  37 #include "brw_state.h"
  38 #include "program/prog_print.h"
  39 #include "program/prog_parameter.h"
  40
  41 #include "glsl/ralloc.h"
  42
  43 static inline void assign_vue_slot(struct brw_vue_map *vue_map,
  44                                    int varying)
  45 {
  46    /* Make sure this varying hasn't been assigned a slot already */
  47    assert (vue_map->varying_to_slot[varying] == -1);
  48
  49    vue_map->varying_to_slot[varying] = vue_map->num_slots;
  50    vue_map->slot_to_varying[vue_map->num_slots++] = varying;
  51 }
  52
  53 /**
  54  * Compute the VUE map for vertex shader program.
  55  *
  56  * Note that consumers of this map using cache keys must include
  57  * prog_data->userclip and prog_data->outputs_written in their key
  58  * (generated by CACHE_NEW_VS_PROG).
  59  */
  60 static void
  61 brw_compute_vue_map(struct brw_context *brw, struct brw_vs_compile *c,
  62                     GLbitfield64 slots_valid)
  63 {
  64    const struct intel_context *intel = &brw->intel;
  65    struct brw_vue_map *vue_map = &c->prog_data.vue_map;
  66    vue_map->slots_valid = slots_valid;
  67    int i;
  68
  69    vue_map->num_slots = 0;
  70    for (i = 0; i < BRW_VARYING_SLOT_COUNT; ++i) {
  71       vue_map->varying_to_slot[i] = -1;
  72       vue_map->slot_to_varying[i] = BRW_VARYING_SLOT_COUNT;
  73    }
  74
  75    /* VUE header: format depends on chip generation and whether clipping is
  76     * enabled.
  77     */
  78    switch (intel->gen) {
  79    case 4:
  80       /* There are 8 dwords in VUE header pre-Ironlake:
  81        * dword 0-3 is indices, point width, clip flags.
  82        * dword 4-7 is ndc position
  83        * dword 8-11 is the first vertex data.
  84        */
  85       assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
  86       assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC);
  87       assign_vue_slot(vue_map, VARYING_SLOT_POS);
  88       break;
  89    case 5:
  90       /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
  91        * dword 0-3 of the header is indices, point width, clip flags.
  92        * dword 4-7 is the ndc position
  93        * dword 8-11 of the vertex header is the 4D space position
  94        * dword 12-19 of the vertex header is the user clip distance.
  95        * dword 20-23 is a pad so that the vertex element data is aligned
  96        * dword 24-27 is the first vertex data we fill.
  97        *
  98        * Note: future pipeline stages expect 4D space position to be
  99        * contiguous with the other varyings, so we make dword 24-27 a
 100        * duplicate copy of the 4D space position.
 101        */
 102       assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
 103       assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC);
 104       assign_vue_slot(vue_map, BRW_VARYING_SLOT_POS_DUPLICATE);
 105       assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0);
 106       assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1);
 107       assign_vue_slot(vue_map, BRW_VARYING_SLOT_PAD);
 108       assign_vue_slot(vue_map, VARYING_SLOT_POS);
 109       break;
 110    case 6:
 111    case 7:
 112       /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
 113        * dword 0-3 of the header is indices, point width, clip flags.
 114        * dword 4-7 is the 4D space position
 115        * dword 8-15 of the vertex header is the user clip distance if
 116        * enabled.
 117        * dword 8-11 or 16-19 is the first vertex element data we fill.
 118        */
 119       assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
 120       assign_vue_slot(vue_map, VARYING_SLOT_POS);
 121       if (c->key.userclip_active) {
 122          assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0);
 123          assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1);
 124       }
 125       /* front and back colors need to be consecutive so that we can use
 126        * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing
 127        * two-sided color.
 128        */
 129       if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL0))
 130          assign_vue_slot(vue_map, VARYING_SLOT_COL0);
 131       if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC0))
 132          assign_vue_slot(vue_map, VARYING_SLOT_BFC0);
 133       if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL1))
 134          assign_vue_slot(vue_map, VARYING_SLOT_COL1);
 135       if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC1))
 136          assign_vue_slot(vue_map, VARYING_SLOT_BFC1);
 137       break;
 138    default:
 139       assert (!"VUE map not known for this chip generation");
 140       break;
 141    }
 142
 143    /* The hardware doesn't care about the rest of the vertex outputs, so just
 144     * assign them contiguously.  Don't reassign outputs that already have a
 145     * slot.
 146     *
 147     * Also, prior to Gen6, don't assign a slot for VARYING_SLOT_CLIP_VERTEX,
 148     * since it is unsupported.  In Gen6 and above, VARYING_SLOT_CLIP_VERTEX may
 149     * be needed for transform feedback; since we don't want to have to
 150     * recompute the VUE map (and everything that depends on it) when transform
 151     * feedback is enabled or disabled, just go ahead and assign a slot for it.
 152     */
 153    for (int i = 0; i < VARYING_SLOT_MAX; ++i) {
 154       if (intel->gen < 6 && i == VARYING_SLOT_CLIP_VERTEX)
 155          continue;
 156       if ((slots_valid & BITFIELD64_BIT(i)) &&
 157           vue_map->varying_to_slot[i] == -1) {
 158          assign_vue_slot(vue_map, i);
 159       }
 160    }
 161 }
 162
 163
 164 /**
 165  * Decide which set of clip planes should be used when clipping via
 166  * gl_Position or gl_ClipVertex.
 167  */
 168 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
 169 {
 170    if (ctx->Shader.CurrentVertexProgram) {
 171       /* There is currently a GLSL vertex shader, so clip according to GLSL
 172        * rules, which means compare gl_ClipVertex (or gl_Position, if
 173        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
 174        * that were stored in EyeUserPlane at the time the clip planes were
 175        * specified.
 176        */
 177       return ctx->Transform.EyeUserPlane;
 178    } else {
 179       /* Either we are using fixed function or an ARB vertex program.  In
 180        * either case the clip planes are going to be compared against
 181        * gl_Position (which is in clip coordinates) so we have to clip using
 182        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
 183        * core.
 184        */
 185       return ctx->Transform._ClipUserPlane;
 186    }
 187 }
 188
 189 bool
 190 brw_vs_prog_data_compare(const void *in_a, const void *in_b,
 191                          int aux_size, const void *in_key)
 192 {
 193    const struct brw_vs_prog_data *a = in_a;
 194    const struct brw_vs_prog_data *b = in_b;
 195
 196    /* Compare all the struct up to the pointers. */
 197    if (memcmp(a, b, offsetof(struct brw_vs_prog_data, param)))
 198       return false;
 199
 200    if (memcmp(a->param, b->param, a->nr_params * sizeof(void *)))
 201       return false;
 202
 203    if (memcmp(a->pull_param, b->pull_param, a->nr_pull_params * sizeof(void *)))
 204       return false;
 205
 206    return true;
 207 }
 208
 209 static bool
 210 do_vs_prog(struct brw_context *brw,
 211            struct gl_shader_program *prog,
 212            struct brw_vertex_program *vp,
 213            struct brw_vs_prog_key *key)
 214 {
 215    struct intel_context *intel = &brw->intel;
 216    GLuint program_size;
 217    const GLuint *program;
 218    struct brw_vs_compile c;
 219    void *mem_ctx;
 220    int i;
 221    struct gl_shader *vs = NULL;
 222
 223    if (prog)
 224       vs = prog->_LinkedShaders[MESA_SHADER_VERTEX];
 225
 226    memset(&c, 0, sizeof(c));
 227    memcpy(&c.key, key, sizeof(*key));
 228
 229    mem_ctx = ralloc_context(NULL);
 230
 231    c.vp = vp;
 232
 233    /* Allocate the references to the uniforms that will end up in the
 234     * prog_data associated with the compiled program, and which will be freed
 235     * by the state cache.
 236     */
 237    int param_count;
 238    if (vs) {
 239       /* We add padding around uniform values below vec4 size, with the worst
 240        * case being a float value that gets blown up to a vec4, so be
 241        * conservative here.
 242        */
 243       param_count = vs->num_uniform_components * 4;
 244
 245    } else {
 246       param_count = vp->program.Base.Parameters->NumParameters * 4;
 247    }
 248    /* We also upload clip plane data as uniforms */
 249    param_count += MAX_CLIP_PLANES * 4;
 250
 251    c.prog_data.param = rzalloc_array(NULL, const float *, param_count);
 252    c.prog_data.pull_param = rzalloc_array(NULL, const float *, param_count);
 253
 254    GLbitfield64 outputs_written = vp->program.Base.OutputsWritten;
 255    c.prog_data.inputs_read = vp->program.Base.InputsRead;
 256
 257    if (c.key.copy_edgeflag) {
 258       outputs_written |= BITFIELD64_BIT(VARYING_SLOT_EDGE);
 259       c.prog_data.inputs_read |= VERT_BIT_EDGEFLAG;
 260    }
 261
 262    if (intel->gen < 6) {
 263       /* Put dummy slots into the VUE for the SF to put the replaced
 264        * point sprite coords in.  We shouldn't need these dummy slots,
 265        * which take up precious URB space, but it would mean that the SF
 266        * doesn't get nice aligned pairs of input coords into output
 267        * coords, which would be a pain to handle.
 268        */
 269       for (i = 0; i < 8; i++) {
 270          if (c.key.point_coord_replace & (1 << i))
 271             outputs_written |= BITFIELD64_BIT(VARYING_SLOT_TEX0 + i);
 272       }
 273    }
 274
 275    brw_compute_vue_map(brw, &c, outputs_written);
 276
 277    if (0) {
 278       _mesa_fprint_program_opt(stdout, &c.vp->program.Base, PROG_PRINT_DEBUG,
 279                                true);
 280    }
 281
 282    /* Emit GEN4 code.
 283     */
 284    program = brw_vs_emit(brw, prog, &c, mem_ctx, &program_size);
 285    if (program == NULL) {
 286       ralloc_free(mem_ctx);
 287       return false;
 288    }
 289
 290    if (c.prog_data.nr_pull_params)
 291       c.prog_data.num_surfaces = 1;
 292    if (c.vp->program.Base.SamplersUsed)
 293       c.prog_data.num_surfaces = SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT);
 294    if (prog &&
 295        prog->_LinkedShaders[MESA_SHADER_VERTEX]->NumUniformBlocks) {
 296       c.prog_data.num_surfaces =
 297          SURF_INDEX_VS_UBO(prog->_LinkedShaders[MESA_SHADER_VERTEX]->NumUniformBlocks);
 298    }
 299
 300    /* Scratch space is used for register spilling */
 301    if (c.last_scratch) {
 302       perf_debug("Vertex shader triggered register spilling.  "
 303                  "Try reducing the number of live vec4 values to "
 304                  "improve performance.\n");
 305
 306       c.prog_data.total_scratch = brw_get_scratch_size(c.last_scratch*REG_SIZE);
 307
 308       brw_get_scratch_bo(intel, &brw->vs.scratch_bo,
 309                          c.prog_data.total_scratch * brw->max_vs_threads);
 310    }
 311
 312    brw_upload_cache(&brw->cache, BRW_VS_PROG,
 313                     &c.key, sizeof(c.key),
 314                     program, program_size,
 315                     &c.prog_data, sizeof(c.prog_data),
 316                     &brw->vs.prog_offset, &brw->vs.prog_data);
 317    ralloc_free(mem_ctx);
 318
 319    return true;
 320 }
 321
 322 static bool
 323 key_debug(struct intel_context *intel, const char *name, int a, int b)
 324 {
 325    if (a != b) {
 326       perf_debug("  %s %d->%d\n", name, a, b);
 327       return true;
 328    }
 329    return false;
 330 }
 331
 332 void
 333 brw_vs_debug_recompile(struct brw_context *brw,
 334                        struct gl_shader_program *prog,
 335                        const struct brw_vs_prog_key *key)
 336 {
 337    struct intel_context *intel = &brw->intel;
 338    struct brw_cache_item *c = NULL;
 339    const struct brw_vs_prog_key *old_key = NULL;
 340    bool found = false;
 341
 342    perf_debug("Recompiling vertex shader for program %d\n", prog->Name);
 343
 344    for (unsigned int i = 0; i < brw->cache.size; i++) {
 345       for (c = brw->cache.items[i]; c; c = c->next) {
 346          if (c->cache_id == BRW_VS_PROG) {
 347             old_key = c->key;
 348
 349             if (old_key->program_string_id == key->program_string_id)
 350                break;
 351          }
 352       }
 353       if (c)
 354          break;
 355    }
 356
 357    if (!c) {
 358       perf_debug("  Didn't find previous compile in the shader cache for "
 359                  "debug\n");
 360       return;
 361    }
 362
 363    for (unsigned int i = 0; i < VERT_ATTRIB_MAX; i++) {
 364       found |= key_debug(intel, "Vertex attrib w/a flags",
 365                          old_key->gl_attrib_wa_flags[i],
 366                          key->gl_attrib_wa_flags[i]);
 367    }
 368
 369    found |= key_debug(intel, "user clip flags",
 370                       old_key->userclip_active, key->userclip_active);
 371
 372    found |= key_debug(intel, "user clipping planes as push constants",
 373                       old_key->nr_userclip_plane_consts,
 374                       key->nr_userclip_plane_consts);
 375
 376    found |= key_debug(intel, "clip distance enable",
 377                       old_key->uses_clip_distance, key->uses_clip_distance);
 378    found |= key_debug(intel, "clip plane enable bitfield",
 379                       old_key->userclip_planes_enabled_gen_4_5,
 380                       key->userclip_planes_enabled_gen_4_5);
 381    found |= key_debug(intel, "copy edgeflag",
 382                       old_key->copy_edgeflag, key->copy_edgeflag);
 383    found |= key_debug(intel, "PointCoord replace",
 384                       old_key->point_coord_replace, key->point_coord_replace);
 385    found |= key_debug(intel, "vertex color clamping",
 386                       old_key->clamp_vertex_color, key->clamp_vertex_color);
 387
 388    found |= brw_debug_recompile_sampler_key(intel, &old_key->tex, &key->tex);
 389
 390    if (!found) {
 391       perf_debug("  Something else\n");
 392    }
 393 }
 394
 395 static void brw_upload_vs_prog(struct brw_context *brw)
 396 {
 397    struct intel_context *intel = &brw->intel;
 398    struct gl_context *ctx = &intel->ctx;
 399    struct brw_vs_prog_key key;
 400    /* BRW_NEW_VERTEX_PROGRAM */
 401    struct brw_vertex_program *vp =
 402       (struct brw_vertex_program *)brw->vertex_program;
 403    struct gl_program *prog = (struct gl_program *) brw->vertex_program;
 404    int i;
 405
 406    memset(&key, 0, sizeof(key));
 407
 408    /* Just upload the program verbatim for now.  Always send it all
 409     * the inputs it asks for, whether they are varying or not.
 410     */
 411    key.program_string_id = vp->id;
 412    key.userclip_active = (ctx->Transform.ClipPlanesEnabled != 0);
 413    key.uses_clip_distance = vp->program.UsesClipDistance;
 414    if (key.userclip_active && !key.uses_clip_distance) {
 415       if (intel->gen < 6) {
 416          key.nr_userclip_plane_consts
 417             = _mesa_bitcount_64(ctx->Transform.ClipPlanesEnabled);
 418          key.userclip_planes_enabled_gen_4_5
 419             = ctx->Transform.ClipPlanesEnabled;
 420       } else {
 421          key.nr_userclip_plane_consts
 422             = _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1;
 423       }
 424    }
 425
 426    /* _NEW_POLYGON */
 427    if (intel->gen < 6) {
 428       key.copy_edgeflag = (ctx->Polygon.FrontMode != GL_FILL ||
 429                            ctx->Polygon.BackMode != GL_FILL);
 430    }
 431
 432    /* _NEW_LIGHT | _NEW_BUFFERS */
 433    key.clamp_vertex_color = ctx->Light._ClampVertexColor;
 434
 435    /* _NEW_POINT */
 436    if (intel->gen < 6 && ctx->Point.PointSprite) {
 437       for (i = 0; i < 8; i++) {
 438          if (ctx->Point.CoordReplace[i])
 439             key.point_coord_replace |= (1 << i);
 440       }
 441    }
 442
 443    /* _NEW_TEXTURE */
 444    brw_populate_sampler_prog_key_data(ctx, prog, &key.tex);
 445
 446    /* BRW_NEW_VERTICES */
 447    if (intel->gen < 8 && !intel->is_haswell) {
 448       /* Prior to Haswell, the hardware can't natively support GL_FIXED or
 449        * 2_10_10_10_REV vertex formats.  Set appropriate workaround flags.
 450        */
 451       for (i = 0; i < VERT_ATTRIB_MAX; i++) {
 452          if (!(vp->program.Base.InputsRead & BITFIELD64_BIT(i)))
 453             continue;
 454
 455          uint8_t wa_flags = 0;
 456
 457          switch (brw->vb.inputs[i].glarray->Type) {
 458
 459          case GL_FIXED:
 460             wa_flags = brw->vb.inputs[i].glarray->Size;
 461             break;
 462
 463          case GL_INT_2_10_10_10_REV:
 464             wa_flags |= BRW_ATTRIB_WA_SIGN;
 465             /* fallthough */
 466
 467          case GL_UNSIGNED_INT_2_10_10_10_REV:
 468             if (brw->vb.inputs[i].glarray->Format == GL_BGRA)
 469                wa_flags |= BRW_ATTRIB_WA_BGRA;
 470
 471             if (brw->vb.inputs[i].glarray->Normalized)
 472                wa_flags |= BRW_ATTRIB_WA_NORMALIZE;
 473             else if (!brw->vb.inputs[i].glarray->Integer)
 474                wa_flags |= BRW_ATTRIB_WA_SCALE;
 475
 476             break;
 477          }
 478
 479          key.gl_attrib_wa_flags[i] = wa_flags;
 480       }
 481    }
 482
 483    if (!brw_search_cache(&brw->cache, BRW_VS_PROG,
 484                          &key, sizeof(key),
 485                          &brw->vs.prog_offset, &brw->vs.prog_data)) {
 486       bool success = do_vs_prog(brw, ctx->Shader.CurrentVertexProgram,
 487                                 vp, &key);
 488
 489       assert(success);
 490    }
 491    if (memcmp(&brw->vs.prog_data->vue_map, &brw->vue_map_geom_out,
 492               sizeof(brw->vue_map_geom_out)) != 0) {
 493       brw->vue_map_geom_out = brw->vs.prog_data->vue_map;
 494       brw->state.dirty.brw |= BRW_NEW_VUE_MAP_GEOM_OUT;
 495    }
 496 }
 497
 498 /* See brw_vs.c:
 499  */
 500 const struct brw_tracked_state brw_vs_prog = {
 501    .dirty = {
 502       .mesa  = (_NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT | _NEW_LIGHT |
 503                 _NEW_TEXTURE |
 504                 _NEW_BUFFERS),
 505       .brw   = (BRW_NEW_VERTEX_PROGRAM |
 506                 BRW_NEW_VERTICES),
 507       .cache = 0
 508    },
 509    .emit = brw_upload_vs_prog
 510 };
 511
 512 bool
 513 brw_vs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
 514 {
 515    struct brw_context *brw = brw_context(ctx);
 516    struct brw_vs_prog_key key;
 517    uint32_t old_prog_offset = brw->vs.prog_offset;
 518    struct brw_vs_prog_data *old_prog_data = brw->vs.prog_data;
 519    bool success;
 520
 521    if (!prog->_LinkedShaders[MESA_SHADER_VERTEX])
 522       return true;
 523
 524    struct gl_vertex_program *vp = (struct gl_vertex_program *)
 525       prog->_LinkedShaders[MESA_SHADER_VERTEX]->Program;
 526    struct brw_vertex_program *bvp = brw_vertex_program(vp);
 527
 528    memset(&key, 0, sizeof(key));
 529
 530    key.program_string_id = bvp->id;
 531    key.clamp_vertex_color = true;
 532
 533    for (int i = 0; i < MAX_SAMPLERS; i++) {
 534       if (vp->Base.ShadowSamplers & (1 << i)) {
 535          /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
 536          key.tex.swizzles[i] =
 537             MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_ONE);
 538       } else {
 539          /* Color sampler: assume no swizzling. */
 540          key.tex.swizzles[i] = SWIZZLE_XYZW;
 541       }
 542    }
 543
 544    success = do_vs_prog(brw, prog, bvp, &key);
 545
 546    brw->vs.prog_offset = old_prog_offset;
 547    brw->vs.prog_data = old_prog_data;
 548
 549    return success;
 550 }
 551
 552 void
 553 brw_vs_prog_data_free(const void *in_prog_data)
 554 {
 555    const struct brw_vs_prog_data *prog_data = in_prog_data;
 556
 557    ralloc_free((void *)prog_data->param);
 558    ralloc_free((void *)prog_data->pull_param);
 559 }