i965: Add functions for comparing two brw_wm/vs_prog_data structs.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vs.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/compiler.h"
34 #include "brw_context.h"
35 #include "brw_vs.h"
36 #include "brw_util.h"
37 #include "brw_state.h"
38 #include "program/prog_print.h"
39 #include "program/prog_parameter.h"
40
41 #include "glsl/ralloc.h"
42
43 static inline void assign_vue_slot(struct brw_vue_map *vue_map,
44 int vert_result)
45 {
46 /* Make sure this vert_result hasn't been assigned a slot already */
47 assert (vue_map->vert_result_to_slot[vert_result] == -1);
48
49 vue_map->vert_result_to_slot[vert_result] = vue_map->num_slots;
50 vue_map->slot_to_vert_result[vue_map->num_slots++] = vert_result;
51 }
52
53 /**
54 * Compute the VUE map for vertex shader program.
55 *
56 * Note that consumers of this map using cache keys must include
57 * prog_data->userclip and prog_data->outputs_written in their key
58 * (generated by CACHE_NEW_VS_PROG).
59 */
60 static void
61 brw_compute_vue_map(struct brw_vs_compile *c)
62 {
63 struct brw_context *brw = c->func.brw;
64 const struct intel_context *intel = &brw->intel;
65 struct brw_vue_map *vue_map = &c->prog_data.vue_map;
66 GLbitfield64 outputs_written = c->prog_data.outputs_written;
67 int i;
68
69 vue_map->num_slots = 0;
70 for (i = 0; i < BRW_VERT_RESULT_MAX; ++i) {
71 vue_map->vert_result_to_slot[i] = -1;
72 vue_map->slot_to_vert_result[i] = BRW_VERT_RESULT_MAX;
73 }
74
75 /* VUE header: format depends on chip generation and whether clipping is
76 * enabled.
77 */
78 switch (intel->gen) {
79 case 4:
80 /* There are 8 dwords in VUE header pre-Ironlake:
81 * dword 0-3 is indices, point width, clip flags.
82 * dword 4-7 is ndc position
83 * dword 8-11 is the first vertex data.
84 */
85 assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
86 assign_vue_slot(vue_map, BRW_VERT_RESULT_NDC);
87 assign_vue_slot(vue_map, VERT_RESULT_HPOS);
88 break;
89 case 5:
90 /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
91 * dword 0-3 of the header is indices, point width, clip flags.
92 * dword 4-7 is the ndc position
93 * dword 8-11 of the vertex header is the 4D space position
94 * dword 12-19 of the vertex header is the user clip distance.
95 * dword 20-23 is a pad so that the vertex element data is aligned
96 * dword 24-27 is the first vertex data we fill.
97 *
98 * Note: future pipeline stages expect 4D space position to be
99 * contiguous with the other vert_results, so we make dword 24-27 a
100 * duplicate copy of the 4D space position.
101 */
102 assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
103 assign_vue_slot(vue_map, BRW_VERT_RESULT_NDC);
104 assign_vue_slot(vue_map, BRW_VERT_RESULT_HPOS_DUPLICATE);
105 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST0);
106 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST1);
107 assign_vue_slot(vue_map, BRW_VERT_RESULT_PAD);
108 assign_vue_slot(vue_map, VERT_RESULT_HPOS);
109 break;
110 case 6:
111 case 7:
112 /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
113 * dword 0-3 of the header is indices, point width, clip flags.
114 * dword 4-7 is the 4D space position
115 * dword 8-15 of the vertex header is the user clip distance if
116 * enabled.
117 * dword 8-11 or 16-19 is the first vertex element data we fill.
118 */
119 assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
120 assign_vue_slot(vue_map, VERT_RESULT_HPOS);
121 if (c->key.userclip_active) {
122 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST0);
123 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST1);
124 }
125 /* front and back colors need to be consecutive so that we can use
126 * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing
127 * two-sided color.
128 */
129 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_COL0))
130 assign_vue_slot(vue_map, VERT_RESULT_COL0);
131 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC0))
132 assign_vue_slot(vue_map, VERT_RESULT_BFC0);
133 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_COL1))
134 assign_vue_slot(vue_map, VERT_RESULT_COL1);
135 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC1))
136 assign_vue_slot(vue_map, VERT_RESULT_BFC1);
137 break;
138 default:
139 assert (!"VUE map not known for this chip generation");
140 break;
141 }
142
143 /* The hardware doesn't care about the rest of the vertex outputs, so just
144 * assign them contiguously. Don't reassign outputs that already have a
145 * slot.
146 *
147 * Also, prior to Gen6, don't assign a slot for VERT_RESULT_CLIP_VERTEX,
148 * since it is unsupported. In Gen6 and above, VERT_RESULT_CLIP_VERTEX may
149 * be needed for transform feedback; since we don't want to have to
150 * recompute the VUE map (and everything that depends on it) when transform
151 * feedback is enabled or disabled, just go ahead and assign a slot for it.
152 */
153 for (int i = 0; i < VERT_RESULT_MAX; ++i) {
154 if (intel->gen < 6 && i == VERT_RESULT_CLIP_VERTEX)
155 continue;
156 if ((outputs_written & BITFIELD64_BIT(i)) &&
157 vue_map->vert_result_to_slot[i] == -1) {
158 assign_vue_slot(vue_map, i);
159 }
160 }
161 }
162
163
164 /**
165 * Decide which set of clip planes should be used when clipping via
166 * gl_Position or gl_ClipVertex.
167 */
168 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
169 {
170 if (ctx->Shader.CurrentVertexProgram) {
171 /* There is currently a GLSL vertex shader, so clip according to GLSL
172 * rules, which means compare gl_ClipVertex (or gl_Position, if
173 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
174 * that were stored in EyeUserPlane at the time the clip planes were
175 * specified.
176 */
177 return ctx->Transform.EyeUserPlane;
178 } else {
179 /* Either we are using fixed function or an ARB vertex program. In
180 * either case the clip planes are going to be compared against
181 * gl_Position (which is in clip coordinates) so we have to clip using
182 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
183 * core.
184 */
185 return ctx->Transform._ClipUserPlane;
186 }
187 }
188
189 bool
190 brw_vs_prog_data_compare(const void *in_a, const void *in_b,
191 int aux_size, const void *in_key)
192 {
193 const struct brw_vs_prog_data *a = in_a;
194 const struct brw_vs_prog_data *b = in_b;
195
196 /* Compare all the struct up to the pointers. */
197 if (memcmp(a, b, offsetof(struct brw_vs_prog_data, param)))
198 return false;
199
200 if (memcmp(a->param, b->param, a->nr_params * sizeof(void *)))
201 return false;
202
203 if (memcmp(a->pull_param, b->pull_param, a->nr_pull_params * sizeof(void *)))
204 return false;
205
206 return true;
207 }
208
209 static bool
210 do_vs_prog(struct brw_context *brw,
211 struct gl_shader_program *prog,
212 struct brw_vertex_program *vp,
213 struct brw_vs_prog_key *key)
214 {
215 struct gl_context *ctx = &brw->intel.ctx;
216 struct intel_context *intel = &brw->intel;
217 GLuint program_size;
218 const GLuint *program;
219 struct brw_vs_compile c;
220 void *mem_ctx;
221 int aux_size;
222 int i;
223
224 memset(&c, 0, sizeof(c));
225 memcpy(&c.key, key, sizeof(*key));
226
227 mem_ctx = ralloc_context(NULL);
228
229 brw_init_compile(brw, &c.func, mem_ctx);
230 c.vp = vp;
231
232 c.prog_data.outputs_written = vp->program.Base.OutputsWritten;
233 c.prog_data.inputs_read = vp->program.Base.InputsRead;
234
235 if (c.key.copy_edgeflag) {
236 c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_EDGE);
237 c.prog_data.inputs_read |= VERT_BIT_EDGEFLAG;
238 }
239
240 /* Put dummy slots into the VUE for the SF to put the replaced
241 * point sprite coords in. We shouldn't need these dummy slots,
242 * which take up precious URB space, but it would mean that the SF
243 * doesn't get nice aligned pairs of input coords into output
244 * coords, which would be a pain to handle.
245 */
246 for (i = 0; i < 8; i++) {
247 if (c.key.point_coord_replace & (1 << i))
248 c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_TEX0 + i);
249 }
250
251 brw_compute_vue_map(&c);
252
253 if (0) {
254 _mesa_fprint_program_opt(stdout, &c.vp->program.Base, PROG_PRINT_DEBUG,
255 true);
256 }
257
258 /* Emit GEN4 code.
259 */
260 if (prog) {
261 if (!brw_vs_emit(prog, &c)) {
262 ralloc_free(mem_ctx);
263 return false;
264 }
265 } else {
266 brw_old_vs_emit(&c);
267 }
268
269 if (c.prog_data.nr_pull_params)
270 c.prog_data.num_surfaces = 1;
271 if (c.vp->program.Base.SamplersUsed)
272 c.prog_data.num_surfaces = SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT);
273 if (prog &&
274 prog->_LinkedShaders[MESA_SHADER_VERTEX]->NumUniformBlocks) {
275 c.prog_data.num_surfaces =
276 SURF_INDEX_VS_UBO(prog->_LinkedShaders[MESA_SHADER_VERTEX]->NumUniformBlocks);
277 }
278
279 /* Scratch space is used for register spilling */
280 if (c.last_scratch) {
281 perf_debug("Vertex shader triggered register spilling. "
282 "Try reducing the number of live vec4 values to "
283 "improve performance.\n");
284
285 c.prog_data.total_scratch = brw_get_scratch_size(c.last_scratch);
286
287 brw_get_scratch_bo(intel, &brw->vs.scratch_bo,
288 c.prog_data.total_scratch * brw->max_vs_threads);
289 }
290
291 /* get the program
292 */
293 program = brw_get_program(&c.func, &program_size);
294
295 /* We upload from &c.prog_data including the constant_map assuming
296 * they're packed together. It would be nice to have a
297 * compile-time assert macro here.
298 */
299 assert(c.constant_map == (int8_t *)&c.prog_data +
300 sizeof(c.prog_data));
301 assert(ctx->Const.VertexProgram.MaxNativeParameters ==
302 ARRAY_SIZE(c.constant_map));
303 (void) ctx;
304
305 aux_size = sizeof(c.prog_data);
306 /* constant_map */
307 aux_size += c.vp->program.Base.Parameters->NumParameters;
308
309 brw_upload_cache(&brw->cache, BRW_VS_PROG,
310 &c.key, sizeof(c.key),
311 program, program_size,
312 &c.prog_data, aux_size,
313 &brw->vs.prog_offset, &brw->vs.prog_data);
314 ralloc_free(mem_ctx);
315
316 return true;
317 }
318
319 static bool
320 key_debug(const char *name, int a, int b)
321 {
322 if (a != b) {
323 perf_debug(" %s %d->%d\n", name, a, b);
324 return true;
325 }
326 return false;
327 }
328
329 void
330 brw_vs_debug_recompile(struct brw_context *brw,
331 struct gl_shader_program *prog,
332 const struct brw_vs_prog_key *key)
333 {
334 struct brw_cache_item *c = NULL;
335 const struct brw_vs_prog_key *old_key = NULL;
336 bool found = false;
337
338 perf_debug("Recompiling vertex shader for program %d\n", prog->Name);
339
340 for (unsigned int i = 0; i < brw->cache.size; i++) {
341 for (c = brw->cache.items[i]; c; c = c->next) {
342 if (c->cache_id == BRW_VS_PROG) {
343 old_key = c->key;
344
345 if (old_key->program_string_id == key->program_string_id)
346 break;
347 }
348 }
349 if (c)
350 break;
351 }
352
353 if (!c) {
354 perf_debug(" Didn't find previous compile in the shader cache for "
355 "debug\n");
356 return;
357 }
358
359 for (unsigned int i = 0; i < VERT_ATTRIB_MAX; i++) {
360 found |= key_debug("GL_FIXED rescaling",
361 old_key->gl_fixed_input_size[i],
362 key->gl_fixed_input_size[i]);
363 }
364
365 found |= key_debug("user clip flags",
366 old_key->userclip_active, key->userclip_active);
367
368 found |= key_debug("user clipping planes as push constants",
369 old_key->nr_userclip_plane_consts,
370 key->nr_userclip_plane_consts);
371
372 found |= key_debug("clip distance enable",
373 old_key->uses_clip_distance, key->uses_clip_distance);
374 found |= key_debug("clip plane enable bitfield",
375 old_key->userclip_planes_enabled_gen_4_5,
376 key->userclip_planes_enabled_gen_4_5);
377 found |= key_debug("copy edgeflag",
378 old_key->copy_edgeflag, key->copy_edgeflag);
379 found |= key_debug("PointCoord replace",
380 old_key->point_coord_replace, key->point_coord_replace);
381 found |= key_debug("vertex color clamping",
382 old_key->clamp_vertex_color, key->clamp_vertex_color);
383
384 found |= brw_debug_recompile_sampler_key(&old_key->tex, &key->tex);
385
386 if (!found) {
387 perf_debug(" Something else\n");
388 }
389 }
390
391 static void brw_upload_vs_prog(struct brw_context *brw)
392 {
393 struct intel_context *intel = &brw->intel;
394 struct gl_context *ctx = &intel->ctx;
395 struct brw_vs_prog_key key;
396 /* BRW_NEW_VERTEX_PROGRAM */
397 struct brw_vertex_program *vp =
398 (struct brw_vertex_program *)brw->vertex_program;
399 struct gl_program *prog = (struct gl_program *) brw->vertex_program;
400 int i;
401
402 memset(&key, 0, sizeof(key));
403
404 /* Just upload the program verbatim for now. Always send it all
405 * the inputs it asks for, whether they are varying or not.
406 */
407 key.program_string_id = vp->id;
408 key.userclip_active = (ctx->Transform.ClipPlanesEnabled != 0);
409 key.uses_clip_distance = vp->program.UsesClipDistance;
410 if (key.userclip_active && !key.uses_clip_distance) {
411 if (intel->gen < 6) {
412 key.nr_userclip_plane_consts
413 = _mesa_bitcount_64(ctx->Transform.ClipPlanesEnabled);
414 key.userclip_planes_enabled_gen_4_5
415 = ctx->Transform.ClipPlanesEnabled;
416 } else {
417 key.nr_userclip_plane_consts
418 = _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1;
419 }
420 }
421
422 /* _NEW_POLYGON */
423 if (intel->gen < 6) {
424 key.copy_edgeflag = (ctx->Polygon.FrontMode != GL_FILL ||
425 ctx->Polygon.BackMode != GL_FILL);
426 }
427
428 /* _NEW_LIGHT | _NEW_BUFFERS */
429 key.clamp_vertex_color = ctx->Light._ClampVertexColor;
430
431 /* _NEW_POINT */
432 if (ctx->Point.PointSprite) {
433 for (i = 0; i < 8; i++) {
434 if (ctx->Point.CoordReplace[i])
435 key.point_coord_replace |= (1 << i);
436 }
437 }
438
439 /* _NEW_TEXTURE */
440 brw_populate_sampler_prog_key_data(ctx, prog, &key.tex);
441
442 /* BRW_NEW_VERTICES */
443 for (i = 0; i < VERT_ATTRIB_MAX; i++) {
444 if (vp->program.Base.InputsRead & BITFIELD64_BIT(i) &&
445 brw->vb.inputs[i].glarray->Type == GL_FIXED) {
446 key.gl_fixed_input_size[i] = brw->vb.inputs[i].glarray->Size;
447 }
448 }
449
450 if (!brw_search_cache(&brw->cache, BRW_VS_PROG,
451 &key, sizeof(key),
452 &brw->vs.prog_offset, &brw->vs.prog_data)) {
453 bool success = do_vs_prog(brw, ctx->Shader.CurrentVertexProgram,
454 vp, &key);
455
456 assert(success);
457 }
458 brw->vs.constant_map = ((int8_t *)brw->vs.prog_data +
459 sizeof(*brw->vs.prog_data));
460 }
461
462 /* See brw_vs.c:
463 */
464 const struct brw_tracked_state brw_vs_prog = {
465 .dirty = {
466 .mesa = (_NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT | _NEW_LIGHT |
467 _NEW_TEXTURE |
468 _NEW_BUFFERS),
469 .brw = (BRW_NEW_VERTEX_PROGRAM |
470 BRW_NEW_VERTICES),
471 .cache = 0
472 },
473 .emit = brw_upload_vs_prog
474 };
475
476 bool
477 brw_vs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
478 {
479 struct brw_context *brw = brw_context(ctx);
480 struct brw_vs_prog_key key;
481 uint32_t old_prog_offset = brw->vs.prog_offset;
482 struct brw_vs_prog_data *old_prog_data = brw->vs.prog_data;
483 bool success;
484
485 if (!prog->_LinkedShaders[MESA_SHADER_VERTEX])
486 return true;
487
488 struct gl_vertex_program *vp = (struct gl_vertex_program *)
489 prog->_LinkedShaders[MESA_SHADER_VERTEX]->Program;
490 struct brw_vertex_program *bvp = brw_vertex_program(vp);
491
492 memset(&key, 0, sizeof(key));
493
494 key.program_string_id = bvp->id;
495 key.clamp_vertex_color = true;
496
497 for (int i = 0; i < MAX_SAMPLERS; i++) {
498 if (vp->Base.ShadowSamplers & (1 << i)) {
499 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
500 key.tex.swizzles[i] =
501 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_ONE);
502 } else {
503 /* Color sampler: assume no swizzling. */
504 key.tex.swizzles[i] = SWIZZLE_XYZW;
505 }
506 }
507
508 success = do_vs_prog(brw, prog, bvp, &key);
509
510 brw->vs.prog_offset = old_prog_offset;
511 brw->vs.prog_data = old_prog_data;
512
513 return success;
514 }