i965/vs: Add VS program key dumping to INTEL_DEBUG=perf.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vs.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/compiler.h"
34 #include "brw_context.h"
35 #include "brw_vs.h"
36 #include "brw_util.h"
37 #include "brw_state.h"
38 #include "program/prog_print.h"
39 #include "program/prog_parameter.h"
40
41 #include "glsl/ralloc.h"
42
43 static inline void assign_vue_slot(struct brw_vue_map *vue_map,
44 int vert_result)
45 {
46 /* Make sure this vert_result hasn't been assigned a slot already */
47 assert (vue_map->vert_result_to_slot[vert_result] == -1);
48
49 vue_map->vert_result_to_slot[vert_result] = vue_map->num_slots;
50 vue_map->slot_to_vert_result[vue_map->num_slots++] = vert_result;
51 }
52
53 /**
54 * Compute the VUE map for vertex shader program.
55 *
56 * Note that consumers of this map using cache keys must include
57 * prog_data->userclip and prog_data->outputs_written in their key
58 * (generated by CACHE_NEW_VS_PROG).
59 */
60 static void
61 brw_compute_vue_map(struct brw_vs_compile *c)
62 {
63 struct brw_context *brw = c->func.brw;
64 const struct intel_context *intel = &brw->intel;
65 struct brw_vue_map *vue_map = &c->prog_data.vue_map;
66 GLbitfield64 outputs_written = c->prog_data.outputs_written;
67 int i;
68
69 vue_map->num_slots = 0;
70 for (i = 0; i < BRW_VERT_RESULT_MAX; ++i) {
71 vue_map->vert_result_to_slot[i] = -1;
72 vue_map->slot_to_vert_result[i] = BRW_VERT_RESULT_MAX;
73 }
74
75 /* VUE header: format depends on chip generation and whether clipping is
76 * enabled.
77 */
78 switch (intel->gen) {
79 case 4:
80 /* There are 8 dwords in VUE header pre-Ironlake:
81 * dword 0-3 is indices, point width, clip flags.
82 * dword 4-7 is ndc position
83 * dword 8-11 is the first vertex data.
84 */
85 assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
86 assign_vue_slot(vue_map, BRW_VERT_RESULT_NDC);
87 assign_vue_slot(vue_map, VERT_RESULT_HPOS);
88 break;
89 case 5:
90 /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
91 * dword 0-3 of the header is indices, point width, clip flags.
92 * dword 4-7 is the ndc position
93 * dword 8-11 of the vertex header is the 4D space position
94 * dword 12-19 of the vertex header is the user clip distance.
95 * dword 20-23 is a pad so that the vertex element data is aligned
96 * dword 24-27 is the first vertex data we fill.
97 *
98 * Note: future pipeline stages expect 4D space position to be
99 * contiguous with the other vert_results, so we make dword 24-27 a
100 * duplicate copy of the 4D space position.
101 */
102 assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
103 assign_vue_slot(vue_map, BRW_VERT_RESULT_NDC);
104 assign_vue_slot(vue_map, BRW_VERT_RESULT_HPOS_DUPLICATE);
105 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST0);
106 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST1);
107 assign_vue_slot(vue_map, BRW_VERT_RESULT_PAD);
108 assign_vue_slot(vue_map, VERT_RESULT_HPOS);
109 break;
110 case 6:
111 case 7:
112 /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
113 * dword 0-3 of the header is indices, point width, clip flags.
114 * dword 4-7 is the 4D space position
115 * dword 8-15 of the vertex header is the user clip distance if
116 * enabled.
117 * dword 8-11 or 16-19 is the first vertex element data we fill.
118 */
119 assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
120 assign_vue_slot(vue_map, VERT_RESULT_HPOS);
121 if (c->key.userclip_active) {
122 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST0);
123 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST1);
124 }
125 /* front and back colors need to be consecutive so that we can use
126 * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing
127 * two-sided color.
128 */
129 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_COL0))
130 assign_vue_slot(vue_map, VERT_RESULT_COL0);
131 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC0))
132 assign_vue_slot(vue_map, VERT_RESULT_BFC0);
133 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_COL1))
134 assign_vue_slot(vue_map, VERT_RESULT_COL1);
135 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC1))
136 assign_vue_slot(vue_map, VERT_RESULT_BFC1);
137 break;
138 default:
139 assert (!"VUE map not known for this chip generation");
140 break;
141 }
142
143 /* The hardware doesn't care about the rest of the vertex outputs, so just
144 * assign them contiguously. Don't reassign outputs that already have a
145 * slot.
146 *
147 * Also, prior to Gen6, don't assign a slot for VERT_RESULT_CLIP_VERTEX,
148 * since it is unsupported. In Gen6 and above, VERT_RESULT_CLIP_VERTEX may
149 * be needed for transform feedback; since we don't want to have to
150 * recompute the VUE map (and everything that depends on it) when transform
151 * feedback is enabled or disabled, just go ahead and assign a slot for it.
152 */
153 for (int i = 0; i < VERT_RESULT_MAX; ++i) {
154 if (intel->gen < 6 && i == VERT_RESULT_CLIP_VERTEX)
155 continue;
156 if ((outputs_written & BITFIELD64_BIT(i)) &&
157 vue_map->vert_result_to_slot[i] == -1) {
158 assign_vue_slot(vue_map, i);
159 }
160 }
161 }
162
163
164 /**
165 * Decide which set of clip planes should be used when clipping via
166 * gl_Position or gl_ClipVertex.
167 */
168 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
169 {
170 if (ctx->Shader.CurrentVertexProgram) {
171 /* There is currently a GLSL vertex shader, so clip according to GLSL
172 * rules, which means compare gl_ClipVertex (or gl_Position, if
173 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
174 * that were stored in EyeUserPlane at the time the clip planes were
175 * specified.
176 */
177 return ctx->Transform.EyeUserPlane;
178 } else {
179 /* Either we are using fixed function or an ARB vertex program. In
180 * either case the clip planes are going to be compared against
181 * gl_Position (which is in clip coordinates) so we have to clip using
182 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
183 * core.
184 */
185 return ctx->Transform._ClipUserPlane;
186 }
187 }
188
189
190 static bool
191 do_vs_prog(struct brw_context *brw,
192 struct gl_shader_program *prog,
193 struct brw_vertex_program *vp,
194 struct brw_vs_prog_key *key)
195 {
196 struct gl_context *ctx = &brw->intel.ctx;
197 struct intel_context *intel = &brw->intel;
198 GLuint program_size;
199 const GLuint *program;
200 struct brw_vs_compile c;
201 void *mem_ctx;
202 int aux_size;
203 int i;
204
205 memset(&c, 0, sizeof(c));
206 memcpy(&c.key, key, sizeof(*key));
207
208 mem_ctx = ralloc_context(NULL);
209
210 brw_init_compile(brw, &c.func, mem_ctx);
211 c.vp = vp;
212
213 c.prog_data.outputs_written = vp->program.Base.OutputsWritten;
214 c.prog_data.inputs_read = vp->program.Base.InputsRead;
215
216 if (c.key.copy_edgeflag) {
217 c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_EDGE);
218 c.prog_data.inputs_read |= VERT_BIT_EDGEFLAG;
219 }
220
221 /* Put dummy slots into the VUE for the SF to put the replaced
222 * point sprite coords in. We shouldn't need these dummy slots,
223 * which take up precious URB space, but it would mean that the SF
224 * doesn't get nice aligned pairs of input coords into output
225 * coords, which would be a pain to handle.
226 */
227 for (i = 0; i < 8; i++) {
228 if (c.key.point_coord_replace & (1 << i))
229 c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_TEX0 + i);
230 }
231
232 brw_compute_vue_map(&c);
233
234 if (0) {
235 _mesa_fprint_program_opt(stdout, &c.vp->program.Base, PROG_PRINT_DEBUG,
236 true);
237 }
238
239 /* Emit GEN4 code.
240 */
241 if (prog) {
242 if (!brw_vs_emit(prog, &c)) {
243 ralloc_free(mem_ctx);
244 return false;
245 }
246 } else {
247 brw_old_vs_emit(&c);
248 }
249
250 if (c.prog_data.nr_pull_params)
251 c.prog_data.num_surfaces = 1;
252 if (c.vp->program.Base.SamplersUsed)
253 c.prog_data.num_surfaces = SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT);
254 if (prog &&
255 prog->_LinkedShaders[MESA_SHADER_VERTEX]->NumUniformBlocks) {
256 c.prog_data.num_surfaces =
257 SURF_INDEX_VS_UBO(prog->_LinkedShaders[MESA_SHADER_VERTEX]->NumUniformBlocks);
258 }
259
260 /* Scratch space is used for register spilling */
261 if (c.last_scratch) {
262 perf_debug("Vertex shader triggered register spilling. "
263 "Try reducing the number of live vec4 values to "
264 "improve performance.\n");
265
266 c.prog_data.total_scratch = brw_get_scratch_size(c.last_scratch);
267
268 brw_get_scratch_bo(intel, &brw->vs.scratch_bo,
269 c.prog_data.total_scratch * brw->max_vs_threads);
270 }
271
272 /* get the program
273 */
274 program = brw_get_program(&c.func, &program_size);
275
276 /* We upload from &c.prog_data including the constant_map assuming
277 * they're packed together. It would be nice to have a
278 * compile-time assert macro here.
279 */
280 assert(c.constant_map == (int8_t *)&c.prog_data +
281 sizeof(c.prog_data));
282 assert(ctx->Const.VertexProgram.MaxNativeParameters ==
283 ARRAY_SIZE(c.constant_map));
284 (void) ctx;
285
286 aux_size = sizeof(c.prog_data);
287 /* constant_map */
288 aux_size += c.vp->program.Base.Parameters->NumParameters;
289
290 brw_upload_cache(&brw->cache, BRW_VS_PROG,
291 &c.key, sizeof(c.key),
292 program, program_size,
293 &c.prog_data, aux_size,
294 &brw->vs.prog_offset, &brw->vs.prog_data);
295 ralloc_free(mem_ctx);
296
297 return true;
298 }
299
300 static bool
301 key_debug(const char *name, int a, int b)
302 {
303 if (a != b) {
304 perf_debug(" %s %d->%d\n", name, a, b);
305 return true;
306 }
307 return false;
308 }
309
310 void
311 brw_vs_debug_recompile(struct brw_context *brw,
312 struct gl_shader_program *prog,
313 const struct brw_vs_prog_key *key)
314 {
315 struct brw_cache_item *c = NULL;
316 const struct brw_vs_prog_key *old_key = NULL;
317 bool found = false;
318
319 perf_debug("Recompiling vertex shader for program %d\n", prog->Name);
320
321 for (unsigned int i = 0; i < brw->cache.size; i++) {
322 for (c = brw->cache.items[i]; c; c = c->next) {
323 if (c->cache_id == BRW_VS_PROG) {
324 old_key = c->key;
325
326 if (old_key->program_string_id == key->program_string_id)
327 break;
328 }
329 }
330 if (c)
331 break;
332 }
333
334 if (!c) {
335 perf_debug(" Didn't find previous compile in the shader cache for "
336 "debug\n");
337 return;
338 }
339
340 for (unsigned int i = 0; i < VERT_ATTRIB_MAX; i++) {
341 found |= key_debug("GL_FIXED rescaling",
342 old_key->gl_fixed_input_size[i],
343 key->gl_fixed_input_size[i]);
344 }
345
346 found |= key_debug("user clip flags",
347 old_key->userclip_active, key->userclip_active);
348
349 found |= key_debug("user clipping planes as push constants",
350 old_key->nr_userclip_plane_consts,
351 key->nr_userclip_plane_consts);
352
353 found |= key_debug("clip distance enable",
354 old_key->uses_clip_distance, key->uses_clip_distance);
355 found |= key_debug("clip plane enable bitfield",
356 old_key->userclip_planes_enabled_gen_4_5,
357 key->userclip_planes_enabled_gen_4_5);
358 found |= key_debug("copy edgeflag",
359 old_key->copy_edgeflag, key->copy_edgeflag);
360 found |= key_debug("PointCoord replace",
361 old_key->point_coord_replace, key->point_coord_replace);
362 found |= key_debug("vertex color clamping",
363 old_key->clamp_vertex_color, key->clamp_vertex_color);
364
365 found |= brw_debug_recompile_sampler_key(&old_key->tex, &key->tex);
366
367 if (!found) {
368 perf_debug(" Something else\n");
369 }
370 }
371
372 static void brw_upload_vs_prog(struct brw_context *brw)
373 {
374 struct intel_context *intel = &brw->intel;
375 struct gl_context *ctx = &intel->ctx;
376 struct brw_vs_prog_key key;
377 /* BRW_NEW_VERTEX_PROGRAM */
378 struct brw_vertex_program *vp =
379 (struct brw_vertex_program *)brw->vertex_program;
380 struct gl_program *prog = (struct gl_program *) brw->vertex_program;
381 int i;
382
383 memset(&key, 0, sizeof(key));
384
385 /* Just upload the program verbatim for now. Always send it all
386 * the inputs it asks for, whether they are varying or not.
387 */
388 key.program_string_id = vp->id;
389 key.userclip_active = (ctx->Transform.ClipPlanesEnabled != 0);
390 key.uses_clip_distance = vp->program.UsesClipDistance;
391 if (key.userclip_active && !key.uses_clip_distance) {
392 if (intel->gen < 6) {
393 key.nr_userclip_plane_consts
394 = _mesa_bitcount_64(ctx->Transform.ClipPlanesEnabled);
395 key.userclip_planes_enabled_gen_4_5
396 = ctx->Transform.ClipPlanesEnabled;
397 } else {
398 key.nr_userclip_plane_consts
399 = _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1;
400 }
401 }
402
403 /* _NEW_POLYGON */
404 if (intel->gen < 6) {
405 key.copy_edgeflag = (ctx->Polygon.FrontMode != GL_FILL ||
406 ctx->Polygon.BackMode != GL_FILL);
407 }
408
409 /* _NEW_LIGHT | _NEW_BUFFERS */
410 key.clamp_vertex_color = ctx->Light._ClampVertexColor;
411
412 /* _NEW_POINT */
413 if (ctx->Point.PointSprite) {
414 for (i = 0; i < 8; i++) {
415 if (ctx->Point.CoordReplace[i])
416 key.point_coord_replace |= (1 << i);
417 }
418 }
419
420 /* _NEW_TEXTURE */
421 brw_populate_sampler_prog_key_data(ctx, prog, &key.tex);
422
423 /* BRW_NEW_VERTICES */
424 for (i = 0; i < VERT_ATTRIB_MAX; i++) {
425 if (vp->program.Base.InputsRead & BITFIELD64_BIT(i) &&
426 brw->vb.inputs[i].glarray->Type == GL_FIXED) {
427 key.gl_fixed_input_size[i] = brw->vb.inputs[i].glarray->Size;
428 }
429 }
430
431 if (!brw_search_cache(&brw->cache, BRW_VS_PROG,
432 &key, sizeof(key),
433 &brw->vs.prog_offset, &brw->vs.prog_data)) {
434 bool success = do_vs_prog(brw, ctx->Shader.CurrentVertexProgram,
435 vp, &key);
436
437 assert(success);
438 }
439 brw->vs.constant_map = ((int8_t *)brw->vs.prog_data +
440 sizeof(*brw->vs.prog_data));
441 }
442
443 /* See brw_vs.c:
444 */
445 const struct brw_tracked_state brw_vs_prog = {
446 .dirty = {
447 .mesa = (_NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT | _NEW_LIGHT |
448 _NEW_TEXTURE |
449 _NEW_BUFFERS),
450 .brw = (BRW_NEW_VERTEX_PROGRAM |
451 BRW_NEW_VERTICES),
452 .cache = 0
453 },
454 .emit = brw_upload_vs_prog
455 };
456
457 bool
458 brw_vs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
459 {
460 struct brw_context *brw = brw_context(ctx);
461 struct brw_vs_prog_key key;
462 uint32_t old_prog_offset = brw->vs.prog_offset;
463 struct brw_vs_prog_data *old_prog_data = brw->vs.prog_data;
464 bool success;
465
466 if (!prog->_LinkedShaders[MESA_SHADER_VERTEX])
467 return true;
468
469 struct gl_vertex_program *vp = (struct gl_vertex_program *)
470 prog->_LinkedShaders[MESA_SHADER_VERTEX]->Program;
471 struct brw_vertex_program *bvp = brw_vertex_program(vp);
472
473 memset(&key, 0, sizeof(key));
474
475 key.program_string_id = bvp->id;
476 key.clamp_vertex_color = true;
477
478 success = do_vs_prog(brw, prog, bvp, &key);
479
480 brw->vs.prog_offset = old_prog_offset;
481 brw->vs.prog_data = old_prog_data;
482
483 return success;
484 }