i965: Generalize GL_FIXED VS w/a support
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vs.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/compiler.h"
34 #include "brw_context.h"
35 #include "brw_vs.h"
36 #include "brw_util.h"
37 #include "brw_state.h"
38 #include "program/prog_print.h"
39 #include "program/prog_parameter.h"
40
41 #include "glsl/ralloc.h"
42
43 static inline void assign_vue_slot(struct brw_vue_map *vue_map,
44 int vert_result)
45 {
46 /* Make sure this vert_result hasn't been assigned a slot already */
47 assert (vue_map->vert_result_to_slot[vert_result] == -1);
48
49 vue_map->vert_result_to_slot[vert_result] = vue_map->num_slots;
50 vue_map->slot_to_vert_result[vue_map->num_slots++] = vert_result;
51 }
52
53 /**
54 * Compute the VUE map for vertex shader program.
55 *
56 * Note that consumers of this map using cache keys must include
57 * prog_data->userclip and prog_data->outputs_written in their key
58 * (generated by CACHE_NEW_VS_PROG).
59 */
60 static void
61 brw_compute_vue_map(struct brw_vs_compile *c)
62 {
63 struct brw_context *brw = c->func.brw;
64 const struct intel_context *intel = &brw->intel;
65 struct brw_vue_map *vue_map = &c->prog_data.vue_map;
66 GLbitfield64 outputs_written = c->prog_data.outputs_written;
67 int i;
68
69 vue_map->num_slots = 0;
70 for (i = 0; i < BRW_VERT_RESULT_MAX; ++i) {
71 vue_map->vert_result_to_slot[i] = -1;
72 vue_map->slot_to_vert_result[i] = BRW_VERT_RESULT_MAX;
73 }
74
75 /* VUE header: format depends on chip generation and whether clipping is
76 * enabled.
77 */
78 switch (intel->gen) {
79 case 4:
80 /* There are 8 dwords in VUE header pre-Ironlake:
81 * dword 0-3 is indices, point width, clip flags.
82 * dword 4-7 is ndc position
83 * dword 8-11 is the first vertex data.
84 */
85 assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
86 assign_vue_slot(vue_map, BRW_VERT_RESULT_NDC);
87 assign_vue_slot(vue_map, VERT_RESULT_HPOS);
88 break;
89 case 5:
90 /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
91 * dword 0-3 of the header is indices, point width, clip flags.
92 * dword 4-7 is the ndc position
93 * dword 8-11 of the vertex header is the 4D space position
94 * dword 12-19 of the vertex header is the user clip distance.
95 * dword 20-23 is a pad so that the vertex element data is aligned
96 * dword 24-27 is the first vertex data we fill.
97 *
98 * Note: future pipeline stages expect 4D space position to be
99 * contiguous with the other vert_results, so we make dword 24-27 a
100 * duplicate copy of the 4D space position.
101 */
102 assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
103 assign_vue_slot(vue_map, BRW_VERT_RESULT_NDC);
104 assign_vue_slot(vue_map, BRW_VERT_RESULT_HPOS_DUPLICATE);
105 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST0);
106 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST1);
107 assign_vue_slot(vue_map, BRW_VERT_RESULT_PAD);
108 assign_vue_slot(vue_map, VERT_RESULT_HPOS);
109 break;
110 case 6:
111 case 7:
112 /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
113 * dword 0-3 of the header is indices, point width, clip flags.
114 * dword 4-7 is the 4D space position
115 * dword 8-15 of the vertex header is the user clip distance if
116 * enabled.
117 * dword 8-11 or 16-19 is the first vertex element data we fill.
118 */
119 assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
120 assign_vue_slot(vue_map, VERT_RESULT_HPOS);
121 if (c->key.userclip_active) {
122 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST0);
123 assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST1);
124 }
125 /* front and back colors need to be consecutive so that we can use
126 * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing
127 * two-sided color.
128 */
129 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_COL0))
130 assign_vue_slot(vue_map, VERT_RESULT_COL0);
131 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC0))
132 assign_vue_slot(vue_map, VERT_RESULT_BFC0);
133 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_COL1))
134 assign_vue_slot(vue_map, VERT_RESULT_COL1);
135 if (outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC1))
136 assign_vue_slot(vue_map, VERT_RESULT_BFC1);
137 break;
138 default:
139 assert (!"VUE map not known for this chip generation");
140 break;
141 }
142
143 /* The hardware doesn't care about the rest of the vertex outputs, so just
144 * assign them contiguously. Don't reassign outputs that already have a
145 * slot.
146 *
147 * Also, prior to Gen6, don't assign a slot for VERT_RESULT_CLIP_VERTEX,
148 * since it is unsupported. In Gen6 and above, VERT_RESULT_CLIP_VERTEX may
149 * be needed for transform feedback; since we don't want to have to
150 * recompute the VUE map (and everything that depends on it) when transform
151 * feedback is enabled or disabled, just go ahead and assign a slot for it.
152 */
153 for (int i = 0; i < VERT_RESULT_MAX; ++i) {
154 if (intel->gen < 6 && i == VERT_RESULT_CLIP_VERTEX)
155 continue;
156 if ((outputs_written & BITFIELD64_BIT(i)) &&
157 vue_map->vert_result_to_slot[i] == -1) {
158 assign_vue_slot(vue_map, i);
159 }
160 }
161 }
162
163
164 /**
165 * Decide which set of clip planes should be used when clipping via
166 * gl_Position or gl_ClipVertex.
167 */
168 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
169 {
170 if (ctx->Shader.CurrentVertexProgram) {
171 /* There is currently a GLSL vertex shader, so clip according to GLSL
172 * rules, which means compare gl_ClipVertex (or gl_Position, if
173 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
174 * that were stored in EyeUserPlane at the time the clip planes were
175 * specified.
176 */
177 return ctx->Transform.EyeUserPlane;
178 } else {
179 /* Either we are using fixed function or an ARB vertex program. In
180 * either case the clip planes are going to be compared against
181 * gl_Position (which is in clip coordinates) so we have to clip using
182 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
183 * core.
184 */
185 return ctx->Transform._ClipUserPlane;
186 }
187 }
188
189 bool
190 brw_vs_prog_data_compare(const void *in_a, const void *in_b,
191 int aux_size, const void *in_key)
192 {
193 const struct brw_vs_prog_data *a = in_a;
194 const struct brw_vs_prog_data *b = in_b;
195
196 /* Compare all the struct up to the pointers. */
197 if (memcmp(a, b, offsetof(struct brw_vs_prog_data, param)))
198 return false;
199
200 if (memcmp(a->param, b->param, a->nr_params * sizeof(void *)))
201 return false;
202
203 if (memcmp(a->pull_param, b->pull_param, a->nr_pull_params * sizeof(void *)))
204 return false;
205
206 return true;
207 }
208
209 static bool
210 do_vs_prog(struct brw_context *brw,
211 struct gl_shader_program *prog,
212 struct brw_vertex_program *vp,
213 struct brw_vs_prog_key *key)
214 {
215 struct intel_context *intel = &brw->intel;
216 GLuint program_size;
217 const GLuint *program;
218 struct brw_vs_compile c;
219 void *mem_ctx;
220 int i;
221 struct gl_shader *vs = NULL;
222
223 if (prog)
224 vs = prog->_LinkedShaders[MESA_SHADER_VERTEX];
225
226 memset(&c, 0, sizeof(c));
227 memcpy(&c.key, key, sizeof(*key));
228
229 mem_ctx = ralloc_context(NULL);
230
231 brw_init_compile(brw, &c.func, mem_ctx);
232 c.vp = vp;
233
234 /* Allocate the references to the uniforms that will end up in the
235 * prog_data associated with the compiled program, and which will be freed
236 * by the state cache.
237 */
238 int param_count;
239 if (vs) {
240 /* We add padding around uniform values below vec4 size, with the worst
241 * case being a float value that gets blown up to a vec4, so be
242 * conservative here.
243 */
244 param_count = vs->num_uniform_components * 4;
245
246 } else {
247 param_count = vp->program.Base.Parameters->NumParameters * 4;
248 }
249 /* We also upload clip plane data as uniforms */
250 param_count += MAX_CLIP_PLANES * 4;
251
252 c.prog_data.param = rzalloc_array(NULL, const float *, param_count);
253 c.prog_data.pull_param = rzalloc_array(NULL, const float *, param_count);
254
255 c.prog_data.outputs_written = vp->program.Base.OutputsWritten;
256 c.prog_data.inputs_read = vp->program.Base.InputsRead;
257
258 if (c.key.copy_edgeflag) {
259 c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_EDGE);
260 c.prog_data.inputs_read |= VERT_BIT_EDGEFLAG;
261 }
262
263 /* Put dummy slots into the VUE for the SF to put the replaced
264 * point sprite coords in. We shouldn't need these dummy slots,
265 * which take up precious URB space, but it would mean that the SF
266 * doesn't get nice aligned pairs of input coords into output
267 * coords, which would be a pain to handle.
268 */
269 for (i = 0; i < 8; i++) {
270 if (c.key.point_coord_replace & (1 << i))
271 c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_TEX0 + i);
272 }
273
274 brw_compute_vue_map(&c);
275
276 if (0) {
277 _mesa_fprint_program_opt(stdout, &c.vp->program.Base, PROG_PRINT_DEBUG,
278 true);
279 }
280
281 /* Emit GEN4 code.
282 */
283 if (!brw_vs_emit(prog, &c)) {
284 ralloc_free(mem_ctx);
285 return false;
286 }
287
288 if (c.prog_data.nr_pull_params)
289 c.prog_data.num_surfaces = 1;
290 if (c.vp->program.Base.SamplersUsed)
291 c.prog_data.num_surfaces = SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT);
292 if (prog &&
293 prog->_LinkedShaders[MESA_SHADER_VERTEX]->NumUniformBlocks) {
294 c.prog_data.num_surfaces =
295 SURF_INDEX_VS_UBO(prog->_LinkedShaders[MESA_SHADER_VERTEX]->NumUniformBlocks);
296 }
297
298 /* Scratch space is used for register spilling */
299 if (c.last_scratch) {
300 perf_debug("Vertex shader triggered register spilling. "
301 "Try reducing the number of live vec4 values to "
302 "improve performance.\n");
303
304 c.prog_data.total_scratch = brw_get_scratch_size(c.last_scratch*REG_SIZE);
305
306 brw_get_scratch_bo(intel, &brw->vs.scratch_bo,
307 c.prog_data.total_scratch * brw->max_vs_threads);
308 }
309
310 /* get the program
311 */
312 program = brw_get_program(&c.func, &program_size);
313
314 brw_upload_cache(&brw->cache, BRW_VS_PROG,
315 &c.key, sizeof(c.key),
316 program, program_size,
317 &c.prog_data, sizeof(c.prog_data),
318 &brw->vs.prog_offset, &brw->vs.prog_data);
319 ralloc_free(mem_ctx);
320
321 return true;
322 }
323
324 static bool
325 key_debug(const char *name, int a, int b)
326 {
327 if (a != b) {
328 perf_debug(" %s %d->%d\n", name, a, b);
329 return true;
330 }
331 return false;
332 }
333
334 void
335 brw_vs_debug_recompile(struct brw_context *brw,
336 struct gl_shader_program *prog,
337 const struct brw_vs_prog_key *key)
338 {
339 struct brw_cache_item *c = NULL;
340 const struct brw_vs_prog_key *old_key = NULL;
341 bool found = false;
342
343 perf_debug("Recompiling vertex shader for program %d\n", prog->Name);
344
345 for (unsigned int i = 0; i < brw->cache.size; i++) {
346 for (c = brw->cache.items[i]; c; c = c->next) {
347 if (c->cache_id == BRW_VS_PROG) {
348 old_key = c->key;
349
350 if (old_key->program_string_id == key->program_string_id)
351 break;
352 }
353 }
354 if (c)
355 break;
356 }
357
358 if (!c) {
359 perf_debug(" Didn't find previous compile in the shader cache for "
360 "debug\n");
361 return;
362 }
363
364 for (unsigned int i = 0; i < VERT_ATTRIB_MAX; i++) {
365 found |= key_debug("Vertex attrib w/a flags",
366 old_key->gl_attrib_wa_flags[i],
367 key->gl_attrib_wa_flags[i]);
368 }
369
370 found |= key_debug("user clip flags",
371 old_key->userclip_active, key->userclip_active);
372
373 found |= key_debug("user clipping planes as push constants",
374 old_key->nr_userclip_plane_consts,
375 key->nr_userclip_plane_consts);
376
377 found |= key_debug("clip distance enable",
378 old_key->uses_clip_distance, key->uses_clip_distance);
379 found |= key_debug("clip plane enable bitfield",
380 old_key->userclip_planes_enabled_gen_4_5,
381 key->userclip_planes_enabled_gen_4_5);
382 found |= key_debug("copy edgeflag",
383 old_key->copy_edgeflag, key->copy_edgeflag);
384 found |= key_debug("PointCoord replace",
385 old_key->point_coord_replace, key->point_coord_replace);
386 found |= key_debug("vertex color clamping",
387 old_key->clamp_vertex_color, key->clamp_vertex_color);
388
389 found |= brw_debug_recompile_sampler_key(&old_key->tex, &key->tex);
390
391 if (!found) {
392 perf_debug(" Something else\n");
393 }
394 }
395
396 static void brw_upload_vs_prog(struct brw_context *brw)
397 {
398 struct intel_context *intel = &brw->intel;
399 struct gl_context *ctx = &intel->ctx;
400 struct brw_vs_prog_key key;
401 /* BRW_NEW_VERTEX_PROGRAM */
402 struct brw_vertex_program *vp =
403 (struct brw_vertex_program *)brw->vertex_program;
404 struct gl_program *prog = (struct gl_program *) brw->vertex_program;
405 int i;
406
407 memset(&key, 0, sizeof(key));
408
409 /* Just upload the program verbatim for now. Always send it all
410 * the inputs it asks for, whether they are varying or not.
411 */
412 key.program_string_id = vp->id;
413 key.userclip_active = (ctx->Transform.ClipPlanesEnabled != 0);
414 key.uses_clip_distance = vp->program.UsesClipDistance;
415 if (key.userclip_active && !key.uses_clip_distance) {
416 if (intel->gen < 6) {
417 key.nr_userclip_plane_consts
418 = _mesa_bitcount_64(ctx->Transform.ClipPlanesEnabled);
419 key.userclip_planes_enabled_gen_4_5
420 = ctx->Transform.ClipPlanesEnabled;
421 } else {
422 key.nr_userclip_plane_consts
423 = _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1;
424 }
425 }
426
427 /* _NEW_POLYGON */
428 if (intel->gen < 6) {
429 key.copy_edgeflag = (ctx->Polygon.FrontMode != GL_FILL ||
430 ctx->Polygon.BackMode != GL_FILL);
431 }
432
433 /* _NEW_LIGHT | _NEW_BUFFERS */
434 key.clamp_vertex_color = ctx->Light._ClampVertexColor;
435
436 /* _NEW_POINT */
437 if (ctx->Point.PointSprite) {
438 for (i = 0; i < 8; i++) {
439 if (ctx->Point.CoordReplace[i])
440 key.point_coord_replace |= (1 << i);
441 }
442 }
443
444 /* _NEW_TEXTURE */
445 brw_populate_sampler_prog_key_data(ctx, prog, &key.tex);
446
447 /* BRW_NEW_VERTICES */
448 for (i = 0; i < VERT_ATTRIB_MAX; i++) {
449 /* TODO: flag w/a for packed vertex formats here too */
450 if (vp->program.Base.InputsRead & BITFIELD64_BIT(i) &&
451 brw->vb.inputs[i].glarray->Type == GL_FIXED) {
452 key.gl_attrib_wa_flags[i] = brw->vb.inputs[i].glarray->Size;
453 }
454 }
455
456 if (!brw_search_cache(&brw->cache, BRW_VS_PROG,
457 &key, sizeof(key),
458 &brw->vs.prog_offset, &brw->vs.prog_data)) {
459 bool success = do_vs_prog(brw, ctx->Shader.CurrentVertexProgram,
460 vp, &key);
461
462 assert(success);
463 }
464 }
465
466 /* See brw_vs.c:
467 */
468 const struct brw_tracked_state brw_vs_prog = {
469 .dirty = {
470 .mesa = (_NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT | _NEW_LIGHT |
471 _NEW_TEXTURE |
472 _NEW_BUFFERS),
473 .brw = (BRW_NEW_VERTEX_PROGRAM |
474 BRW_NEW_VERTICES),
475 .cache = 0
476 },
477 .emit = brw_upload_vs_prog
478 };
479
480 bool
481 brw_vs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
482 {
483 struct brw_context *brw = brw_context(ctx);
484 struct brw_vs_prog_key key;
485 uint32_t old_prog_offset = brw->vs.prog_offset;
486 struct brw_vs_prog_data *old_prog_data = brw->vs.prog_data;
487 bool success;
488
489 if (!prog->_LinkedShaders[MESA_SHADER_VERTEX])
490 return true;
491
492 struct gl_vertex_program *vp = (struct gl_vertex_program *)
493 prog->_LinkedShaders[MESA_SHADER_VERTEX]->Program;
494 struct brw_vertex_program *bvp = brw_vertex_program(vp);
495
496 memset(&key, 0, sizeof(key));
497
498 key.program_string_id = bvp->id;
499 key.clamp_vertex_color = true;
500
501 for (int i = 0; i < MAX_SAMPLERS; i++) {
502 if (vp->Base.ShadowSamplers & (1 << i)) {
503 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
504 key.tex.swizzles[i] =
505 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_ONE);
506 } else {
507 /* Color sampler: assume no swizzling. */
508 key.tex.swizzles[i] = SWIZZLE_XYZW;
509 }
510 }
511
512 success = do_vs_prog(brw, prog, bvp, &key);
513
514 brw->vs.prog_offset = old_prog_offset;
515 brw->vs.prog_data = old_prog_data;
516
517 return success;
518 }
519
520 void
521 brw_vs_prog_data_free(const void *in_prog_data)
522 {
523 const struct brw_vs_prog_data *prog_data = in_prog_data;
524
525 ralloc_free((void *)prog_data->param);
526 ralloc_free((void *)prog_data->pull_param);
527 }