mesa/i965/i915/r200: eliminate gl_vertex_program
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vs.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRW_VS_H
34 #define BRW_VS_H
35
36
37 #include "brw_vec4.h"
38
39 /**
40 * The VF can't natively handle certain types of attributes, such as GL_FIXED
41 * or most 10_10_10_2 types. These flags enable various VS workarounds to
42 * "fix" attributes at the beginning of shaders.
43 */
44 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
45 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
46 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
47 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
48 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
49
50 #ifdef __cplusplus
51 extern "C" {
52 #endif
53
54 GLbitfield64
55 brw_vs_outputs_written(struct brw_context *brw, struct brw_vs_prog_key *key,
56 GLbitfield64 outputs_written);
57
58 void brw_vs_debug_recompile(struct brw_context *brw,
59 struct gl_shader_program *prog,
60 const struct brw_vs_prog_key *key);
61
62 void
63 brw_upload_vs_prog(struct brw_context *brw);
64
65 bool
66 brw_codegen_vs_prog(struct brw_context *brw,
67 struct gl_shader_program *prog,
68 struct brw_vertex_program *vp,
69 struct brw_vs_prog_key *key);
70
71 void
72 brw_vs_populate_key(struct brw_context *brw,
73 struct brw_vs_prog_key *key);
74
75 #ifdef __cplusplus
76 } /* extern "C" */
77
78
79 namespace brw {
80
81 class vec4_vs_visitor : public vec4_visitor
82 {
83 public:
84 vec4_vs_visitor(const struct brw_compiler *compiler,
85 void *log_data,
86 const struct brw_vs_prog_key *key,
87 struct brw_vs_prog_data *vs_prog_data,
88 const nir_shader *shader,
89 gl_clip_plane *clip_planes,
90 void *mem_ctx,
91 int shader_time_index,
92 bool use_legacy_snorm_formula);
93
94 protected:
95 virtual dst_reg *make_reg_for_system_value(int location);
96 virtual void setup_payload();
97 virtual void emit_prolog();
98 virtual void emit_thread_end();
99 virtual void emit_urb_write_header(int mrf);
100 virtual void emit_urb_slot(dst_reg reg, int varying);
101 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
102
103 private:
104 int setup_attributes(int payload_reg);
105 void setup_uniform_clipplane_values();
106 void emit_clip_distances(dst_reg reg, int offset);
107
108 const struct brw_vs_prog_key *const key;
109 struct brw_vs_prog_data * const vs_prog_data;
110
111 gl_clip_plane *clip_planes;
112
113 bool use_legacy_snorm_formula;
114 };
115
116 } /* namespace brw */
117
118
119 #endif
120
121 #endif