2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/macros.h"
34 #include "shader/program.h"
35 #include "shader/prog_parameter.h"
36 #include "shader/prog_print.h"
37 #include "brw_context.h"
41 static struct brw_reg
get_tmp( struct brw_vs_compile
*c
)
43 struct brw_reg tmp
= brw_vec8_grf(c
->last_tmp
, 0);
45 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
46 c
->prog_data
.total_grf
= c
->last_tmp
;
51 static void release_tmp( struct brw_vs_compile
*c
, struct brw_reg tmp
)
53 if (tmp
.nr
== c
->last_tmp
-1)
57 static void release_tmps( struct brw_vs_compile
*c
)
59 c
->last_tmp
= c
->first_tmp
;
64 * Preallocate GRF register before code emit.
65 * Do things as simply as possible. Allocate and populate all regs
68 static void brw_vs_alloc_regs( struct brw_vs_compile
*c
)
70 GLuint i
, reg
= 0, mrf
;
71 int attributes_in_vue
;
73 /* Determine whether to use a real constant buffer or use a block
74 * of GRF registers for constants. The later is faster but only
75 * works if everything fits in the GRF.
76 * XXX this heuristic/check may need some fine tuning...
78 if (c
->vp
->program
.Base
.Parameters
->NumParameters
+
79 c
->vp
->program
.Base
.NumTemporaries
+ 20 > BRW_MAX_GRF
)
80 c
->vp
->use_const_buffer
= GL_TRUE
;
82 c
->vp
->use_const_buffer
= GL_FALSE
;
84 /*printf("use_const_buffer = %d\n", c->vp->use_const_buffer);*/
86 /* r0 -- reserved as usual
88 c
->r0
= brw_vec8_grf(reg
, 0);
91 /* User clip planes from curbe:
93 if (c
->key
.nr_userclip
) {
94 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
95 c
->userplane
[i
] = stride( brw_vec4_grf(reg
+3+i
/2, (i
%2) * 4), 0, 4, 1);
98 /* Deal with curbe alignment:
100 reg
+= ((6 + c
->key
.nr_userclip
+ 3) / 4) * 2;
103 /* Vertex program parameters from curbe:
105 if (c
->vp
->use_const_buffer
) {
106 /* get constants from a real constant buffer */
107 c
->prog_data
.curb_read_length
= 0;
108 c
->prog_data
.nr_params
= 4; /* XXX 0 causes a bug elsewhere... */
111 /* use a section of the GRF for constants */
112 GLuint nr_params
= c
->vp
->program
.Base
.Parameters
->NumParameters
;
113 for (i
= 0; i
< nr_params
; i
++) {
114 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2, (i
%2) * 4), 0, 4, 1);
116 reg
+= (nr_params
+ 1) / 2;
117 c
->prog_data
.curb_read_length
= reg
- 1;
119 c
->prog_data
.nr_params
= nr_params
* 4;
122 /* Allocate input regs:
125 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
126 if (c
->prog_data
.inputs_read
& (1 << i
)) {
128 c
->regs
[PROGRAM_INPUT
][i
] = brw_vec8_grf(reg
, 0);
132 /* If there are no inputs, we'll still be reading one attribute's worth
133 * because it's required -- see urb_read_length setting.
135 if (c
->nr_inputs
== 0)
138 /* Allocate outputs. The non-position outputs go straight into message regs.
141 c
->first_output
= reg
;
142 c
->first_overflow_output
= 0;
144 if (BRW_IS_IGDNG(c
->func
.brw
))
149 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
150 if (c
->prog_data
.outputs_written
& (1 << i
)) {
152 assert(i
< Elements(c
->regs
[PROGRAM_OUTPUT
]));
153 if (i
== VERT_RESULT_HPOS
) {
154 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
157 else if (i
== VERT_RESULT_PSIZ
) {
158 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
160 mrf
++; /* just a placeholder? XXX fix later stages & remove this */
164 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_message_reg(mrf
);
168 /* too many vertex results to fit in MRF, use GRF for overflow */
169 if (!c
->first_overflow_output
)
170 c
->first_overflow_output
= i
;
171 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
178 /* Allocate program temporaries:
180 for (i
= 0; i
< c
->vp
->program
.Base
.NumTemporaries
; i
++) {
181 c
->regs
[PROGRAM_TEMPORARY
][i
] = brw_vec8_grf(reg
, 0);
185 /* Address reg(s). Don't try to use the internal address reg until
188 for (i
= 0; i
< c
->vp
->program
.Base
.NumAddressRegs
; i
++) {
189 c
->regs
[PROGRAM_ADDRESS
][i
] = brw_reg(BRW_GENERAL_REGISTER_FILE
,
193 BRW_VERTICAL_STRIDE_8
,
195 BRW_HORIZONTAL_STRIDE_1
,
201 if (c
->vp
->use_const_buffer
) {
202 for (i
= 0; i
< 3; i
++) {
203 c
->current_const
[i
].index
= -1;
204 c
->current_const
[i
].reg
= brw_vec8_grf(reg
, 0);
209 for (i
= 0; i
< 128; i
++) {
210 if (c
->output_regs
[i
].used_in_src
) {
211 c
->output_regs
[i
].reg
= brw_vec8_grf(reg
, 0);
216 c
->stack
= brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, reg
, 0);
219 /* Some opcodes need an internal temporary:
222 c
->last_tmp
= reg
; /* for allocation purposes */
224 /* Each input reg holds data from two vertices. The
225 * urb_read_length is the number of registers read from *each*
226 * vertex urb, so is half the amount:
228 c
->prog_data
.urb_read_length
= (c
->nr_inputs
+ 1) / 2;
229 /* Setting this field to 0 leads to undefined behavior according to the
230 * the VS_STATE docs. Our VUEs will always have at least one attribute
231 * sitting in them, even if it's padding.
233 if (c
->prog_data
.urb_read_length
== 0)
234 c
->prog_data
.urb_read_length
= 1;
236 /* The VS VUEs are shared by VF (outputting our inputs) and VS, so size
237 * them to fit the biggest thing they need to.
239 attributes_in_vue
= MAX2(c
->nr_outputs
, c
->nr_inputs
);
241 if (BRW_IS_IGDNG(c
->func
.brw
))
242 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 6 + 3) / 4;
244 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 2 + 3) / 4;
246 c
->prog_data
.total_grf
= reg
;
248 if (INTEL_DEBUG
& DEBUG_VS
) {
249 _mesa_printf("%s NumAddrRegs %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumAddressRegs
);
250 _mesa_printf("%s NumTemps %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumTemporaries
);
251 _mesa_printf("%s reg = %d\n", __FUNCTION__
, reg
);
257 * If an instruction uses a temp reg both as a src and the dest, we
258 * sometimes need to allocate an intermediate temporary.
260 static void unalias1( struct brw_vs_compile
*c
,
263 void (*func
)( struct brw_vs_compile
*,
267 if (dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) {
268 struct brw_compile
*p
= &c
->func
;
269 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
271 brw_MOV(p
, dst
, tmp
);
281 * Checkes if 2-operand instruction needs an intermediate temporary.
283 static void unalias2( struct brw_vs_compile
*c
,
287 void (*func
)( struct brw_vs_compile
*,
292 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
293 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
)) {
294 struct brw_compile
*p
= &c
->func
;
295 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
296 func(c
, tmp
, arg0
, arg1
);
297 brw_MOV(p
, dst
, tmp
);
301 func(c
, dst
, arg0
, arg1
);
307 * Checkes if 3-operand instruction needs an intermediate temporary.
309 static void unalias3( struct brw_vs_compile
*c
,
314 void (*func
)( struct brw_vs_compile
*,
320 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
321 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
) ||
322 (dst
.file
== arg2
.file
&& dst
.nr
== arg2
.nr
)) {
323 struct brw_compile
*p
= &c
->func
;
324 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
325 func(c
, tmp
, arg0
, arg1
, arg2
);
326 brw_MOV(p
, dst
, tmp
);
330 func(c
, dst
, arg0
, arg1
, arg2
);
334 static void emit_sop( struct brw_compile
*p
,
340 brw_MOV(p
, dst
, brw_imm_f(0.0f
));
341 brw_CMP(p
, brw_null_reg(), cond
, arg0
, arg1
);
342 brw_MOV(p
, dst
, brw_imm_f(1.0f
));
343 brw_set_predicate_control_flag_value(p
, 0xff);
346 static void emit_seq( struct brw_compile
*p
,
349 struct brw_reg arg1
)
351 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_EQ
);
354 static void emit_sne( struct brw_compile
*p
,
357 struct brw_reg arg1
)
359 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_NEQ
);
361 static void emit_slt( struct brw_compile
*p
,
364 struct brw_reg arg1
)
366 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_L
);
369 static void emit_sle( struct brw_compile
*p
,
372 struct brw_reg arg1
)
374 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_LE
);
377 static void emit_sgt( struct brw_compile
*p
,
380 struct brw_reg arg1
)
382 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_G
);
385 static void emit_sge( struct brw_compile
*p
,
388 struct brw_reg arg1
)
390 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_GE
);
393 static void emit_max( struct brw_compile
*p
,
396 struct brw_reg arg1
)
398 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
399 brw_SEL(p
, dst
, arg1
, arg0
);
400 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
403 static void emit_min( struct brw_compile
*p
,
406 struct brw_reg arg1
)
408 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
409 brw_SEL(p
, dst
, arg0
, arg1
);
410 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
414 static void emit_math1( struct brw_vs_compile
*c
,
420 /* There are various odd behaviours with SEND on the simulator. In
421 * addition there are documented issues with the fact that the GEN4
422 * processor doesn't do dependency control properly on SEND
423 * results. So, on balance, this kludge to get around failures
424 * with writemasked math results looks like it might be necessary
425 * whether that turns out to be a simulator bug or not:
427 struct brw_compile
*p
= &c
->func
;
428 struct brw_reg tmp
= dst
;
429 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
430 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
438 BRW_MATH_SATURATE_NONE
,
441 BRW_MATH_DATA_SCALAR
,
445 brw_MOV(p
, dst
, tmp
);
451 static void emit_math2( struct brw_vs_compile
*c
,
458 struct brw_compile
*p
= &c
->func
;
459 struct brw_reg tmp
= dst
;
460 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
461 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
466 brw_MOV(p
, brw_message_reg(3), arg1
);
471 BRW_MATH_SATURATE_NONE
,
474 BRW_MATH_DATA_SCALAR
,
478 brw_MOV(p
, dst
, tmp
);
484 static void emit_exp_noalias( struct brw_vs_compile
*c
,
486 struct brw_reg arg0
)
488 struct brw_compile
*p
= &c
->func
;
491 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
) {
492 struct brw_reg tmp
= get_tmp(c
);
493 struct brw_reg tmp_d
= retype(tmp
, BRW_REGISTER_TYPE_D
);
495 /* tmp_d = floor(arg0.x) */
496 brw_RNDD(p
, tmp_d
, brw_swizzle1(arg0
, 0));
498 /* result[0] = 2.0 ^ tmp */
500 /* Adjust exponent for floating point:
503 brw_ADD(p
, brw_writemask(tmp_d
, WRITEMASK_X
), tmp_d
, brw_imm_d(127));
505 /* Install exponent and sign.
506 * Excess drops off the edge:
508 brw_SHL(p
, brw_writemask(retype(dst
, BRW_REGISTER_TYPE_D
), WRITEMASK_X
),
509 tmp_d
, brw_imm_d(23));
514 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
) {
515 /* result[1] = arg0.x - floor(arg0.x) */
516 brw_FRC(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
, 0));
519 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
520 /* As with the LOG instruction, we might be better off just
521 * doing a taylor expansion here, seeing as we have to do all
524 * If mathbox partial precision is too low, consider also:
525 * result[3] = result[0] * EXP(result[1])
528 BRW_MATH_FUNCTION_EXP
,
529 brw_writemask(dst
, WRITEMASK_Z
),
530 brw_swizzle1(arg0
, 0),
531 BRW_MATH_PRECISION_FULL
);
534 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
535 /* result[3] = 1.0; */
536 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), brw_imm_f(1));
541 static void emit_log_noalias( struct brw_vs_compile
*c
,
543 struct brw_reg arg0
)
545 struct brw_compile
*p
= &c
->func
;
546 struct brw_reg tmp
= dst
;
547 struct brw_reg tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
548 struct brw_reg arg0_ud
= retype(arg0
, BRW_REGISTER_TYPE_UD
);
549 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
550 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
554 tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
557 /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt
560 * These almost look likey they could be joined up, but not really
563 * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127
564 * result[1].i = (x.i & ((1<<23)-1) + (127<<23)
566 if (dst
.dw1
.bits
.writemask
& WRITEMASK_XZ
) {
568 brw_writemask(tmp_ud
, WRITEMASK_X
),
569 brw_swizzle1(arg0_ud
, 0),
570 brw_imm_ud((1U<<31)-1));
573 brw_writemask(tmp_ud
, WRITEMASK_X
),
578 brw_writemask(tmp
, WRITEMASK_X
),
579 retype(tmp_ud
, BRW_REGISTER_TYPE_D
), /* does it matter? */
583 if (dst
.dw1
.bits
.writemask
& WRITEMASK_YZ
) {
585 brw_writemask(tmp_ud
, WRITEMASK_Y
),
586 brw_swizzle1(arg0_ud
, 0),
587 brw_imm_ud((1<<23)-1));
590 brw_writemask(tmp_ud
, WRITEMASK_Y
),
592 brw_imm_ud(127<<23));
595 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
596 /* result[2] = result[0] + LOG2(result[1]); */
598 /* Why bother? The above is just a hint how to do this with a
599 * taylor series. Maybe we *should* use a taylor series as by
600 * the time all the above has been done it's almost certainly
601 * quicker than calling the mathbox, even with low precision.
604 * - result[0] + mathbox.LOG2(result[1])
605 * - mathbox.LOG2(arg0.x)
606 * - result[0] + inline_taylor_approx(result[1])
609 BRW_MATH_FUNCTION_LOG
,
610 brw_writemask(tmp
, WRITEMASK_Z
),
611 brw_swizzle1(tmp
, 1),
612 BRW_MATH_PRECISION_FULL
);
615 brw_writemask(tmp
, WRITEMASK_Z
),
616 brw_swizzle1(tmp
, 2),
617 brw_swizzle1(tmp
, 0));
620 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
621 /* result[3] = 1.0; */
622 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_W
), brw_imm_f(1));
626 brw_MOV(p
, dst
, tmp
);
632 /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
634 static void emit_dst_noalias( struct brw_vs_compile
*c
,
639 struct brw_compile
*p
= &c
->func
;
641 /* There must be a better way to do this:
643 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
)
644 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_X
), brw_imm_f(1.0));
645 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
)
646 brw_MUL(p
, brw_writemask(dst
, WRITEMASK_Y
), arg0
, arg1
);
647 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
)
648 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Z
), arg0
);
649 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
)
650 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), arg1
);
654 static void emit_xpd( struct brw_compile
*p
,
659 brw_MUL(p
, brw_null_reg(), brw_swizzle(t
, 1,2,0,3), brw_swizzle(u
,2,0,1,3));
660 brw_MAC(p
, dst
, negate(brw_swizzle(t
, 2,0,1,3)), brw_swizzle(u
,1,2,0,3));
664 static void emit_lit_noalias( struct brw_vs_compile
*c
,
666 struct brw_reg arg0
)
668 struct brw_compile
*p
= &c
->func
;
669 struct brw_instruction
*if_insn
;
670 struct brw_reg tmp
= dst
;
671 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
676 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_YZ
), brw_imm_f(0));
677 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_XW
), brw_imm_f(1));
679 /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order
680 * to get all channels active inside the IF. In the clipping code
681 * we run with NoMask, so it's not an option and we can use
682 * BRW_EXECUTE_1 for all comparisions.
684 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,0), brw_imm_f(0));
685 if_insn
= brw_IF(p
, BRW_EXECUTE_8
);
687 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
,0));
689 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,1), brw_imm_f(0));
690 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_Z
), brw_swizzle1(arg0
,1));
691 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
694 BRW_MATH_FUNCTION_POW
,
695 brw_writemask(dst
, WRITEMASK_Z
),
696 brw_swizzle1(tmp
, 2),
697 brw_swizzle1(arg0
, 3),
698 BRW_MATH_PRECISION_PARTIAL
);
701 brw_ENDIF(p
, if_insn
);
706 static void emit_lrp_noalias(struct brw_vs_compile
*c
,
712 struct brw_compile
*p
= &c
->func
;
714 brw_ADD(p
, dst
, negate(arg0
), brw_imm_f(1.0));
715 brw_MUL(p
, brw_null_reg(), dst
, arg2
);
716 brw_MAC(p
, dst
, arg0
, arg1
);
719 /** 3 or 4-component vector normalization */
720 static void emit_nrm( struct brw_vs_compile
*c
,
725 struct brw_compile
*p
= &c
->func
;
726 struct brw_reg tmp
= get_tmp(c
);
728 /* tmp = dot(arg0, arg0) */
730 brw_DP3(p
, tmp
, arg0
, arg0
);
732 brw_DP4(p
, tmp
, arg0
, arg0
);
734 /* tmp = 1 / sqrt(tmp) */
735 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, tmp
, tmp
, BRW_MATH_PRECISION_FULL
);
737 /* dst = arg0 * tmp */
738 brw_MUL(p
, dst
, arg0
, tmp
);
744 static struct brw_reg
745 get_constant(struct brw_vs_compile
*c
,
746 const struct prog_instruction
*inst
,
749 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
750 struct brw_compile
*p
= &c
->func
;
751 struct brw_reg const_reg
;
752 struct brw_reg const2_reg
;
753 const GLboolean relAddr
= src
->RelAddr
;
755 assert(argIndex
< 3);
757 if (c
->current_const
[argIndex
].index
!= src
->Index
|| relAddr
) {
758 struct brw_reg addrReg
= c
->regs
[PROGRAM_ADDRESS
][0];
760 c
->current_const
[argIndex
].index
= src
->Index
;
763 printf(" fetch const[%d] for arg %d into reg %d\n",
764 src
->Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
766 /* need to fetch the constant now */
768 c
->current_const
[argIndex
].reg
,/* writeback dest */
770 relAddr
, /* relative indexing? */
771 addrReg
, /* address register */
772 16 * src
->Index
, /* byte offset */
773 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
778 const2_reg
= get_tmp(c
);
780 /* use upper half of address reg for second read */
781 addrReg
= stride(addrReg
, 0, 4, 0);
785 const2_reg
, /* writeback dest */
787 relAddr
, /* relative indexing? */
788 addrReg
, /* address register */
789 16 * src
->Index
, /* byte offset */
790 SURF_INDEX_VERT_CONST_BUFFER
795 const_reg
= c
->current_const
[argIndex
].reg
;
798 /* merge the two Owords into the constant register */
799 /* const_reg[7..4] = const2_reg[7..4] */
801 suboffset(stride(const_reg
, 0, 4, 1), 4),
802 suboffset(stride(const2_reg
, 0, 4, 1), 4));
803 release_tmp(c
, const2_reg
);
806 /* replicate lower four floats into upper half (to get XYZWXYZW) */
807 const_reg
= stride(const_reg
, 0, 4, 0);
816 /* TODO: relative addressing!
818 static struct brw_reg
get_reg( struct brw_vs_compile
*c
,
819 gl_register_file file
,
823 case PROGRAM_TEMPORARY
:
826 assert(c
->regs
[file
][index
].nr
!= 0);
827 return c
->regs
[file
][index
];
828 case PROGRAM_STATE_VAR
:
829 case PROGRAM_CONSTANT
:
830 case PROGRAM_UNIFORM
:
831 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
832 return c
->regs
[PROGRAM_STATE_VAR
][index
];
833 case PROGRAM_ADDRESS
:
835 return c
->regs
[file
][index
];
837 case PROGRAM_UNDEFINED
: /* undef values */
838 return brw_null_reg();
840 case PROGRAM_LOCAL_PARAM
:
841 case PROGRAM_ENV_PARAM
:
842 case PROGRAM_WRITE_ONLY
:
845 return brw_null_reg();
851 * Indirect addressing: get reg[[arg] + offset].
853 static struct brw_reg
deref( struct brw_vs_compile
*c
,
857 struct brw_compile
*p
= &c
->func
;
858 struct brw_reg tmp
= vec4(get_tmp(c
));
859 struct brw_reg addr_reg
= c
->regs
[PROGRAM_ADDRESS
][0];
860 struct brw_reg vp_address
= retype(vec1(addr_reg
), BRW_REGISTER_TYPE_UW
);
861 GLuint byte_offset
= arg
.nr
* 32 + arg
.subnr
+ offset
* 16;
862 struct brw_reg indirect
= brw_vec4_indirect(0,0);
865 brw_push_insn_state(p
);
866 brw_set_access_mode(p
, BRW_ALIGN_1
);
868 /* This is pretty clunky - load the address register twice and
869 * fetch each 4-dword value in turn. There must be a way to do
870 * this in a single pass, but I couldn't get it to work.
872 brw_ADD(p
, brw_address_reg(0), vp_address
, brw_imm_d(byte_offset
));
873 brw_MOV(p
, tmp
, indirect
);
875 brw_ADD(p
, brw_address_reg(0), suboffset(vp_address
, 8), brw_imm_d(byte_offset
));
876 brw_MOV(p
, suboffset(tmp
, 4), indirect
);
878 brw_pop_insn_state(p
);
881 /* NOTE: tmp not released */
887 * Get brw reg corresponding to the instruction's [argIndex] src reg.
888 * TODO: relative addressing!
890 static struct brw_reg
891 get_src_reg( struct brw_vs_compile
*c
,
892 const struct prog_instruction
*inst
,
895 const GLuint file
= inst
->SrcReg
[argIndex
].File
;
896 const GLint index
= inst
->SrcReg
[argIndex
].Index
;
897 const GLboolean relAddr
= inst
->SrcReg
[argIndex
].RelAddr
;
900 case PROGRAM_TEMPORARY
:
904 return deref(c
, c
->regs
[file
][0], index
);
907 assert(c
->regs
[file
][index
].nr
!= 0);
908 return c
->regs
[file
][index
];
911 case PROGRAM_STATE_VAR
:
912 case PROGRAM_CONSTANT
:
913 case PROGRAM_UNIFORM
:
914 case PROGRAM_ENV_PARAM
:
915 if (c
->vp
->use_const_buffer
) {
916 return get_constant(c
, inst
, argIndex
);
919 return deref(c
, c
->regs
[PROGRAM_STATE_VAR
][0], index
);
922 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
923 return c
->regs
[PROGRAM_STATE_VAR
][index
];
925 case PROGRAM_ADDRESS
:
927 return c
->regs
[file
][index
];
929 case PROGRAM_UNDEFINED
:
930 /* this is a normal case since we loop over all three src args */
931 return brw_null_reg();
933 case PROGRAM_LOCAL_PARAM
:
934 case PROGRAM_WRITE_ONLY
:
937 return brw_null_reg();
942 static void emit_arl( struct brw_vs_compile
*c
,
944 struct brw_reg arg0
)
946 struct brw_compile
*p
= &c
->func
;
947 struct brw_reg tmp
= dst
;
948 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
953 brw_RNDD(p
, tmp
, arg0
); /* tmp = round(arg0) */
954 brw_MUL(p
, dst
, tmp
, brw_imm_d(16)); /* dst = tmp * 16 */
962 * Return the brw reg for the given instruction's src argument.
963 * Will return mangled results for SWZ op. The emit_swz() function
964 * ignores this result and recalculates taking extended swizzles into
967 static struct brw_reg
get_arg( struct brw_vs_compile
*c
,
968 const struct prog_instruction
*inst
,
971 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
974 if (src
->File
== PROGRAM_UNDEFINED
)
975 return brw_null_reg();
977 reg
= get_src_reg(c
, inst
, argIndex
);
979 /* Convert 3-bit swizzle to 2-bit.
981 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(GET_SWZ(src
->Swizzle
, 0),
982 GET_SWZ(src
->Swizzle
, 1),
983 GET_SWZ(src
->Swizzle
, 2),
984 GET_SWZ(src
->Swizzle
, 3));
986 /* Note this is ok for non-swizzle instructions:
988 reg
.negate
= src
->Negate
? 1 : 0;
995 * Get brw register for the given program dest register.
997 static struct brw_reg
get_dst( struct brw_vs_compile
*c
,
998 struct prog_dst_register dst
)
1003 case PROGRAM_TEMPORARY
:
1004 case PROGRAM_OUTPUT
:
1005 assert(c
->regs
[dst
.File
][dst
.Index
].nr
!= 0);
1006 reg
= c
->regs
[dst
.File
][dst
.Index
];
1008 case PROGRAM_ADDRESS
:
1009 assert(dst
.Index
== 0);
1010 reg
= c
->regs
[dst
.File
][dst
.Index
];
1012 case PROGRAM_UNDEFINED
:
1013 /* we may hit this for OPCODE_END, OPCODE_KIL, etc */
1014 reg
= brw_null_reg();
1018 reg
= brw_null_reg();
1021 reg
.dw1
.bits
.writemask
= dst
.WriteMask
;
1027 static void emit_swz( struct brw_vs_compile
*c
,
1029 const struct prog_instruction
*inst
)
1031 const GLuint argIndex
= 0;
1032 const struct prog_src_register src
= inst
->SrcReg
[argIndex
];
1033 struct brw_compile
*p
= &c
->func
;
1034 GLuint zeros_mask
= 0;
1035 GLuint ones_mask
= 0;
1036 GLuint src_mask
= 0;
1038 GLboolean need_tmp
= (src
.Negate
&&
1039 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
1040 struct brw_reg tmp
= dst
;
1046 for (i
= 0; i
< 4; i
++) {
1047 if (dst
.dw1
.bits
.writemask
& (1<<i
)) {
1048 GLubyte s
= GET_SWZ(src
.Swizzle
, i
);
1067 /* Do src first, in case dst aliases src:
1070 struct brw_reg arg0
;
1072 arg0
= get_src_reg(c
, inst
, argIndex
);
1074 arg0
= brw_swizzle(arg0
,
1075 src_swz
[0], src_swz
[1],
1076 src_swz
[2], src_swz
[3]);
1078 brw_MOV(p
, brw_writemask(tmp
, src_mask
), arg0
);
1082 brw_MOV(p
, brw_writemask(tmp
, zeros_mask
), brw_imm_f(0));
1085 brw_MOV(p
, brw_writemask(tmp
, ones_mask
), brw_imm_f(1));
1088 brw_MOV(p
, brw_writemask(tmp
, src
.Negate
), negate(tmp
));
1091 brw_MOV(p
, dst
, tmp
);
1092 release_tmp(c
, tmp
);
1098 * Post-vertex-program processing. Send the results to the URB.
1100 static void emit_vertex_write( struct brw_vs_compile
*c
)
1102 struct brw_compile
*p
= &c
->func
;
1103 struct brw_reg m0
= brw_message_reg(0);
1104 struct brw_reg pos
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_HPOS
];
1107 GLuint len_vertext_header
= 2;
1109 if (c
->key
.copy_edgeflag
) {
1111 get_reg(c
, PROGRAM_OUTPUT
, VERT_RESULT_EDGE
),
1112 get_reg(c
, PROGRAM_INPUT
, VERT_ATTRIB_EDGEFLAG
));
1115 /* Build ndc coords */
1117 /* ndc = 1.0 / pos.w */
1118 emit_math1(c
, BRW_MATH_FUNCTION_INV
, ndc
, brw_swizzle1(pos
, 3), BRW_MATH_PRECISION_FULL
);
1119 /* ndc.xyz = pos * ndc */
1120 brw_MUL(p
, brw_writemask(ndc
, WRITEMASK_XYZ
), pos
, ndc
);
1122 /* Update the header for point size, user clipping flags, and -ve rhw
1125 if ((c
->prog_data
.outputs_written
& (1<<VERT_RESULT_PSIZ
)) ||
1126 c
->key
.nr_userclip
|| BRW_IS_965(p
->brw
))
1128 struct brw_reg header1
= retype(get_tmp(c
), BRW_REGISTER_TYPE_UD
);
1131 brw_MOV(p
, header1
, brw_imm_ud(0));
1133 brw_set_access_mode(p
, BRW_ALIGN_16
);
1135 if (c
->prog_data
.outputs_written
& (1<<VERT_RESULT_PSIZ
)) {
1136 struct brw_reg psiz
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_PSIZ
];
1137 brw_MUL(p
, brw_writemask(header1
, WRITEMASK_W
), brw_swizzle1(psiz
, 0), brw_imm_f(1<<11));
1138 brw_AND(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(0x7ff<<8));
1141 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1142 brw_set_conditionalmod(p
, BRW_CONDITIONAL_L
);
1143 brw_DP4(p
, brw_null_reg(), pos
, c
->userplane
[i
]);
1144 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<i
));
1145 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1148 /* i965 clipping workaround:
1149 * 1) Test for -ve rhw
1151 * set ndc = (0,0,0,0)
1154 * Later, clipping will detect ucp[6] and ensure the primitive is
1155 * clipped against all fixed planes.
1157 if (BRW_IS_965(p
->brw
)) {
1159 vec8(brw_null_reg()),
1161 brw_swizzle1(ndc
, 3),
1164 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1165 brw_MOV(p
, ndc
, brw_imm_f(0));
1166 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1169 brw_set_access_mode(p
, BRW_ALIGN_1
); /* why? */
1170 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), header1
);
1171 brw_set_access_mode(p
, BRW_ALIGN_16
);
1173 release_tmp(c
, header1
);
1176 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
1179 /* Emit the (interleaved) headers for the two vertices - an 8-reg
1180 * of zeros followed by two sets of NDC coordinates:
1182 brw_set_access_mode(p
, BRW_ALIGN_1
);
1183 brw_MOV(p
, offset(m0
, 2), ndc
);
1185 if (BRW_IS_IGDNG(p
->brw
)) {
1186 /* There are 20 DWs (D0-D19) in VUE vertex header on IGDNG */
1187 brw_MOV(p
, offset(m0
, 3), pos
); /* a portion of vertex header */
1188 /* m4, m5 contain the distances from vertex to the user clip planeXXX.
1189 * Seems it is useless for us.
1190 * m6 is used for aligning, so that the remainder of vertex element is
1193 brw_MOV(p
, offset(m0
, 7), pos
); /* the remainder of vertex element */
1194 len_vertext_header
= 6;
1196 brw_MOV(p
, offset(m0
, 3), pos
);
1197 len_vertext_header
= 2;
1200 eot
= (c
->first_overflow_output
== 0);
1203 brw_null_reg(), /* dest */
1204 0, /* starting mrf reg nr */
1208 MIN2(c
->nr_outputs
+ 1 + len_vertext_header
, (BRW_MAX_MRF
-1)), /* msg len */
1209 0, /* response len */
1211 eot
, /* writes complete */
1212 0, /* urb destination offset */
1213 BRW_URB_SWIZZLE_INTERLEAVE
);
1215 if (c
->first_overflow_output
> 0) {
1216 /* Not all of the vertex outputs/results fit into the MRF.
1217 * Move the overflowed attributes from the GRF to the MRF and
1218 * issue another brw_urb_WRITE().
1220 /* XXX I'm not 100% sure about which MRF regs to use here. Starting
1224 for (i
= c
->first_overflow_output
; i
< VERT_RESULT_MAX
; i
++) {
1225 if (c
->prog_data
.outputs_written
& (1 << i
)) {
1226 /* move from GRF to MRF */
1227 brw_MOV(p
, brw_message_reg(4+mrf
), c
->regs
[PROGRAM_OUTPUT
][i
]);
1233 brw_null_reg(), /* dest */
1234 4, /* starting mrf reg nr */
1238 mrf
+1, /* msg len */
1239 0, /* response len */
1241 1, /* writes complete */
1242 BRW_MAX_MRF
-1, /* urb destination offset */
1243 BRW_URB_SWIZZLE_INTERLEAVE
);
1249 * Called after code generation to resolve subroutine calls and the
1251 * \param end_inst points to brw code for END instruction
1252 * \param last_inst points to last instruction emitted before vertex write
1255 post_vs_emit( struct brw_vs_compile
*c
,
1256 struct brw_instruction
*end_inst
,
1257 struct brw_instruction
*last_inst
)
1261 brw_resolve_cals(&c
->func
);
1263 /* patch up the END code to jump past subroutines, etc */
1264 offset
= last_inst
- end_inst
;
1266 brw_set_src1(end_inst
, brw_imm_d(offset
* 16));
1268 end_inst
->header
.opcode
= BRW_OPCODE_NOP
;
1273 get_predicate(const struct prog_instruction
*inst
)
1275 if (inst
->DstReg
.CondMask
== COND_TR
)
1276 return BRW_PREDICATE_NONE
;
1278 /* All of GLSL only produces predicates for COND_NE and one channel per
1279 * vector. Fail badly if someone starts doing something else, as it might
1280 * mean infinite looping or something.
1282 * We'd like to support all the condition codes, but our hardware doesn't
1283 * quite match the Mesa IR, which is modeled after the NV extensions. For
1284 * those, the instruction may update the condition codes or not, then any
1285 * later instruction may use one of those condition codes. For gen4, the
1286 * instruction may update the flags register based on one of the condition
1287 * codes output by the instruction, and then further instructions may
1288 * predicate on that. We can probably support this, but it won't
1289 * necessarily be easy.
1291 assert(inst
->DstReg
.CondMask
== COND_NE
);
1293 switch (inst
->DstReg
.CondSwizzle
) {
1295 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1297 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1299 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1301 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1303 _mesa_problem(NULL
, "Unexpected predicate: 0x%08x\n",
1304 inst
->DstReg
.CondMask
);
1305 return BRW_PREDICATE_NORMAL
;
1309 /* Emit the vertex program instructions here.
1311 void brw_vs_emit(struct brw_vs_compile
*c
)
1313 #define MAX_IF_DEPTH 32
1314 #define MAX_LOOP_DEPTH 32
1315 struct brw_compile
*p
= &c
->func
;
1316 struct brw_context
*brw
= p
->brw
;
1317 const GLuint nr_insns
= c
->vp
->program
.Base
.NumInstructions
;
1318 GLuint insn
, if_depth
= 0, loop_depth
= 0;
1319 GLuint end_offset
= 0;
1320 struct brw_instruction
*end_inst
, *last_inst
;
1321 struct brw_instruction
*if_inst
[MAX_IF_DEPTH
], *loop_inst
[MAX_LOOP_DEPTH
];
1322 const struct brw_indirect stack_index
= brw_indirect(0, 0);
1326 if (INTEL_DEBUG
& DEBUG_VS
) {
1327 _mesa_printf("vs-mesa:\n");
1328 _mesa_print_program(&c
->vp
->program
.Base
);
1332 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1333 brw_set_access_mode(p
, BRW_ALIGN_16
);
1335 /* Message registers can't be read, so copy the output into GRF register
1336 if they are used in source registers */
1337 for (insn
= 0; insn
< nr_insns
; insn
++) {
1339 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1340 for (i
= 0; i
< 3; i
++) {
1341 struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1342 GLuint index
= src
->Index
;
1343 GLuint file
= src
->File
;
1344 if (file
== PROGRAM_OUTPUT
&& index
!= VERT_RESULT_HPOS
)
1345 c
->output_regs
[index
].used_in_src
= GL_TRUE
;
1349 /* Static register allocation
1351 brw_vs_alloc_regs(c
);
1352 brw_MOV(p
, get_addr_reg(stack_index
), brw_address(c
->stack
));
1354 for (insn
= 0; insn
< nr_insns
; insn
++) {
1356 const struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1357 struct brw_reg args
[3], dst
;
1361 printf("%d: ", insn
);
1362 _mesa_print_instruction(inst
);
1365 /* Get argument regs. SWZ is special and does this itself.
1367 if (inst
->Opcode
!= OPCODE_SWZ
)
1368 for (i
= 0; i
< 3; i
++) {
1369 const struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1372 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1373 args
[i
] = c
->output_regs
[index
].reg
;
1375 args
[i
] = get_arg(c
, inst
, i
);
1378 /* Get dest regs. Note that it is possible for a reg to be both
1379 * dst and arg, given the static allocation of registers. So
1380 * care needs to be taken emitting multi-operation instructions.
1382 index
= inst
->DstReg
.Index
;
1383 file
= inst
->DstReg
.File
;
1384 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1385 dst
= c
->output_regs
[index
].reg
;
1387 dst
= get_dst(c
, inst
->DstReg
);
1389 if (inst
->SaturateMode
!= SATURATE_OFF
) {
1390 _mesa_problem(NULL
, "Unsupported saturate %d in vertex shader",
1391 inst
->SaturateMode
);
1394 switch (inst
->Opcode
) {
1396 brw_MOV(p
, dst
, brw_abs(args
[0]));
1399 brw_ADD(p
, dst
, args
[0], args
[1]);
1402 emit_math1(c
, BRW_MATH_FUNCTION_COS
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1405 brw_DP3(p
, dst
, args
[0], args
[1]);
1408 brw_DP4(p
, dst
, args
[0], args
[1]);
1411 brw_DPH(p
, dst
, args
[0], args
[1]);
1414 emit_nrm(c
, dst
, args
[0], 3);
1417 emit_nrm(c
, dst
, args
[0], 4);
1420 unalias2(c
, dst
, args
[0], args
[1], emit_dst_noalias
);
1423 unalias1(c
, dst
, args
[0], emit_exp_noalias
);
1426 emit_math1(c
, BRW_MATH_FUNCTION_EXP
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1429 emit_arl(c
, dst
, args
[0]);
1432 brw_RNDD(p
, dst
, args
[0]);
1435 brw_FRC(p
, dst
, args
[0]);
1438 unalias1(c
, dst
, args
[0], emit_log_noalias
);
1441 emit_math1(c
, BRW_MATH_FUNCTION_LOG
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1444 unalias1(c
, dst
, args
[0], emit_lit_noalias
);
1447 unalias3(c
, dst
, args
[0], args
[1], args
[2], emit_lrp_noalias
);
1450 brw_MOV(p
, brw_acc_reg(), args
[2]);
1451 brw_MAC(p
, dst
, args
[0], args
[1]);
1454 emit_max(p
, dst
, args
[0], args
[1]);
1457 emit_min(p
, dst
, args
[0], args
[1]);
1460 brw_MOV(p
, dst
, args
[0]);
1463 brw_MUL(p
, dst
, args
[0], args
[1]);
1466 emit_math2(c
, BRW_MATH_FUNCTION_POW
, dst
, args
[0], args
[1], BRW_MATH_PRECISION_FULL
);
1469 emit_math1(c
, BRW_MATH_FUNCTION_INV
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1472 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1476 emit_seq(p
, dst
, args
[0], args
[1]);
1479 emit_math1(c
, BRW_MATH_FUNCTION_SIN
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1482 emit_sne(p
, dst
, args
[0], args
[1]);
1485 emit_sge(p
, dst
, args
[0], args
[1]);
1488 emit_sgt(p
, dst
, args
[0], args
[1]);
1491 emit_slt(p
, dst
, args
[0], args
[1]);
1494 emit_sle(p
, dst
, args
[0], args
[1]);
1497 brw_ADD(p
, dst
, args
[0], negate(args
[1]));
1500 /* The args[0] value can't be used here as it won't have
1501 * correctly encoded the full swizzle:
1503 emit_swz(c
, dst
, inst
);
1506 /* round toward zero */
1507 brw_RNDZ(p
, dst
, args
[0]);
1510 emit_xpd(p
, dst
, args
[0], args
[1]);
1513 assert(if_depth
< MAX_IF_DEPTH
);
1514 if_inst
[if_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1515 /* Note that brw_IF smashes the predicate_control field. */
1516 if_inst
[if_depth
]->header
.predicate_control
= get_predicate(inst
);
1520 if_inst
[if_depth
-1] = brw_ELSE(p
, if_inst
[if_depth
-1]);
1523 assert(if_depth
> 0);
1524 brw_ENDIF(p
, if_inst
[--if_depth
]);
1526 case OPCODE_BGNLOOP
:
1527 loop_inst
[loop_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
1530 brw_set_predicate_control(p
, get_predicate(inst
));
1532 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1535 brw_set_predicate_control(p
, get_predicate(inst
));
1537 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1539 case OPCODE_ENDLOOP
:
1541 struct brw_instruction
*inst0
, *inst1
;
1546 if (BRW_IS_IGDNG(brw
))
1549 inst0
= inst1
= brw_WHILE(p
, loop_inst
[loop_depth
]);
1550 /* patch all the BREAK/CONT instructions from last BEGINLOOP */
1551 while (inst0
> loop_inst
[loop_depth
]) {
1553 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
) {
1554 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
1555 inst0
->bits3
.if_else
.pop_count
= 0;
1557 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
) {
1558 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
1559 inst0
->bits3
.if_else
.pop_count
= 0;
1565 brw_set_predicate_control(p
, get_predicate(inst
));
1566 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1567 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1570 brw_set_access_mode(p
, BRW_ALIGN_1
);
1571 brw_ADD(p
, deref_1d(stack_index
, 0), brw_ip_reg(), brw_imm_d(3*16));
1572 brw_set_access_mode(p
, BRW_ALIGN_16
);
1573 brw_ADD(p
, get_addr_reg(stack_index
),
1574 get_addr_reg(stack_index
), brw_imm_d(4));
1575 brw_save_call(p
, inst
->Comment
, p
->nr_insn
);
1576 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1579 brw_ADD(p
, get_addr_reg(stack_index
),
1580 get_addr_reg(stack_index
), brw_imm_d(-4));
1581 brw_set_access_mode(p
, BRW_ALIGN_1
);
1582 brw_MOV(p
, brw_ip_reg(), deref_1d(stack_index
, 0));
1583 brw_set_access_mode(p
, BRW_ALIGN_16
);
1586 end_offset
= p
->nr_insn
;
1587 /* this instruction will get patched later to jump past subroutine
1590 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1596 brw_save_label(p
, inst
->Comment
, p
->nr_insn
);
1602 _mesa_problem(NULL
, "Unsupported opcode %i (%s) in vertex shader",
1603 inst
->Opcode
, inst
->Opcode
< MAX_OPCODE
?
1604 _mesa_opcode_string(inst
->Opcode
) :
1608 /* Set the predication update on the last instruction of the native
1609 * instruction sequence.
1611 * This would be problematic if it was set on a math instruction,
1612 * but that shouldn't be the case with the current GLSL compiler.
1614 if (inst
->CondUpdate
) {
1615 struct brw_instruction
*hw_insn
= &p
->store
[p
->nr_insn
- 1];
1617 assert(hw_insn
->header
.destreg__conditionalmod
== 0);
1618 hw_insn
->header
.destreg__conditionalmod
= BRW_CONDITIONAL_NZ
;
1621 if ((inst
->DstReg
.File
== PROGRAM_OUTPUT
)
1622 && (inst
->DstReg
.Index
!= VERT_RESULT_HPOS
)
1623 && c
->output_regs
[inst
->DstReg
.Index
].used_in_src
) {
1624 brw_MOV(p
, get_dst(c
, inst
->DstReg
), dst
);
1627 /* Result color clamping.
1629 * When destination register is an output register and
1630 * it's primary/secondary front/back color, we have to clamp
1631 * the result to [0,1]. This is done by enabling the
1632 * saturation bit for the last instruction.
1634 * We don't use brw_set_saturate() as it modifies
1635 * p->current->header.saturate, which affects all the subsequent
1636 * instructions. Instead, we directly modify the header
1637 * of the last (already stored) instruction.
1639 if (inst
->DstReg
.File
== PROGRAM_OUTPUT
) {
1640 if ((inst
->DstReg
.Index
== VERT_RESULT_COL0
)
1641 || (inst
->DstReg
.Index
== VERT_RESULT_COL1
)
1642 || (inst
->DstReg
.Index
== VERT_RESULT_BFC0
)
1643 || (inst
->DstReg
.Index
== VERT_RESULT_BFC1
)) {
1644 p
->store
[p
->nr_insn
-1].header
.saturate
= 1;
1651 end_inst
= &p
->store
[end_offset
];
1652 last_inst
= &p
->store
[p
->nr_insn
];
1654 /* The END instruction will be patched to jump to this code */
1655 emit_vertex_write(c
);
1657 post_vs_emit(c
, end_inst
, last_inst
);
1659 if (INTEL_DEBUG
& DEBUG_VS
) {
1662 _mesa_printf("vs-native:\n");
1663 for (i
= 0; i
< p
->nr_insn
; i
++)
1664 brw_disasm(stderr
, &p
->store
[i
]);