2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/macros.h"
34 #include "shader/program.h"
35 #include "shader/prog_parameter.h"
36 #include "shader/prog_print.h"
37 #include "brw_context.h"
41 static struct brw_reg
get_tmp( struct brw_vs_compile
*c
)
43 struct brw_reg tmp
= brw_vec8_grf(c
->last_tmp
, 0);
45 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
46 c
->prog_data
.total_grf
= c
->last_tmp
;
51 static void release_tmp( struct brw_vs_compile
*c
, struct brw_reg tmp
)
53 if (tmp
.nr
== c
->last_tmp
-1)
57 static void release_tmps( struct brw_vs_compile
*c
)
59 c
->last_tmp
= c
->first_tmp
;
64 * Preallocate GRF register before code emit.
65 * Do things as simply as possible. Allocate and populate all regs
68 static void brw_vs_alloc_regs( struct brw_vs_compile
*c
)
70 struct intel_context
*intel
= &c
->func
.brw
->intel
;
71 GLuint i
, reg
= 0, mrf
;
72 int attributes_in_vue
;
74 /* Determine whether to use a real constant buffer or use a block
75 * of GRF registers for constants. The later is faster but only
76 * works if everything fits in the GRF.
77 * XXX this heuristic/check may need some fine tuning...
79 if (c
->vp
->program
.Base
.Parameters
->NumParameters
+
80 c
->vp
->program
.Base
.NumTemporaries
+ 20 > BRW_MAX_GRF
)
81 c
->vp
->use_const_buffer
= GL_TRUE
;
83 c
->vp
->use_const_buffer
= GL_FALSE
;
85 /*printf("use_const_buffer = %d\n", c->vp->use_const_buffer);*/
87 /* r0 -- reserved as usual
89 c
->r0
= brw_vec8_grf(reg
, 0);
92 /* User clip planes from curbe:
94 if (c
->key
.nr_userclip
) {
95 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
96 c
->userplane
[i
] = stride( brw_vec4_grf(reg
+3+i
/2, (i
%2) * 4), 0, 4, 1);
99 /* Deal with curbe alignment:
101 reg
+= ((6 + c
->key
.nr_userclip
+ 3) / 4) * 2;
104 /* Vertex program parameters from curbe:
106 if (c
->vp
->use_const_buffer
) {
107 /* get constants from a real constant buffer */
108 c
->prog_data
.curb_read_length
= 0;
109 c
->prog_data
.nr_params
= 4; /* XXX 0 causes a bug elsewhere... */
112 /* use a section of the GRF for constants */
113 GLuint nr_params
= c
->vp
->program
.Base
.Parameters
->NumParameters
;
114 for (i
= 0; i
< nr_params
; i
++) {
115 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2, (i
%2) * 4), 0, 4, 1);
117 reg
+= (nr_params
+ 1) / 2;
118 c
->prog_data
.curb_read_length
= reg
- 1;
120 c
->prog_data
.nr_params
= nr_params
* 4;
123 /* Allocate input regs:
126 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
127 if (c
->prog_data
.inputs_read
& (1 << i
)) {
129 c
->regs
[PROGRAM_INPUT
][i
] = brw_vec8_grf(reg
, 0);
133 /* If there are no inputs, we'll still be reading one attribute's worth
134 * because it's required -- see urb_read_length setting.
136 if (c
->nr_inputs
== 0)
139 /* Allocate outputs. The non-position outputs go straight into message regs.
142 c
->first_output
= reg
;
143 c
->first_overflow_output
= 0;
145 if (intel
->is_ironlake
)
150 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
151 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(i
)) {
153 assert(i
< Elements(c
->regs
[PROGRAM_OUTPUT
]));
154 if (i
== VERT_RESULT_HPOS
) {
155 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
158 else if (i
== VERT_RESULT_PSIZ
) {
159 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
161 mrf
++; /* just a placeholder? XXX fix later stages & remove this */
165 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_message_reg(mrf
);
169 /* too many vertex results to fit in MRF, use GRF for overflow */
170 if (!c
->first_overflow_output
)
171 c
->first_overflow_output
= i
;
172 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
179 /* Allocate program temporaries:
181 for (i
= 0; i
< c
->vp
->program
.Base
.NumTemporaries
; i
++) {
182 c
->regs
[PROGRAM_TEMPORARY
][i
] = brw_vec8_grf(reg
, 0);
186 /* Address reg(s). Don't try to use the internal address reg until
189 for (i
= 0; i
< c
->vp
->program
.Base
.NumAddressRegs
; i
++) {
190 c
->regs
[PROGRAM_ADDRESS
][i
] = brw_reg(BRW_GENERAL_REGISTER_FILE
,
194 BRW_VERTICAL_STRIDE_8
,
196 BRW_HORIZONTAL_STRIDE_1
,
202 if (c
->vp
->use_const_buffer
) {
203 for (i
= 0; i
< 3; i
++) {
204 c
->current_const
[i
].index
= -1;
205 c
->current_const
[i
].reg
= brw_vec8_grf(reg
, 0);
210 for (i
= 0; i
< 128; i
++) {
211 if (c
->output_regs
[i
].used_in_src
) {
212 c
->output_regs
[i
].reg
= brw_vec8_grf(reg
, 0);
217 c
->stack
= brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, reg
, 0);
220 /* Some opcodes need an internal temporary:
223 c
->last_tmp
= reg
; /* for allocation purposes */
225 /* Each input reg holds data from two vertices. The
226 * urb_read_length is the number of registers read from *each*
227 * vertex urb, so is half the amount:
229 c
->prog_data
.urb_read_length
= (c
->nr_inputs
+ 1) / 2;
230 /* Setting this field to 0 leads to undefined behavior according to the
231 * the VS_STATE docs. Our VUEs will always have at least one attribute
232 * sitting in them, even if it's padding.
234 if (c
->prog_data
.urb_read_length
== 0)
235 c
->prog_data
.urb_read_length
= 1;
237 /* The VS VUEs are shared by VF (outputting our inputs) and VS, so size
238 * them to fit the biggest thing they need to.
240 attributes_in_vue
= MAX2(c
->nr_outputs
, c
->nr_inputs
);
242 if (intel
->is_ironlake
)
243 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 6 + 3) / 4;
245 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 2 + 3) / 4;
247 c
->prog_data
.total_grf
= reg
;
249 if (INTEL_DEBUG
& DEBUG_VS
) {
250 _mesa_printf("%s NumAddrRegs %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumAddressRegs
);
251 _mesa_printf("%s NumTemps %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumTemporaries
);
252 _mesa_printf("%s reg = %d\n", __FUNCTION__
, reg
);
258 * If an instruction uses a temp reg both as a src and the dest, we
259 * sometimes need to allocate an intermediate temporary.
261 static void unalias1( struct brw_vs_compile
*c
,
264 void (*func
)( struct brw_vs_compile
*,
268 if (dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) {
269 struct brw_compile
*p
= &c
->func
;
270 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
272 brw_MOV(p
, dst
, tmp
);
282 * Checkes if 2-operand instruction needs an intermediate temporary.
284 static void unalias2( struct brw_vs_compile
*c
,
288 void (*func
)( struct brw_vs_compile
*,
293 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
294 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
)) {
295 struct brw_compile
*p
= &c
->func
;
296 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
297 func(c
, tmp
, arg0
, arg1
);
298 brw_MOV(p
, dst
, tmp
);
302 func(c
, dst
, arg0
, arg1
);
308 * Checkes if 3-operand instruction needs an intermediate temporary.
310 static void unalias3( struct brw_vs_compile
*c
,
315 void (*func
)( struct brw_vs_compile
*,
321 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
322 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
) ||
323 (dst
.file
== arg2
.file
&& dst
.nr
== arg2
.nr
)) {
324 struct brw_compile
*p
= &c
->func
;
325 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
326 func(c
, tmp
, arg0
, arg1
, arg2
);
327 brw_MOV(p
, dst
, tmp
);
331 func(c
, dst
, arg0
, arg1
, arg2
);
335 static void emit_sop( struct brw_vs_compile
*c
,
341 struct brw_compile
*p
= &c
->func
;
343 brw_MOV(p
, dst
, brw_imm_f(0.0f
));
344 brw_CMP(p
, brw_null_reg(), cond
, arg0
, arg1
);
345 brw_MOV(p
, dst
, brw_imm_f(1.0f
));
346 brw_set_predicate_control_flag_value(p
, 0xff);
349 static void emit_seq( struct brw_vs_compile
*c
,
352 struct brw_reg arg1
)
354 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_EQ
);
357 static void emit_sne( struct brw_vs_compile
*c
,
360 struct brw_reg arg1
)
362 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_NEQ
);
364 static void emit_slt( struct brw_vs_compile
*c
,
367 struct brw_reg arg1
)
369 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_L
);
372 static void emit_sle( struct brw_vs_compile
*c
,
375 struct brw_reg arg1
)
377 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_LE
);
380 static void emit_sgt( struct brw_vs_compile
*c
,
383 struct brw_reg arg1
)
385 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_G
);
388 static void emit_sge( struct brw_vs_compile
*c
,
391 struct brw_reg arg1
)
393 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_GE
);
396 static void emit_cmp( struct brw_compile
*p
,
400 struct brw_reg arg2
)
402 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, brw_imm_f(0));
403 brw_SEL(p
, dst
, arg1
, arg2
);
404 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
407 static void emit_max( struct brw_compile
*p
,
410 struct brw_reg arg1
)
412 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
413 brw_SEL(p
, dst
, arg1
, arg0
);
414 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
417 static void emit_min( struct brw_compile
*p
,
420 struct brw_reg arg1
)
422 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
423 brw_SEL(p
, dst
, arg0
, arg1
);
424 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
428 static void emit_math1( struct brw_vs_compile
*c
,
434 /* There are various odd behaviours with SEND on the simulator. In
435 * addition there are documented issues with the fact that the GEN4
436 * processor doesn't do dependency control properly on SEND
437 * results. So, on balance, this kludge to get around failures
438 * with writemasked math results looks like it might be necessary
439 * whether that turns out to be a simulator bug or not:
441 struct brw_compile
*p
= &c
->func
;
442 struct brw_reg tmp
= dst
;
443 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
444 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
452 BRW_MATH_SATURATE_NONE
,
455 BRW_MATH_DATA_SCALAR
,
459 brw_MOV(p
, dst
, tmp
);
465 static void emit_math2( struct brw_vs_compile
*c
,
472 struct brw_compile
*p
= &c
->func
;
473 struct brw_reg tmp
= dst
;
474 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
475 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
480 brw_MOV(p
, brw_message_reg(3), arg1
);
485 BRW_MATH_SATURATE_NONE
,
488 BRW_MATH_DATA_SCALAR
,
492 brw_MOV(p
, dst
, tmp
);
498 static void emit_exp_noalias( struct brw_vs_compile
*c
,
500 struct brw_reg arg0
)
502 struct brw_compile
*p
= &c
->func
;
505 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
) {
506 struct brw_reg tmp
= get_tmp(c
);
507 struct brw_reg tmp_d
= retype(tmp
, BRW_REGISTER_TYPE_D
);
509 /* tmp_d = floor(arg0.x) */
510 brw_RNDD(p
, tmp_d
, brw_swizzle1(arg0
, 0));
512 /* result[0] = 2.0 ^ tmp */
514 /* Adjust exponent for floating point:
517 brw_ADD(p
, brw_writemask(tmp_d
, WRITEMASK_X
), tmp_d
, brw_imm_d(127));
519 /* Install exponent and sign.
520 * Excess drops off the edge:
522 brw_SHL(p
, brw_writemask(retype(dst
, BRW_REGISTER_TYPE_D
), WRITEMASK_X
),
523 tmp_d
, brw_imm_d(23));
528 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
) {
529 /* result[1] = arg0.x - floor(arg0.x) */
530 brw_FRC(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
, 0));
533 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
534 /* As with the LOG instruction, we might be better off just
535 * doing a taylor expansion here, seeing as we have to do all
538 * If mathbox partial precision is too low, consider also:
539 * result[3] = result[0] * EXP(result[1])
542 BRW_MATH_FUNCTION_EXP
,
543 brw_writemask(dst
, WRITEMASK_Z
),
544 brw_swizzle1(arg0
, 0),
545 BRW_MATH_PRECISION_FULL
);
548 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
549 /* result[3] = 1.0; */
550 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), brw_imm_f(1));
555 static void emit_log_noalias( struct brw_vs_compile
*c
,
557 struct brw_reg arg0
)
559 struct brw_compile
*p
= &c
->func
;
560 struct brw_reg tmp
= dst
;
561 struct brw_reg tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
562 struct brw_reg arg0_ud
= retype(arg0
, BRW_REGISTER_TYPE_UD
);
563 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
564 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
568 tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
571 /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt
574 * These almost look likey they could be joined up, but not really
577 * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127
578 * result[1].i = (x.i & ((1<<23)-1) + (127<<23)
580 if (dst
.dw1
.bits
.writemask
& WRITEMASK_XZ
) {
582 brw_writemask(tmp_ud
, WRITEMASK_X
),
583 brw_swizzle1(arg0_ud
, 0),
584 brw_imm_ud((1U<<31)-1));
587 brw_writemask(tmp_ud
, WRITEMASK_X
),
592 brw_writemask(tmp
, WRITEMASK_X
),
593 retype(tmp_ud
, BRW_REGISTER_TYPE_D
), /* does it matter? */
597 if (dst
.dw1
.bits
.writemask
& WRITEMASK_YZ
) {
599 brw_writemask(tmp_ud
, WRITEMASK_Y
),
600 brw_swizzle1(arg0_ud
, 0),
601 brw_imm_ud((1<<23)-1));
604 brw_writemask(tmp_ud
, WRITEMASK_Y
),
606 brw_imm_ud(127<<23));
609 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
610 /* result[2] = result[0] + LOG2(result[1]); */
612 /* Why bother? The above is just a hint how to do this with a
613 * taylor series. Maybe we *should* use a taylor series as by
614 * the time all the above has been done it's almost certainly
615 * quicker than calling the mathbox, even with low precision.
618 * - result[0] + mathbox.LOG2(result[1])
619 * - mathbox.LOG2(arg0.x)
620 * - result[0] + inline_taylor_approx(result[1])
623 BRW_MATH_FUNCTION_LOG
,
624 brw_writemask(tmp
, WRITEMASK_Z
),
625 brw_swizzle1(tmp
, 1),
626 BRW_MATH_PRECISION_FULL
);
629 brw_writemask(tmp
, WRITEMASK_Z
),
630 brw_swizzle1(tmp
, 2),
631 brw_swizzle1(tmp
, 0));
634 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
635 /* result[3] = 1.0; */
636 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_W
), brw_imm_f(1));
640 brw_MOV(p
, dst
, tmp
);
646 /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
648 static void emit_dst_noalias( struct brw_vs_compile
*c
,
653 struct brw_compile
*p
= &c
->func
;
655 /* There must be a better way to do this:
657 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
)
658 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_X
), brw_imm_f(1.0));
659 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
)
660 brw_MUL(p
, brw_writemask(dst
, WRITEMASK_Y
), arg0
, arg1
);
661 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
)
662 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Z
), arg0
);
663 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
)
664 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), arg1
);
668 static void emit_xpd( struct brw_compile
*p
,
673 brw_MUL(p
, brw_null_reg(), brw_swizzle(t
, 1,2,0,3), brw_swizzle(u
,2,0,1,3));
674 brw_MAC(p
, dst
, negate(brw_swizzle(t
, 2,0,1,3)), brw_swizzle(u
,1,2,0,3));
678 static void emit_lit_noalias( struct brw_vs_compile
*c
,
680 struct brw_reg arg0
)
682 struct brw_compile
*p
= &c
->func
;
683 struct brw_instruction
*if_insn
;
684 struct brw_reg tmp
= dst
;
685 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
690 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_YZ
), brw_imm_f(0));
691 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_XW
), brw_imm_f(1));
693 /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order
694 * to get all channels active inside the IF. In the clipping code
695 * we run with NoMask, so it's not an option and we can use
696 * BRW_EXECUTE_1 for all comparisions.
698 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,0), brw_imm_f(0));
699 if_insn
= brw_IF(p
, BRW_EXECUTE_8
);
701 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
,0));
703 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,1), brw_imm_f(0));
704 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_Z
), brw_swizzle1(arg0
,1));
705 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
708 BRW_MATH_FUNCTION_POW
,
709 brw_writemask(dst
, WRITEMASK_Z
),
710 brw_swizzle1(tmp
, 2),
711 brw_swizzle1(arg0
, 3),
712 BRW_MATH_PRECISION_PARTIAL
);
715 brw_ENDIF(p
, if_insn
);
720 static void emit_lrp_noalias(struct brw_vs_compile
*c
,
726 struct brw_compile
*p
= &c
->func
;
728 brw_ADD(p
, dst
, negate(arg0
), brw_imm_f(1.0));
729 brw_MUL(p
, brw_null_reg(), dst
, arg2
);
730 brw_MAC(p
, dst
, arg0
, arg1
);
733 /** 3 or 4-component vector normalization */
734 static void emit_nrm( struct brw_vs_compile
*c
,
739 struct brw_compile
*p
= &c
->func
;
740 struct brw_reg tmp
= get_tmp(c
);
742 /* tmp = dot(arg0, arg0) */
744 brw_DP3(p
, tmp
, arg0
, arg0
);
746 brw_DP4(p
, tmp
, arg0
, arg0
);
748 /* tmp = 1 / sqrt(tmp) */
749 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, tmp
, tmp
, BRW_MATH_PRECISION_FULL
);
751 /* dst = arg0 * tmp */
752 brw_MUL(p
, dst
, arg0
, tmp
);
758 static struct brw_reg
759 get_constant(struct brw_vs_compile
*c
,
760 const struct prog_instruction
*inst
,
763 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
764 struct brw_compile
*p
= &c
->func
;
765 struct brw_reg const_reg
;
766 struct brw_reg const2_reg
;
767 const GLboolean relAddr
= src
->RelAddr
;
769 assert(argIndex
< 3);
771 if (c
->current_const
[argIndex
].index
!= src
->Index
|| relAddr
) {
772 struct brw_reg addrReg
= c
->regs
[PROGRAM_ADDRESS
][0];
774 c
->current_const
[argIndex
].index
= src
->Index
;
777 printf(" fetch const[%d] for arg %d into reg %d\n",
778 src
->Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
780 /* need to fetch the constant now */
782 c
->current_const
[argIndex
].reg
,/* writeback dest */
784 relAddr
, /* relative indexing? */
785 addrReg
, /* address register */
786 16 * src
->Index
, /* byte offset */
787 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
792 const2_reg
= get_tmp(c
);
794 /* use upper half of address reg for second read */
795 addrReg
= stride(addrReg
, 0, 4, 0);
799 const2_reg
, /* writeback dest */
801 relAddr
, /* relative indexing? */
802 addrReg
, /* address register */
803 16 * src
->Index
, /* byte offset */
804 SURF_INDEX_VERT_CONST_BUFFER
809 const_reg
= c
->current_const
[argIndex
].reg
;
812 /* merge the two Owords into the constant register */
813 /* const_reg[7..4] = const2_reg[7..4] */
815 suboffset(stride(const_reg
, 0, 4, 1), 4),
816 suboffset(stride(const2_reg
, 0, 4, 1), 4));
817 release_tmp(c
, const2_reg
);
820 /* replicate lower four floats into upper half (to get XYZWXYZW) */
821 const_reg
= stride(const_reg
, 0, 4, 0);
830 /* TODO: relative addressing!
832 static struct brw_reg
get_reg( struct brw_vs_compile
*c
,
833 gl_register_file file
,
837 case PROGRAM_TEMPORARY
:
840 assert(c
->regs
[file
][index
].nr
!= 0);
841 return c
->regs
[file
][index
];
842 case PROGRAM_STATE_VAR
:
843 case PROGRAM_CONSTANT
:
844 case PROGRAM_UNIFORM
:
845 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
846 return c
->regs
[PROGRAM_STATE_VAR
][index
];
847 case PROGRAM_ADDRESS
:
849 return c
->regs
[file
][index
];
851 case PROGRAM_UNDEFINED
: /* undef values */
852 return brw_null_reg();
854 case PROGRAM_LOCAL_PARAM
:
855 case PROGRAM_ENV_PARAM
:
856 case PROGRAM_WRITE_ONLY
:
859 return brw_null_reg();
865 * Indirect addressing: get reg[[arg] + offset].
867 static struct brw_reg
deref( struct brw_vs_compile
*c
,
871 struct brw_compile
*p
= &c
->func
;
872 struct brw_reg tmp
= vec4(get_tmp(c
));
873 struct brw_reg addr_reg
= c
->regs
[PROGRAM_ADDRESS
][0];
874 struct brw_reg vp_address
= retype(vec1(addr_reg
), BRW_REGISTER_TYPE_UW
);
875 GLuint byte_offset
= arg
.nr
* 32 + arg
.subnr
+ offset
* 16;
876 struct brw_reg indirect
= brw_vec4_indirect(0,0);
879 brw_push_insn_state(p
);
880 brw_set_access_mode(p
, BRW_ALIGN_1
);
882 /* This is pretty clunky - load the address register twice and
883 * fetch each 4-dword value in turn. There must be a way to do
884 * this in a single pass, but I couldn't get it to work.
886 brw_ADD(p
, brw_address_reg(0), vp_address
, brw_imm_d(byte_offset
));
887 brw_MOV(p
, tmp
, indirect
);
889 brw_ADD(p
, brw_address_reg(0), suboffset(vp_address
, 8), brw_imm_d(byte_offset
));
890 brw_MOV(p
, suboffset(tmp
, 4), indirect
);
892 brw_pop_insn_state(p
);
895 /* NOTE: tmp not released */
901 * Get brw reg corresponding to the instruction's [argIndex] src reg.
902 * TODO: relative addressing!
904 static struct brw_reg
905 get_src_reg( struct brw_vs_compile
*c
,
906 const struct prog_instruction
*inst
,
909 const GLuint file
= inst
->SrcReg
[argIndex
].File
;
910 const GLint index
= inst
->SrcReg
[argIndex
].Index
;
911 const GLboolean relAddr
= inst
->SrcReg
[argIndex
].RelAddr
;
914 case PROGRAM_TEMPORARY
:
918 return deref(c
, c
->regs
[file
][0], index
);
921 assert(c
->regs
[file
][index
].nr
!= 0);
922 return c
->regs
[file
][index
];
925 case PROGRAM_STATE_VAR
:
926 case PROGRAM_CONSTANT
:
927 case PROGRAM_UNIFORM
:
928 case PROGRAM_ENV_PARAM
:
929 case PROGRAM_LOCAL_PARAM
:
930 if (c
->vp
->use_const_buffer
) {
931 return get_constant(c
, inst
, argIndex
);
934 return deref(c
, c
->regs
[PROGRAM_STATE_VAR
][0], index
);
937 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
938 return c
->regs
[PROGRAM_STATE_VAR
][index
];
940 case PROGRAM_ADDRESS
:
942 return c
->regs
[file
][index
];
944 case PROGRAM_UNDEFINED
:
945 /* this is a normal case since we loop over all three src args */
946 return brw_null_reg();
948 case PROGRAM_WRITE_ONLY
:
951 return brw_null_reg();
956 static void emit_arl( struct brw_vs_compile
*c
,
958 struct brw_reg arg0
)
960 struct brw_compile
*p
= &c
->func
;
961 struct brw_reg tmp
= dst
;
962 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
967 brw_RNDD(p
, tmp
, arg0
); /* tmp = round(arg0) */
968 brw_MUL(p
, dst
, tmp
, brw_imm_d(16)); /* dst = tmp * 16 */
976 * Return the brw reg for the given instruction's src argument.
977 * Will return mangled results for SWZ op. The emit_swz() function
978 * ignores this result and recalculates taking extended swizzles into
981 static struct brw_reg
get_arg( struct brw_vs_compile
*c
,
982 const struct prog_instruction
*inst
,
985 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
988 if (src
->File
== PROGRAM_UNDEFINED
)
989 return brw_null_reg();
991 reg
= get_src_reg(c
, inst
, argIndex
);
993 /* Convert 3-bit swizzle to 2-bit.
995 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(GET_SWZ(src
->Swizzle
, 0),
996 GET_SWZ(src
->Swizzle
, 1),
997 GET_SWZ(src
->Swizzle
, 2),
998 GET_SWZ(src
->Swizzle
, 3));
1000 /* Note this is ok for non-swizzle instructions:
1002 reg
.negate
= src
->Negate
? 1 : 0;
1009 * Get brw register for the given program dest register.
1011 static struct brw_reg
get_dst( struct brw_vs_compile
*c
,
1012 struct prog_dst_register dst
)
1017 case PROGRAM_TEMPORARY
:
1018 case PROGRAM_OUTPUT
:
1019 assert(c
->regs
[dst
.File
][dst
.Index
].nr
!= 0);
1020 reg
= c
->regs
[dst
.File
][dst
.Index
];
1022 case PROGRAM_ADDRESS
:
1023 assert(dst
.Index
== 0);
1024 reg
= c
->regs
[dst
.File
][dst
.Index
];
1026 case PROGRAM_UNDEFINED
:
1027 /* we may hit this for OPCODE_END, OPCODE_KIL, etc */
1028 reg
= brw_null_reg();
1032 reg
= brw_null_reg();
1035 reg
.dw1
.bits
.writemask
= dst
.WriteMask
;
1041 static void emit_swz( struct brw_vs_compile
*c
,
1043 const struct prog_instruction
*inst
)
1045 const GLuint argIndex
= 0;
1046 const struct prog_src_register src
= inst
->SrcReg
[argIndex
];
1047 struct brw_compile
*p
= &c
->func
;
1048 GLuint zeros_mask
= 0;
1049 GLuint ones_mask
= 0;
1050 GLuint src_mask
= 0;
1052 GLboolean need_tmp
= (src
.Negate
&&
1053 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
1054 struct brw_reg tmp
= dst
;
1060 for (i
= 0; i
< 4; i
++) {
1061 if (dst
.dw1
.bits
.writemask
& (1<<i
)) {
1062 GLubyte s
= GET_SWZ(src
.Swizzle
, i
);
1081 /* Do src first, in case dst aliases src:
1084 struct brw_reg arg0
;
1086 arg0
= get_src_reg(c
, inst
, argIndex
);
1088 arg0
= brw_swizzle(arg0
,
1089 src_swz
[0], src_swz
[1],
1090 src_swz
[2], src_swz
[3]);
1092 brw_MOV(p
, brw_writemask(tmp
, src_mask
), arg0
);
1096 brw_MOV(p
, brw_writemask(tmp
, zeros_mask
), brw_imm_f(0));
1099 brw_MOV(p
, brw_writemask(tmp
, ones_mask
), brw_imm_f(1));
1102 brw_MOV(p
, brw_writemask(tmp
, src
.Negate
), negate(tmp
));
1105 brw_MOV(p
, dst
, tmp
);
1106 release_tmp(c
, tmp
);
1112 * Post-vertex-program processing. Send the results to the URB.
1114 static void emit_vertex_write( struct brw_vs_compile
*c
)
1116 struct brw_compile
*p
= &c
->func
;
1117 struct intel_context
*intel
= &p
->brw
->intel
;
1118 struct brw_reg m0
= brw_message_reg(0);
1119 struct brw_reg pos
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_HPOS
];
1122 GLuint len_vertext_header
= 2;
1124 if (c
->key
.copy_edgeflag
) {
1126 get_reg(c
, PROGRAM_OUTPUT
, VERT_RESULT_EDGE
),
1127 get_reg(c
, PROGRAM_INPUT
, VERT_ATTRIB_EDGEFLAG
));
1130 /* Build ndc coords */
1132 /* ndc = 1.0 / pos.w */
1133 emit_math1(c
, BRW_MATH_FUNCTION_INV
, ndc
, brw_swizzle1(pos
, 3), BRW_MATH_PRECISION_FULL
);
1134 /* ndc.xyz = pos * ndc */
1135 brw_MUL(p
, brw_writemask(ndc
, WRITEMASK_XYZ
), pos
, ndc
);
1137 /* Update the header for point size, user clipping flags, and -ve rhw
1140 if ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
1141 c
->key
.nr_userclip
|| BRW_IS_965(p
->brw
))
1143 struct brw_reg header1
= retype(get_tmp(c
), BRW_REGISTER_TYPE_UD
);
1146 brw_MOV(p
, header1
, brw_imm_ud(0));
1148 brw_set_access_mode(p
, BRW_ALIGN_16
);
1150 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1151 struct brw_reg psiz
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_PSIZ
];
1152 brw_MUL(p
, brw_writemask(header1
, WRITEMASK_W
), brw_swizzle1(psiz
, 0), brw_imm_f(1<<11));
1153 brw_AND(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(0x7ff<<8));
1156 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1157 brw_set_conditionalmod(p
, BRW_CONDITIONAL_L
);
1158 brw_DP4(p
, brw_null_reg(), pos
, c
->userplane
[i
]);
1159 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<i
));
1160 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1163 /* i965 clipping workaround:
1164 * 1) Test for -ve rhw
1166 * set ndc = (0,0,0,0)
1169 * Later, clipping will detect ucp[6] and ensure the primitive is
1170 * clipped against all fixed planes.
1172 if (BRW_IS_965(p
->brw
)) {
1174 vec8(brw_null_reg()),
1176 brw_swizzle1(ndc
, 3),
1179 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1180 brw_MOV(p
, ndc
, brw_imm_f(0));
1181 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1184 brw_set_access_mode(p
, BRW_ALIGN_1
); /* why? */
1185 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), header1
);
1186 brw_set_access_mode(p
, BRW_ALIGN_16
);
1188 release_tmp(c
, header1
);
1191 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
1194 /* Emit the (interleaved) headers for the two vertices - an 8-reg
1195 * of zeros followed by two sets of NDC coordinates:
1197 brw_set_access_mode(p
, BRW_ALIGN_1
);
1198 brw_MOV(p
, offset(m0
, 2), ndc
);
1200 if (intel
->is_ironlake
) {
1201 /* There are 20 DWs (D0-D19) in VUE vertex header on Ironlake */
1202 brw_MOV(p
, offset(m0
, 3), pos
); /* a portion of vertex header */
1203 /* m4, m5 contain the distances from vertex to the user clip planeXXX.
1204 * Seems it is useless for us.
1205 * m6 is used for aligning, so that the remainder of vertex element is
1208 brw_MOV(p
, offset(m0
, 7), pos
); /* the remainder of vertex element */
1209 len_vertext_header
= 6;
1211 brw_MOV(p
, offset(m0
, 3), pos
);
1212 len_vertext_header
= 2;
1215 eot
= (c
->first_overflow_output
== 0);
1218 brw_null_reg(), /* dest */
1219 0, /* starting mrf reg nr */
1223 MIN2(c
->nr_outputs
+ 1 + len_vertext_header
, (BRW_MAX_MRF
-1)), /* msg len */
1224 0, /* response len */
1226 eot
, /* writes complete */
1227 0, /* urb destination offset */
1228 BRW_URB_SWIZZLE_INTERLEAVE
);
1230 if (c
->first_overflow_output
> 0) {
1231 /* Not all of the vertex outputs/results fit into the MRF.
1232 * Move the overflowed attributes from the GRF to the MRF and
1233 * issue another brw_urb_WRITE().
1235 /* XXX I'm not 100% sure about which MRF regs to use here. Starting
1239 for (i
= c
->first_overflow_output
; i
< VERT_RESULT_MAX
; i
++) {
1240 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(i
)) {
1241 /* move from GRF to MRF */
1242 brw_MOV(p
, brw_message_reg(4+mrf
), c
->regs
[PROGRAM_OUTPUT
][i
]);
1248 brw_null_reg(), /* dest */
1249 4, /* starting mrf reg nr */
1253 mrf
+1, /* msg len */
1254 0, /* response len */
1256 1, /* writes complete */
1257 BRW_MAX_MRF
-1, /* urb destination offset */
1258 BRW_URB_SWIZZLE_INTERLEAVE
);
1264 * Called after code generation to resolve subroutine calls and the
1266 * \param end_inst points to brw code for END instruction
1267 * \param last_inst points to last instruction emitted before vertex write
1270 post_vs_emit( struct brw_vs_compile
*c
,
1271 struct brw_instruction
*end_inst
,
1272 struct brw_instruction
*last_inst
)
1276 brw_resolve_cals(&c
->func
);
1278 /* patch up the END code to jump past subroutines, etc */
1279 offset
= last_inst
- end_inst
;
1281 brw_set_src1(end_inst
, brw_imm_d(offset
* 16));
1283 end_inst
->header
.opcode
= BRW_OPCODE_NOP
;
1288 accumulator_contains(struct brw_vs_compile
*c
, struct brw_reg val
)
1290 struct brw_compile
*p
= &c
->func
;
1291 struct brw_instruction
*prev_insn
= &p
->store
[p
->nr_insn
- 1];
1293 if (p
->nr_insn
== 0)
1296 if (val
.address_mode
!= BRW_ADDRESS_DIRECT
)
1299 switch (prev_insn
->header
.opcode
) {
1300 case BRW_OPCODE_MOV
:
1301 case BRW_OPCODE_MAC
:
1302 case BRW_OPCODE_MUL
:
1303 if (prev_insn
->header
.access_mode
== BRW_ALIGN_16
&&
1304 prev_insn
->header
.execution_size
== val
.width
&&
1305 prev_insn
->bits1
.da1
.dest_reg_file
== val
.file
&&
1306 prev_insn
->bits1
.da1
.dest_reg_type
== val
.type
&&
1307 prev_insn
->bits1
.da1
.dest_address_mode
== val
.address_mode
&&
1308 prev_insn
->bits1
.da1
.dest_reg_nr
== val
.nr
&&
1309 prev_insn
->bits1
.da16
.dest_subreg_nr
== val
.subnr
/ 16 &&
1310 prev_insn
->bits1
.da16
.dest_writemask
== 0xf)
1320 get_predicate(const struct prog_instruction
*inst
)
1322 if (inst
->DstReg
.CondMask
== COND_TR
)
1323 return BRW_PREDICATE_NONE
;
1325 /* All of GLSL only produces predicates for COND_NE and one channel per
1326 * vector. Fail badly if someone starts doing something else, as it might
1327 * mean infinite looping or something.
1329 * We'd like to support all the condition codes, but our hardware doesn't
1330 * quite match the Mesa IR, which is modeled after the NV extensions. For
1331 * those, the instruction may update the condition codes or not, then any
1332 * later instruction may use one of those condition codes. For gen4, the
1333 * instruction may update the flags register based on one of the condition
1334 * codes output by the instruction, and then further instructions may
1335 * predicate on that. We can probably support this, but it won't
1336 * necessarily be easy.
1338 assert(inst
->DstReg
.CondMask
== COND_NE
);
1340 switch (inst
->DstReg
.CondSwizzle
) {
1342 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1344 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1346 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1348 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1350 _mesa_problem(NULL
, "Unexpected predicate: 0x%08x\n",
1351 inst
->DstReg
.CondMask
);
1352 return BRW_PREDICATE_NORMAL
;
1356 /* Emit the vertex program instructions here.
1358 void brw_vs_emit(struct brw_vs_compile
*c
)
1360 #define MAX_IF_DEPTH 32
1361 #define MAX_LOOP_DEPTH 32
1362 struct brw_compile
*p
= &c
->func
;
1363 struct brw_context
*brw
= p
->brw
;
1364 struct intel_context
*intel
= &brw
->intel
;
1365 const GLuint nr_insns
= c
->vp
->program
.Base
.NumInstructions
;
1366 GLuint insn
, if_depth
= 0, loop_depth
= 0;
1367 GLuint end_offset
= 0;
1368 struct brw_instruction
*end_inst
, *last_inst
;
1369 struct brw_instruction
*if_inst
[MAX_IF_DEPTH
], *loop_inst
[MAX_LOOP_DEPTH
];
1370 const struct brw_indirect stack_index
= brw_indirect(0, 0);
1374 if (INTEL_DEBUG
& DEBUG_VS
) {
1375 _mesa_printf("vs-mesa:\n");
1376 _mesa_print_program(&c
->vp
->program
.Base
);
1380 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1381 brw_set_access_mode(p
, BRW_ALIGN_16
);
1383 /* Message registers can't be read, so copy the output into GRF register
1384 if they are used in source registers */
1385 for (insn
= 0; insn
< nr_insns
; insn
++) {
1387 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1388 for (i
= 0; i
< 3; i
++) {
1389 struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1390 GLuint index
= src
->Index
;
1391 GLuint file
= src
->File
;
1392 if (file
== PROGRAM_OUTPUT
&& index
!= VERT_RESULT_HPOS
)
1393 c
->output_regs
[index
].used_in_src
= GL_TRUE
;
1397 /* Static register allocation
1399 brw_vs_alloc_regs(c
);
1400 brw_MOV(p
, get_addr_reg(stack_index
), brw_address(c
->stack
));
1402 for (insn
= 0; insn
< nr_insns
; insn
++) {
1404 const struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1405 struct brw_reg args
[3], dst
;
1409 printf("%d: ", insn
);
1410 _mesa_print_instruction(inst
);
1413 /* Get argument regs. SWZ is special and does this itself.
1415 if (inst
->Opcode
!= OPCODE_SWZ
)
1416 for (i
= 0; i
< 3; i
++) {
1417 const struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1420 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1421 args
[i
] = c
->output_regs
[index
].reg
;
1423 args
[i
] = get_arg(c
, inst
, i
);
1426 /* Get dest regs. Note that it is possible for a reg to be both
1427 * dst and arg, given the static allocation of registers. So
1428 * care needs to be taken emitting multi-operation instructions.
1430 index
= inst
->DstReg
.Index
;
1431 file
= inst
->DstReg
.File
;
1432 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1433 dst
= c
->output_regs
[index
].reg
;
1435 dst
= get_dst(c
, inst
->DstReg
);
1437 if (inst
->SaturateMode
!= SATURATE_OFF
) {
1438 _mesa_problem(NULL
, "Unsupported saturate %d in vertex shader",
1439 inst
->SaturateMode
);
1442 switch (inst
->Opcode
) {
1444 brw_MOV(p
, dst
, brw_abs(args
[0]));
1447 brw_ADD(p
, dst
, args
[0], args
[1]);
1450 emit_math1(c
, BRW_MATH_FUNCTION_COS
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1453 brw_DP3(p
, dst
, args
[0], args
[1]);
1456 brw_DP4(p
, dst
, args
[0], args
[1]);
1459 brw_DPH(p
, dst
, args
[0], args
[1]);
1462 emit_nrm(c
, dst
, args
[0], 3);
1465 emit_nrm(c
, dst
, args
[0], 4);
1468 unalias2(c
, dst
, args
[0], args
[1], emit_dst_noalias
);
1471 unalias1(c
, dst
, args
[0], emit_exp_noalias
);
1474 emit_math1(c
, BRW_MATH_FUNCTION_EXP
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1477 emit_arl(c
, dst
, args
[0]);
1480 brw_RNDD(p
, dst
, args
[0]);
1483 brw_FRC(p
, dst
, args
[0]);
1486 unalias1(c
, dst
, args
[0], emit_log_noalias
);
1489 emit_math1(c
, BRW_MATH_FUNCTION_LOG
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1492 unalias1(c
, dst
, args
[0], emit_lit_noalias
);
1495 unalias3(c
, dst
, args
[0], args
[1], args
[2], emit_lrp_noalias
);
1498 if (!accumulator_contains(c
, args
[2]))
1499 brw_MOV(p
, brw_acc_reg(), args
[2]);
1500 brw_MAC(p
, dst
, args
[0], args
[1]);
1503 emit_cmp(p
, dst
, args
[0], args
[1], args
[2]);
1506 emit_max(p
, dst
, args
[0], args
[1]);
1509 emit_min(p
, dst
, args
[0], args
[1]);
1512 brw_MOV(p
, dst
, args
[0]);
1515 brw_MUL(p
, dst
, args
[0], args
[1]);
1518 emit_math2(c
, BRW_MATH_FUNCTION_POW
, dst
, args
[0], args
[1], BRW_MATH_PRECISION_FULL
);
1521 emit_math1(c
, BRW_MATH_FUNCTION_INV
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1524 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1528 unalias2(c
, dst
, args
[0], args
[1], emit_seq
);
1531 emit_math1(c
, BRW_MATH_FUNCTION_SIN
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1534 unalias2(c
, dst
, args
[0], args
[1], emit_sne
);
1537 unalias2(c
, dst
, args
[0], args
[1], emit_sge
);
1540 unalias2(c
, dst
, args
[0], args
[1], emit_sgt
);
1543 unalias2(c
, dst
, args
[0], args
[1], emit_slt
);
1546 unalias2(c
, dst
, args
[0], args
[1], emit_sle
);
1549 brw_ADD(p
, dst
, args
[0], negate(args
[1]));
1552 /* The args[0] value can't be used here as it won't have
1553 * correctly encoded the full swizzle:
1555 emit_swz(c
, dst
, inst
);
1558 /* round toward zero */
1559 brw_RNDZ(p
, dst
, args
[0]);
1562 emit_xpd(p
, dst
, args
[0], args
[1]);
1565 assert(if_depth
< MAX_IF_DEPTH
);
1566 if_inst
[if_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1567 /* Note that brw_IF smashes the predicate_control field. */
1568 if_inst
[if_depth
]->header
.predicate_control
= get_predicate(inst
);
1572 if_inst
[if_depth
-1] = brw_ELSE(p
, if_inst
[if_depth
-1]);
1575 assert(if_depth
> 0);
1576 brw_ENDIF(p
, if_inst
[--if_depth
]);
1578 case OPCODE_BGNLOOP
:
1579 loop_inst
[loop_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
1582 brw_set_predicate_control(p
, get_predicate(inst
));
1584 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1587 brw_set_predicate_control(p
, get_predicate(inst
));
1589 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1591 case OPCODE_ENDLOOP
:
1593 struct brw_instruction
*inst0
, *inst1
;
1598 if (intel
->is_ironlake
)
1601 inst0
= inst1
= brw_WHILE(p
, loop_inst
[loop_depth
]);
1602 /* patch all the BREAK/CONT instructions from last BEGINLOOP */
1603 while (inst0
> loop_inst
[loop_depth
]) {
1605 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
) {
1606 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
1607 inst0
->bits3
.if_else
.pop_count
= 0;
1609 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
) {
1610 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
1611 inst0
->bits3
.if_else
.pop_count
= 0;
1617 brw_set_predicate_control(p
, get_predicate(inst
));
1618 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1619 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1622 brw_set_access_mode(p
, BRW_ALIGN_1
);
1623 brw_ADD(p
, deref_1d(stack_index
, 0), brw_ip_reg(), brw_imm_d(3*16));
1624 brw_set_access_mode(p
, BRW_ALIGN_16
);
1625 brw_ADD(p
, get_addr_reg(stack_index
),
1626 get_addr_reg(stack_index
), brw_imm_d(4));
1627 brw_save_call(p
, inst
->Comment
, p
->nr_insn
);
1628 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1631 brw_ADD(p
, get_addr_reg(stack_index
),
1632 get_addr_reg(stack_index
), brw_imm_d(-4));
1633 brw_set_access_mode(p
, BRW_ALIGN_1
);
1634 brw_MOV(p
, brw_ip_reg(), deref_1d(stack_index
, 0));
1635 brw_set_access_mode(p
, BRW_ALIGN_16
);
1638 end_offset
= p
->nr_insn
;
1639 /* this instruction will get patched later to jump past subroutine
1642 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1648 brw_save_label(p
, inst
->Comment
, p
->nr_insn
);
1654 _mesa_problem(NULL
, "Unsupported opcode %i (%s) in vertex shader",
1655 inst
->Opcode
, inst
->Opcode
< MAX_OPCODE
?
1656 _mesa_opcode_string(inst
->Opcode
) :
1660 /* Set the predication update on the last instruction of the native
1661 * instruction sequence.
1663 * This would be problematic if it was set on a math instruction,
1664 * but that shouldn't be the case with the current GLSL compiler.
1666 if (inst
->CondUpdate
) {
1667 struct brw_instruction
*hw_insn
= &p
->store
[p
->nr_insn
- 1];
1669 assert(hw_insn
->header
.destreg__conditionalmod
== 0);
1670 hw_insn
->header
.destreg__conditionalmod
= BRW_CONDITIONAL_NZ
;
1673 if ((inst
->DstReg
.File
== PROGRAM_OUTPUT
)
1674 && (inst
->DstReg
.Index
!= VERT_RESULT_HPOS
)
1675 && c
->output_regs
[inst
->DstReg
.Index
].used_in_src
) {
1676 brw_MOV(p
, get_dst(c
, inst
->DstReg
), dst
);
1679 /* Result color clamping.
1681 * When destination register is an output register and
1682 * it's primary/secondary front/back color, we have to clamp
1683 * the result to [0,1]. This is done by enabling the
1684 * saturation bit for the last instruction.
1686 * We don't use brw_set_saturate() as it modifies
1687 * p->current->header.saturate, which affects all the subsequent
1688 * instructions. Instead, we directly modify the header
1689 * of the last (already stored) instruction.
1691 if (inst
->DstReg
.File
== PROGRAM_OUTPUT
) {
1692 if ((inst
->DstReg
.Index
== VERT_RESULT_COL0
)
1693 || (inst
->DstReg
.Index
== VERT_RESULT_COL1
)
1694 || (inst
->DstReg
.Index
== VERT_RESULT_BFC0
)
1695 || (inst
->DstReg
.Index
== VERT_RESULT_BFC1
)) {
1696 p
->store
[p
->nr_insn
-1].header
.saturate
= 1;
1703 end_inst
= &p
->store
[end_offset
];
1704 last_inst
= &p
->store
[p
->nr_insn
];
1706 /* The END instruction will be patched to jump to this code */
1707 emit_vertex_write(c
);
1709 post_vs_emit(c
, end_inst
, last_inst
);
1711 if (INTEL_DEBUG
& DEBUG_VS
) {
1714 _mesa_printf("vs-native:\n");
1715 for (i
= 0; i
< p
->nr_insn
; i
++)
1716 brw_disasm(stderr
, &p
->store
[i
]);