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i965: Delete old metaops code now that there are no remaining consumers.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vs_emit.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/macros.h"
34 #include "shader/program.h"
35 #include "shader/prog_parameter.h"
36 #include "shader/prog_print.h"
37 #include "brw_context.h"
38 #include "brw_vs.h"
39
40
41
42 /* Do things as simply as possible. Allocate and populate all regs
43 * ahead of time.
44 */
45 static void brw_vs_alloc_regs( struct brw_vs_compile *c )
46 {
47 GLuint i, reg = 0, mrf;
48 GLuint nr_params;
49
50 /* r0 -- reserved as usual
51 */
52 c->r0 = brw_vec8_grf(reg, 0); reg++;
53
54 /* User clip planes from curbe:
55 */
56 if (c->key.nr_userclip) {
57 for (i = 0; i < c->key.nr_userclip; i++) {
58 c->userplane[i] = stride( brw_vec4_grf(reg+3+i/2, (i%2) * 4), 0, 4, 1);
59 }
60
61 /* Deal with curbe alignment:
62 */
63 reg += ((6+c->key.nr_userclip+3)/4)*2;
64 }
65
66 /* Vertex program parameters from curbe:
67 */
68 nr_params = c->vp->program.Base.Parameters->NumParameters;
69 for (i = 0; i < nr_params; i++) {
70 c->regs[PROGRAM_STATE_VAR][i] = stride( brw_vec4_grf(reg+i/2, (i%2) * 4), 0, 4, 1);
71 }
72 reg += (nr_params+1)/2;
73
74 c->prog_data.curb_read_length = reg - 1;
75
76 /* Allocate input regs:
77 */
78 c->nr_inputs = 0;
79 for (i = 0; i < VERT_ATTRIB_MAX; i++) {
80 if (c->prog_data.inputs_read & (1<<i)) {
81 c->nr_inputs++;
82 c->regs[PROGRAM_INPUT][i] = brw_vec8_grf(reg, 0);
83 reg++;
84 }
85 }
86
87 /* Allocate outputs: TODO: could organize the non-position outputs
88 * to go straight into message regs.
89 */
90 c->nr_outputs = 0;
91 c->first_output = reg;
92 mrf = 4;
93 for (i = 0; i < VERT_RESULT_MAX; i++) {
94 if (c->prog_data.outputs_written & (1<<i)) {
95 c->nr_outputs++;
96 if (i == VERT_RESULT_HPOS) {
97 c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0);
98 reg++;
99 }
100 else if (i == VERT_RESULT_PSIZ) {
101 c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0);
102 reg++;
103 mrf++; /* just a placeholder? XXX fix later stages & remove this */
104 }
105 else {
106 c->regs[PROGRAM_OUTPUT][i] = brw_message_reg(mrf);
107 mrf++;
108 }
109 }
110 }
111
112 /* Allocate program temporaries:
113 */
114 for (i = 0; i < c->vp->program.Base.NumTemporaries; i++) {
115 c->regs[PROGRAM_TEMPORARY][i] = brw_vec8_grf(reg, 0);
116 reg++;
117 }
118
119 /* Address reg(s). Don't try to use the internal address reg until
120 * deref time.
121 */
122 for (i = 0; i < c->vp->program.Base.NumAddressRegs; i++) {
123 c->regs[PROGRAM_ADDRESS][i] = brw_reg(BRW_GENERAL_REGISTER_FILE,
124 reg,
125 0,
126 BRW_REGISTER_TYPE_D,
127 BRW_VERTICAL_STRIDE_8,
128 BRW_WIDTH_8,
129 BRW_HORIZONTAL_STRIDE_1,
130 BRW_SWIZZLE_XXXX,
131 WRITEMASK_X);
132 reg++;
133 }
134
135 for (i = 0; i < 128; i++) {
136 if (c->output_regs[i].used_in_src) {
137 c->output_regs[i].reg = brw_vec8_grf(reg, 0);
138 reg++;
139 }
140 }
141
142 c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, reg, 0);
143 reg += 2;
144
145
146 /* Some opcodes need an internal temporary:
147 */
148 c->first_tmp = reg;
149 c->last_tmp = reg; /* for allocation purposes */
150
151 /* Each input reg holds data from two vertices. The
152 * urb_read_length is the number of registers read from *each*
153 * vertex urb, so is half the amount:
154 */
155 c->prog_data.urb_read_length = (c->nr_inputs+1)/2;
156
157 c->prog_data.urb_entry_size = (c->nr_outputs+2+3)/4;
158 c->prog_data.total_grf = reg;
159 }
160
161
162 static struct brw_reg get_tmp( struct brw_vs_compile *c )
163 {
164 struct brw_reg tmp = brw_vec8_grf(c->last_tmp, 0);
165
166 if (++c->last_tmp > c->prog_data.total_grf)
167 c->prog_data.total_grf = c->last_tmp;
168
169 return tmp;
170 }
171
172 static void release_tmp( struct brw_vs_compile *c, struct brw_reg tmp )
173 {
174 if (tmp.nr == c->last_tmp-1)
175 c->last_tmp--;
176 }
177
178 static void release_tmps( struct brw_vs_compile *c )
179 {
180 c->last_tmp = c->first_tmp;
181 }
182
183
184 static void unalias1( struct brw_vs_compile *c,
185 struct brw_reg dst,
186 struct brw_reg arg0,
187 void (*func)( struct brw_vs_compile *,
188 struct brw_reg,
189 struct brw_reg ))
190 {
191 if (dst.file == arg0.file && dst.nr == arg0.nr) {
192 struct brw_compile *p = &c->func;
193 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask);
194 func(c, tmp, arg0);
195 brw_MOV(p, dst, tmp);
196 release_tmp(c, tmp);
197 }
198 else {
199 func(c, dst, arg0);
200 }
201 }
202
203 static void unalias2( struct brw_vs_compile *c,
204 struct brw_reg dst,
205 struct brw_reg arg0,
206 struct brw_reg arg1,
207 void (*func)( struct brw_vs_compile *,
208 struct brw_reg,
209 struct brw_reg,
210 struct brw_reg ))
211 {
212 if ((dst.file == arg0.file && dst.nr == arg0.nr) ||
213 (dst.file == arg1.file && dst.nr == arg1.nr)) {
214 struct brw_compile *p = &c->func;
215 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask);
216 func(c, tmp, arg0, arg1);
217 brw_MOV(p, dst, tmp);
218 release_tmp(c, tmp);
219 }
220 else {
221 func(c, dst, arg0, arg1);
222 }
223 }
224
225 static void unalias3( struct brw_vs_compile *c,
226 struct brw_reg dst,
227 struct brw_reg arg0,
228 struct brw_reg arg1,
229 struct brw_reg arg2,
230 void (*func)( struct brw_vs_compile *,
231 struct brw_reg,
232 struct brw_reg,
233 struct brw_reg,
234 struct brw_reg ))
235 {
236 if ((dst.file == arg0.file && dst.nr == arg0.nr) ||
237 (dst.file == arg1.file && dst.nr == arg1.nr) ||
238 (dst.file == arg2.file && dst.nr == arg2.nr)) {
239 struct brw_compile *p = &c->func;
240 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask);
241 func(c, tmp, arg0, arg1, arg2);
242 brw_MOV(p, dst, tmp);
243 release_tmp(c, tmp);
244 }
245 else {
246 func(c, dst, arg0, arg1, arg2);
247 }
248 }
249
250 static void emit_sop( struct brw_compile *p,
251 struct brw_reg dst,
252 struct brw_reg arg0,
253 struct brw_reg arg1,
254 GLuint cond)
255 {
256 brw_MOV(p, dst, brw_imm_f(0.0f));
257 brw_CMP(p, brw_null_reg(), cond, arg0, arg1);
258 brw_MOV(p, dst, brw_imm_f(1.0f));
259 brw_set_predicate_control_flag_value(p, 0xff);
260 }
261
262 static void emit_seq( struct brw_compile *p,
263 struct brw_reg dst,
264 struct brw_reg arg0,
265 struct brw_reg arg1 )
266 {
267 emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_EQ);
268 }
269
270 static void emit_sne( struct brw_compile *p,
271 struct brw_reg dst,
272 struct brw_reg arg0,
273 struct brw_reg arg1 )
274 {
275 emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_NEQ);
276 }
277 static void emit_slt( struct brw_compile *p,
278 struct brw_reg dst,
279 struct brw_reg arg0,
280 struct brw_reg arg1 )
281 {
282 emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_L);
283 }
284
285 static void emit_sle( struct brw_compile *p,
286 struct brw_reg dst,
287 struct brw_reg arg0,
288 struct brw_reg arg1 )
289 {
290 emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_LE);
291 }
292
293 static void emit_sgt( struct brw_compile *p,
294 struct brw_reg dst,
295 struct brw_reg arg0,
296 struct brw_reg arg1 )
297 {
298 emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_G);
299 }
300
301 static void emit_sge( struct brw_compile *p,
302 struct brw_reg dst,
303 struct brw_reg arg0,
304 struct brw_reg arg1 )
305 {
306 emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_GE);
307 }
308
309 static void emit_max( struct brw_compile *p,
310 struct brw_reg dst,
311 struct brw_reg arg0,
312 struct brw_reg arg1 )
313 {
314 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0, arg1);
315 brw_SEL(p, dst, arg1, arg0);
316 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
317 }
318
319 static void emit_min( struct brw_compile *p,
320 struct brw_reg dst,
321 struct brw_reg arg0,
322 struct brw_reg arg1 )
323 {
324 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0, arg1);
325 brw_SEL(p, dst, arg0, arg1);
326 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
327 }
328
329
330 static void emit_math1( struct brw_vs_compile *c,
331 GLuint function,
332 struct brw_reg dst,
333 struct brw_reg arg0,
334 GLuint precision)
335 {
336 /* There are various odd behaviours with SEND on the simulator. In
337 * addition there are documented issues with the fact that the GEN4
338 * processor doesn't do dependency control properly on SEND
339 * results. So, on balance, this kludge to get around failures
340 * with writemasked math results looks like it might be necessary
341 * whether that turns out to be a simulator bug or not:
342 */
343 struct brw_compile *p = &c->func;
344 struct brw_reg tmp = dst;
345 GLboolean need_tmp = (dst.dw1.bits.writemask != 0xf ||
346 dst.file != BRW_GENERAL_REGISTER_FILE);
347
348 if (need_tmp)
349 tmp = get_tmp(c);
350
351 brw_math(p,
352 tmp,
353 function,
354 BRW_MATH_SATURATE_NONE,
355 2,
356 arg0,
357 BRW_MATH_DATA_SCALAR,
358 precision);
359
360 if (need_tmp) {
361 brw_MOV(p, dst, tmp);
362 release_tmp(c, tmp);
363 }
364 }
365
366
367 static void emit_math2( struct brw_vs_compile *c,
368 GLuint function,
369 struct brw_reg dst,
370 struct brw_reg arg0,
371 struct brw_reg arg1,
372 GLuint precision)
373 {
374 struct brw_compile *p = &c->func;
375 struct brw_reg tmp = dst;
376 GLboolean need_tmp = (dst.dw1.bits.writemask != 0xf ||
377 dst.file != BRW_GENERAL_REGISTER_FILE);
378
379 if (need_tmp)
380 tmp = get_tmp(c);
381
382 brw_MOV(p, brw_message_reg(3), arg1);
383
384 brw_math(p,
385 tmp,
386 function,
387 BRW_MATH_SATURATE_NONE,
388 2,
389 arg0,
390 BRW_MATH_DATA_SCALAR,
391 precision);
392
393 if (need_tmp) {
394 brw_MOV(p, dst, tmp);
395 release_tmp(c, tmp);
396 }
397 }
398
399
400 static void emit_exp_noalias( struct brw_vs_compile *c,
401 struct brw_reg dst,
402 struct brw_reg arg0 )
403 {
404 struct brw_compile *p = &c->func;
405
406
407 if (dst.dw1.bits.writemask & WRITEMASK_X) {
408 struct brw_reg tmp = get_tmp(c);
409 struct brw_reg tmp_d = retype(tmp, BRW_REGISTER_TYPE_D);
410
411 /* tmp_d = floor(arg0.x) */
412 brw_RNDD(p, tmp_d, brw_swizzle1(arg0, 0));
413
414 /* result[0] = 2.0 ^ tmp */
415
416 /* Adjust exponent for floating point:
417 * exp += 127
418 */
419 brw_ADD(p, brw_writemask(tmp_d, WRITEMASK_X), tmp_d, brw_imm_d(127));
420
421 /* Install exponent and sign.
422 * Excess drops off the edge:
423 */
424 brw_SHL(p, brw_writemask(retype(dst, BRW_REGISTER_TYPE_D), WRITEMASK_X),
425 tmp_d, brw_imm_d(23));
426
427 release_tmp(c, tmp);
428 }
429
430 if (dst.dw1.bits.writemask & WRITEMASK_Y) {
431 /* result[1] = arg0.x - floor(arg0.x) */
432 brw_FRC(p, brw_writemask(dst, WRITEMASK_Y), brw_swizzle1(arg0, 0));
433 }
434
435 if (dst.dw1.bits.writemask & WRITEMASK_Z) {
436 /* As with the LOG instruction, we might be better off just
437 * doing a taylor expansion here, seeing as we have to do all
438 * the prep work.
439 *
440 * If mathbox partial precision is too low, consider also:
441 * result[3] = result[0] * EXP(result[1])
442 */
443 emit_math1(c,
444 BRW_MATH_FUNCTION_EXP,
445 brw_writemask(dst, WRITEMASK_Z),
446 brw_swizzle1(arg0, 0),
447 BRW_MATH_PRECISION_FULL);
448 }
449
450 if (dst.dw1.bits.writemask & WRITEMASK_W) {
451 /* result[3] = 1.0; */
452 brw_MOV(p, brw_writemask(dst, WRITEMASK_W), brw_imm_f(1));
453 }
454 }
455
456
457 static void emit_log_noalias( struct brw_vs_compile *c,
458 struct brw_reg dst,
459 struct brw_reg arg0 )
460 {
461 struct brw_compile *p = &c->func;
462 struct brw_reg tmp = dst;
463 struct brw_reg tmp_ud = retype(tmp, BRW_REGISTER_TYPE_UD);
464 struct brw_reg arg0_ud = retype(arg0, BRW_REGISTER_TYPE_UD);
465 GLboolean need_tmp = (dst.dw1.bits.writemask != 0xf ||
466 dst.file != BRW_GENERAL_REGISTER_FILE);
467
468 if (need_tmp) {
469 tmp = get_tmp(c);
470 tmp_ud = retype(tmp, BRW_REGISTER_TYPE_UD);
471 }
472
473 /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt
474 * according to spec:
475 *
476 * These almost look likey they could be joined up, but not really
477 * practical:
478 *
479 * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127
480 * result[1].i = (x.i & ((1<<23)-1) + (127<<23)
481 */
482 if (dst.dw1.bits.writemask & WRITEMASK_XZ) {
483 brw_AND(p,
484 brw_writemask(tmp_ud, WRITEMASK_X),
485 brw_swizzle1(arg0_ud, 0),
486 brw_imm_ud((1U<<31)-1));
487
488 brw_SHR(p,
489 brw_writemask(tmp_ud, WRITEMASK_X),
490 tmp_ud,
491 brw_imm_ud(23));
492
493 brw_ADD(p,
494 brw_writemask(tmp, WRITEMASK_X),
495 retype(tmp_ud, BRW_REGISTER_TYPE_D), /* does it matter? */
496 brw_imm_d(-127));
497 }
498
499 if (dst.dw1.bits.writemask & WRITEMASK_YZ) {
500 brw_AND(p,
501 brw_writemask(tmp_ud, WRITEMASK_Y),
502 brw_swizzle1(arg0_ud, 0),
503 brw_imm_ud((1<<23)-1));
504
505 brw_OR(p,
506 brw_writemask(tmp_ud, WRITEMASK_Y),
507 tmp_ud,
508 brw_imm_ud(127<<23));
509 }
510
511 if (dst.dw1.bits.writemask & WRITEMASK_Z) {
512 /* result[2] = result[0] + LOG2(result[1]); */
513
514 /* Why bother? The above is just a hint how to do this with a
515 * taylor series. Maybe we *should* use a taylor series as by
516 * the time all the above has been done it's almost certainly
517 * quicker than calling the mathbox, even with low precision.
518 *
519 * Options are:
520 * - result[0] + mathbox.LOG2(result[1])
521 * - mathbox.LOG2(arg0.x)
522 * - result[0] + inline_taylor_approx(result[1])
523 */
524 emit_math1(c,
525 BRW_MATH_FUNCTION_LOG,
526 brw_writemask(tmp, WRITEMASK_Z),
527 brw_swizzle1(tmp, 1),
528 BRW_MATH_PRECISION_FULL);
529
530 brw_ADD(p,
531 brw_writemask(tmp, WRITEMASK_Z),
532 brw_swizzle1(tmp, 2),
533 brw_swizzle1(tmp, 0));
534 }
535
536 if (dst.dw1.bits.writemask & WRITEMASK_W) {
537 /* result[3] = 1.0; */
538 brw_MOV(p, brw_writemask(tmp, WRITEMASK_W), brw_imm_f(1));
539 }
540
541 if (need_tmp) {
542 brw_MOV(p, dst, tmp);
543 release_tmp(c, tmp);
544 }
545 }
546
547
548 /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
549 */
550 static void emit_dst_noalias( struct brw_vs_compile *c,
551 struct brw_reg dst,
552 struct brw_reg arg0,
553 struct brw_reg arg1)
554 {
555 struct brw_compile *p = &c->func;
556
557 /* There must be a better way to do this:
558 */
559 if (dst.dw1.bits.writemask & WRITEMASK_X)
560 brw_MOV(p, brw_writemask(dst, WRITEMASK_X), brw_imm_f(1.0));
561 if (dst.dw1.bits.writemask & WRITEMASK_Y)
562 brw_MUL(p, brw_writemask(dst, WRITEMASK_Y), arg0, arg1);
563 if (dst.dw1.bits.writemask & WRITEMASK_Z)
564 brw_MOV(p, brw_writemask(dst, WRITEMASK_Z), arg0);
565 if (dst.dw1.bits.writemask & WRITEMASK_W)
566 brw_MOV(p, brw_writemask(dst, WRITEMASK_W), arg1);
567 }
568
569
570 static void emit_xpd( struct brw_compile *p,
571 struct brw_reg dst,
572 struct brw_reg t,
573 struct brw_reg u)
574 {
575 brw_MUL(p, brw_null_reg(), brw_swizzle(t, 1,2,0,3), brw_swizzle(u,2,0,1,3));
576 brw_MAC(p, dst, negate(brw_swizzle(t, 2,0,1,3)), brw_swizzle(u,1,2,0,3));
577 }
578
579
580 static void emit_lit_noalias( struct brw_vs_compile *c,
581 struct brw_reg dst,
582 struct brw_reg arg0 )
583 {
584 struct brw_compile *p = &c->func;
585 struct brw_instruction *if_insn;
586 struct brw_reg tmp = dst;
587 GLboolean need_tmp = (dst.file != BRW_GENERAL_REGISTER_FILE);
588
589 if (need_tmp)
590 tmp = get_tmp(c);
591
592 brw_MOV(p, brw_writemask(dst, WRITEMASK_YZ), brw_imm_f(0));
593 brw_MOV(p, brw_writemask(dst, WRITEMASK_XW), brw_imm_f(1));
594
595 /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order
596 * to get all channels active inside the IF. In the clipping code
597 * we run with NoMask, so it's not an option and we can use
598 * BRW_EXECUTE_1 for all comparisions.
599 */
600 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_G, brw_swizzle1(arg0,0), brw_imm_f(0));
601 if_insn = brw_IF(p, BRW_EXECUTE_8);
602 {
603 brw_MOV(p, brw_writemask(dst, WRITEMASK_Y), brw_swizzle1(arg0,0));
604
605 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_G, brw_swizzle1(arg0,1), brw_imm_f(0));
606 brw_MOV(p, brw_writemask(tmp, WRITEMASK_Z), brw_swizzle1(arg0,1));
607 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
608
609 emit_math2(c,
610 BRW_MATH_FUNCTION_POW,
611 brw_writemask(dst, WRITEMASK_Z),
612 brw_swizzle1(tmp, 2),
613 brw_swizzle1(arg0, 3),
614 BRW_MATH_PRECISION_PARTIAL);
615 }
616
617 brw_ENDIF(p, if_insn);
618 }
619
620 static void emit_lrp_noalias(struct brw_vs_compile *c,
621 struct brw_reg dst,
622 struct brw_reg arg0,
623 struct brw_reg arg1,
624 struct brw_reg arg2)
625 {
626 struct brw_compile *p = &c->func;
627
628 brw_ADD(p, dst, negate(arg0), brw_imm_f(1.0));
629 brw_MUL(p, brw_null_reg(), dst, arg2);
630 brw_MAC(p, dst, arg0, arg1);
631 }
632
633 /** 3 or 4-component vector normalization */
634 static void emit_nrm( struct brw_vs_compile *c,
635 struct brw_reg dst,
636 struct brw_reg arg0,
637 int num_comps)
638 {
639 struct brw_compile *p = &c->func;
640 struct brw_reg tmp = get_tmp(c);
641
642 /* tmp = dot(arg0, arg0) */
643 if (num_comps == 3)
644 brw_DP3(p, tmp, arg0, arg0);
645 else
646 brw_DP4(p, tmp, arg0, arg0);
647
648 /* tmp = 1 / sqrt(tmp) */
649 emit_math1(c, BRW_MATH_FUNCTION_RSQ, tmp, tmp, BRW_MATH_PRECISION_FULL);
650
651 /* dst = arg0 * tmp */
652 brw_MUL(p, dst, arg0, tmp);
653
654 release_tmp(c, tmp);
655 }
656
657
658 /* TODO: relative addressing!
659 */
660 static struct brw_reg get_reg( struct brw_vs_compile *c,
661 GLuint file,
662 GLuint index )
663 {
664
665 switch (file) {
666 case PROGRAM_TEMPORARY:
667 case PROGRAM_INPUT:
668 case PROGRAM_OUTPUT:
669 assert(c->regs[file][index].nr != 0);
670 return c->regs[file][index];
671 case PROGRAM_STATE_VAR:
672 case PROGRAM_CONSTANT:
673 case PROGRAM_UNIFORM:
674 assert(c->regs[PROGRAM_STATE_VAR][index].nr != 0);
675 return c->regs[PROGRAM_STATE_VAR][index];
676 case PROGRAM_ADDRESS:
677 assert(index == 0);
678 return c->regs[file][index];
679
680 case PROGRAM_UNDEFINED: /* undef values */
681 return brw_null_reg();
682
683 case PROGRAM_LOCAL_PARAM:
684 case PROGRAM_ENV_PARAM:
685 case PROGRAM_WRITE_ONLY:
686 default:
687 assert(0);
688 return brw_null_reg();
689 }
690 }
691
692
693 static struct brw_reg deref( struct brw_vs_compile *c,
694 struct brw_reg arg,
695 GLint offset)
696 {
697 struct brw_compile *p = &c->func;
698 struct brw_reg tmp = vec4(get_tmp(c));
699 struct brw_reg vp_address = retype(vec1(get_reg(c, PROGRAM_ADDRESS, 0)), BRW_REGISTER_TYPE_UW);
700 GLuint byte_offset = arg.nr * 32 + arg.subnr + offset * 16;
701 struct brw_reg indirect = brw_vec4_indirect(0,0);
702
703 {
704 brw_push_insn_state(p);
705 brw_set_access_mode(p, BRW_ALIGN_1);
706
707 /* This is pretty clunky - load the address register twice and
708 * fetch each 4-dword value in turn. There must be a way to do
709 * this in a single pass, but I couldn't get it to work.
710 */
711 brw_ADD(p, brw_address_reg(0), vp_address, brw_imm_d(byte_offset));
712 brw_MOV(p, tmp, indirect);
713
714 brw_ADD(p, brw_address_reg(0), suboffset(vp_address, 8), brw_imm_d(byte_offset));
715 brw_MOV(p, suboffset(tmp, 4), indirect);
716
717 brw_pop_insn_state(p);
718 }
719
720 return vec8(tmp);
721 }
722
723
724 static void emit_arl( struct brw_vs_compile *c,
725 struct brw_reg dst,
726 struct brw_reg arg0 )
727 {
728 struct brw_compile *p = &c->func;
729 struct brw_reg tmp = dst;
730 GLboolean need_tmp = (dst.file != BRW_GENERAL_REGISTER_FILE);
731
732 if (need_tmp)
733 tmp = get_tmp(c);
734
735 brw_RNDD(p, tmp, arg0);
736 brw_MUL(p, dst, tmp, brw_imm_d(16));
737
738 if (need_tmp)
739 release_tmp(c, tmp);
740 }
741
742
743 /* Will return mangled results for SWZ op. The emit_swz() function
744 * ignores this result and recalculates taking extended swizzles into
745 * account.
746 */
747 static struct brw_reg get_arg( struct brw_vs_compile *c,
748 struct prog_src_register *src )
749 {
750 struct brw_reg reg;
751
752 if (src->File == PROGRAM_UNDEFINED)
753 return brw_null_reg();
754
755 if (src->RelAddr)
756 reg = deref(c, c->regs[PROGRAM_STATE_VAR][0], src->Index);
757 else
758 reg = get_reg(c, src->File, src->Index);
759
760 /* Convert 3-bit swizzle to 2-bit.
761 */
762 reg.dw1.bits.swizzle = BRW_SWIZZLE4(GET_SWZ(src->Swizzle, 0),
763 GET_SWZ(src->Swizzle, 1),
764 GET_SWZ(src->Swizzle, 2),
765 GET_SWZ(src->Swizzle, 3));
766
767 /* Note this is ok for non-swizzle instructions:
768 */
769 reg.negate = src->NegateBase ? 1 : 0;
770
771 return reg;
772 }
773
774
775 static struct brw_reg get_dst( struct brw_vs_compile *c,
776 struct prog_dst_register dst )
777 {
778 struct brw_reg reg = get_reg(c, dst.File, dst.Index);
779
780 reg.dw1.bits.writemask = dst.WriteMask;
781
782 return reg;
783 }
784
785
786 static void emit_swz( struct brw_vs_compile *c,
787 struct brw_reg dst,
788 struct prog_src_register src )
789 {
790 struct brw_compile *p = &c->func;
791 GLuint zeros_mask = 0;
792 GLuint ones_mask = 0;
793 GLuint src_mask = 0;
794 GLubyte src_swz[4];
795 GLboolean need_tmp = (src.NegateBase &&
796 dst.file != BRW_GENERAL_REGISTER_FILE);
797 struct brw_reg tmp = dst;
798 GLuint i;
799
800 if (need_tmp)
801 tmp = get_tmp(c);
802
803 for (i = 0; i < 4; i++) {
804 if (dst.dw1.bits.writemask & (1<<i)) {
805 GLubyte s = GET_SWZ(src.Swizzle, i);
806 switch (s) {
807 case SWIZZLE_X:
808 case SWIZZLE_Y:
809 case SWIZZLE_Z:
810 case SWIZZLE_W:
811 src_mask |= 1<<i;
812 src_swz[i] = s;
813 break;
814 case SWIZZLE_ZERO:
815 zeros_mask |= 1<<i;
816 break;
817 case SWIZZLE_ONE:
818 ones_mask |= 1<<i;
819 break;
820 }
821 }
822 }
823
824 /* Do src first, in case dst aliases src:
825 */
826 if (src_mask) {
827 struct brw_reg arg0;
828
829 if (src.RelAddr)
830 arg0 = deref(c, c->regs[PROGRAM_STATE_VAR][0], src.Index);
831 else
832 arg0 = get_reg(c, src.File, src.Index);
833
834 arg0 = brw_swizzle(arg0,
835 src_swz[0], src_swz[1],
836 src_swz[2], src_swz[3]);
837
838 brw_MOV(p, brw_writemask(tmp, src_mask), arg0);
839 }
840
841 if (zeros_mask)
842 brw_MOV(p, brw_writemask(tmp, zeros_mask), brw_imm_f(0));
843
844 if (ones_mask)
845 brw_MOV(p, brw_writemask(tmp, ones_mask), brw_imm_f(1));
846
847 if (src.NegateBase)
848 brw_MOV(p, brw_writemask(tmp, src.NegateBase), negate(tmp));
849
850 if (need_tmp) {
851 brw_MOV(p, dst, tmp);
852 release_tmp(c, tmp);
853 }
854 }
855
856
857 /**
858 * Post-vertex-program processing. Send the results to the URB.
859 */
860 static void emit_vertex_write( struct brw_vs_compile *c)
861 {
862 struct brw_compile *p = &c->func;
863 struct brw_reg m0 = brw_message_reg(0);
864 struct brw_reg pos = c->regs[PROGRAM_OUTPUT][VERT_RESULT_HPOS];
865 struct brw_reg ndc;
866
867 if (c->key.copy_edgeflag) {
868 brw_MOV(p,
869 get_reg(c, PROGRAM_OUTPUT, VERT_RESULT_EDGE),
870 get_reg(c, PROGRAM_INPUT, VERT_ATTRIB_EDGEFLAG));
871 }
872
873 /* Build ndc coords */
874 ndc = get_tmp(c);
875 emit_math1(c, BRW_MATH_FUNCTION_INV, ndc, brw_swizzle1(pos, 3), BRW_MATH_PRECISION_FULL);
876 brw_MUL(p, brw_writemask(ndc, WRITEMASK_XYZ), pos, ndc);
877
878 /* Update the header for point size, user clipping flags, and -ve rhw
879 * workaround.
880 */
881 if ((c->prog_data.outputs_written & (1<<VERT_RESULT_PSIZ)) ||
882 c->key.nr_userclip || !BRW_IS_G4X(p->brw))
883 {
884 struct brw_reg header1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
885 GLuint i;
886
887 brw_MOV(p, header1, brw_imm_ud(0));
888
889 brw_set_access_mode(p, BRW_ALIGN_16);
890
891 if (c->prog_data.outputs_written & (1<<VERT_RESULT_PSIZ)) {
892 struct brw_reg psiz = c->regs[PROGRAM_OUTPUT][VERT_RESULT_PSIZ];
893 brw_MUL(p, brw_writemask(header1, WRITEMASK_W), brw_swizzle1(psiz, 0), brw_imm_f(1<<11));
894 brw_AND(p, brw_writemask(header1, WRITEMASK_W), header1, brw_imm_ud(0x7ff<<8));
895 }
896
897 for (i = 0; i < c->key.nr_userclip; i++) {
898 brw_set_conditionalmod(p, BRW_CONDITIONAL_L);
899 brw_DP4(p, brw_null_reg(), pos, c->userplane[i]);
900 brw_OR(p, brw_writemask(header1, WRITEMASK_W), header1, brw_imm_ud(1<<i));
901 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
902 }
903
904 /* i965 clipping workaround:
905 * 1) Test for -ve rhw
906 * 2) If set,
907 * set ndc = (0,0,0,0)
908 * set ucp[6] = 1
909 *
910 * Later, clipping will detect ucp[6] and ensure the primitive is
911 * clipped against all fixed planes.
912 */
913 if (!BRW_IS_G4X(p->brw)) {
914 brw_CMP(p,
915 vec8(brw_null_reg()),
916 BRW_CONDITIONAL_L,
917 brw_swizzle1(ndc, 3),
918 brw_imm_f(0));
919
920 brw_OR(p, brw_writemask(header1, WRITEMASK_W), header1, brw_imm_ud(1<<6));
921 brw_MOV(p, ndc, brw_imm_f(0));
922 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
923 }
924
925 brw_set_access_mode(p, BRW_ALIGN_1); /* why? */
926 brw_MOV(p, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD), header1);
927 brw_set_access_mode(p, BRW_ALIGN_16);
928
929 release_tmp(c, header1);
930 }
931 else {
932 brw_MOV(p, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD), brw_imm_ud(0));
933 }
934
935 /* Emit the (interleaved) headers for the two vertices - an 8-reg
936 * of zeros followed by two sets of NDC coordinates:
937 */
938 brw_set_access_mode(p, BRW_ALIGN_1);
939 brw_MOV(p, offset(m0, 2), ndc);
940 brw_MOV(p, offset(m0, 3), pos);
941
942 brw_urb_WRITE(p,
943 brw_null_reg(), /* dest */
944 0, /* starting mrf reg nr */
945 c->r0, /* src */
946 0, /* allocate */
947 1, /* used */
948 c->nr_outputs + 3, /* msg len */
949 0, /* response len */
950 1, /* eot */
951 1, /* writes complete */
952 0, /* urb destination offset */
953 BRW_URB_SWIZZLE_INTERLEAVE);
954 }
955
956
957 static void
958 post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst )
959 {
960 GLuint nr_insns = c->vp->program.Base.NumInstructions;
961 GLuint insn, target_insn;
962 struct prog_instruction *inst1, *inst2;
963 struct brw_instruction *brw_inst1, *brw_inst2;
964 int offset;
965 for (insn = 0; insn < nr_insns; insn++) {
966 inst1 = &c->vp->program.Base.Instructions[insn];
967 brw_inst1 = inst1->Data;
968 switch (inst1->Opcode) {
969 case OPCODE_CAL:
970 case OPCODE_BRA:
971 target_insn = inst1->BranchTarget;
972 inst2 = &c->vp->program.Base.Instructions[target_insn];
973 brw_inst2 = inst2->Data;
974 offset = brw_inst2 - brw_inst1;
975 brw_set_src1(brw_inst1, brw_imm_d(offset*16));
976 break;
977 case OPCODE_END:
978 offset = end_inst - brw_inst1;
979 brw_set_src1(brw_inst1, brw_imm_d(offset*16));
980 break;
981 default:
982 break;
983 }
984 }
985 }
986
987 /* Emit the fragment program instructions here.
988 */
989 void brw_vs_emit(struct brw_vs_compile *c )
990 {
991 #define MAX_IFSN 32
992 struct brw_compile *p = &c->func;
993 GLuint nr_insns = c->vp->program.Base.NumInstructions;
994 GLuint insn, if_insn = 0;
995 struct brw_instruction *end_inst;
996 struct brw_instruction *if_inst[MAX_IFSN];
997 struct brw_indirect stack_index = brw_indirect(0, 0);
998
999 GLuint index;
1000 GLuint file;
1001
1002 if (INTEL_DEBUG & DEBUG_VS) {
1003 _mesa_printf("vs-emit:\n");
1004 _mesa_print_program(&c->vp->program.Base);
1005 _mesa_printf("\n");
1006 }
1007
1008 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1009 brw_set_access_mode(p, BRW_ALIGN_16);
1010
1011 /* Message registers can't be read, so copy the output into GRF register
1012 if they are used in source registers */
1013 for (insn = 0; insn < nr_insns; insn++) {
1014 GLuint i;
1015 struct prog_instruction *inst = &c->vp->program.Base.Instructions[insn];
1016 for (i = 0; i < 3; i++) {
1017 struct prog_src_register *src = &inst->SrcReg[i];
1018 GLuint index = src->Index;
1019 GLuint file = src->File;
1020 if (file == PROGRAM_OUTPUT && index != VERT_RESULT_HPOS)
1021 c->output_regs[index].used_in_src = GL_TRUE;
1022 }
1023 }
1024
1025 /* Static register allocation
1026 */
1027 brw_vs_alloc_regs(c);
1028 brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
1029
1030 for (insn = 0; insn < nr_insns; insn++) {
1031
1032 struct prog_instruction *inst = &c->vp->program.Base.Instructions[insn];
1033 struct brw_reg args[3], dst;
1034 GLuint i;
1035
1036 /* Get argument regs. SWZ is special and does this itself.
1037 */
1038 inst->Data = &p->store[p->nr_insn];
1039 if (inst->Opcode != OPCODE_SWZ)
1040 for (i = 0; i < 3; i++) {
1041 struct prog_src_register *src = &inst->SrcReg[i];
1042 index = src->Index;
1043 file = src->File;
1044 if (file == PROGRAM_OUTPUT&&c->output_regs[index].used_in_src)
1045 args[i] = c->output_regs[index].reg;
1046 else
1047 args[i] = get_arg(c, src);
1048 }
1049
1050 /* Get dest regs. Note that it is possible for a reg to be both
1051 * dst and arg, given the static allocation of registers. So
1052 * care needs to be taken emitting multi-operation instructions.
1053 */
1054 index = inst->DstReg.Index;
1055 file = inst->DstReg.File;
1056 if (file == PROGRAM_OUTPUT && c->output_regs[index].used_in_src)
1057 dst = c->output_regs[index].reg;
1058 else
1059 dst = get_dst(c, inst->DstReg);
1060
1061 if (inst->SaturateMode != SATURATE_OFF) {
1062 _mesa_problem(NULL, "Unsupported saturate %d in vertex shader",
1063 inst->SaturateMode);
1064 }
1065
1066 switch (inst->Opcode) {
1067 case OPCODE_ABS:
1068 brw_MOV(p, dst, brw_abs(args[0]));
1069 break;
1070 case OPCODE_ADD:
1071 brw_ADD(p, dst, args[0], args[1]);
1072 break;
1073 case OPCODE_COS:
1074 emit_math1(c, BRW_MATH_FUNCTION_COS, dst, args[0], BRW_MATH_PRECISION_FULL);
1075 break;
1076 case OPCODE_DP3:
1077 brw_DP3(p, dst, args[0], args[1]);
1078 break;
1079 case OPCODE_DP4:
1080 brw_DP4(p, dst, args[0], args[1]);
1081 break;
1082 case OPCODE_DPH:
1083 brw_DPH(p, dst, args[0], args[1]);
1084 break;
1085 case OPCODE_NRM3:
1086 emit_nrm(c, dst, args[0], 3);
1087 break;
1088 case OPCODE_NRM4:
1089 emit_nrm(c, dst, args[0], 4);
1090 break;
1091 case OPCODE_DST:
1092 unalias2(c, dst, args[0], args[1], emit_dst_noalias);
1093 break;
1094 case OPCODE_EXP:
1095 unalias1(c, dst, args[0], emit_exp_noalias);
1096 break;
1097 case OPCODE_EX2:
1098 emit_math1(c, BRW_MATH_FUNCTION_EXP, dst, args[0], BRW_MATH_PRECISION_FULL);
1099 break;
1100 case OPCODE_ARL:
1101 emit_arl(c, dst, args[0]);
1102 break;
1103 case OPCODE_FLR:
1104 brw_RNDD(p, dst, args[0]);
1105 break;
1106 case OPCODE_FRC:
1107 brw_FRC(p, dst, args[0]);
1108 break;
1109 case OPCODE_LOG:
1110 unalias1(c, dst, args[0], emit_log_noalias);
1111 break;
1112 case OPCODE_LG2:
1113 emit_math1(c, BRW_MATH_FUNCTION_LOG, dst, args[0], BRW_MATH_PRECISION_FULL);
1114 break;
1115 case OPCODE_LIT:
1116 unalias1(c, dst, args[0], emit_lit_noalias);
1117 break;
1118 case OPCODE_LRP:
1119 unalias3(c, dst, args[0], args[1], args[2], emit_lrp_noalias);
1120 break;
1121 case OPCODE_MAD:
1122 brw_MOV(p, brw_acc_reg(), args[2]);
1123 brw_MAC(p, dst, args[0], args[1]);
1124 break;
1125 case OPCODE_MAX:
1126 emit_max(p, dst, args[0], args[1]);
1127 break;
1128 case OPCODE_MIN:
1129 emit_min(p, dst, args[0], args[1]);
1130 break;
1131 case OPCODE_MOV:
1132 brw_MOV(p, dst, args[0]);
1133 break;
1134 case OPCODE_MUL:
1135 brw_MUL(p, dst, args[0], args[1]);
1136 break;
1137 case OPCODE_POW:
1138 emit_math2(c, BRW_MATH_FUNCTION_POW, dst, args[0], args[1], BRW_MATH_PRECISION_FULL);
1139 break;
1140 case OPCODE_RCP:
1141 emit_math1(c, BRW_MATH_FUNCTION_INV, dst, args[0], BRW_MATH_PRECISION_FULL);
1142 break;
1143 case OPCODE_RSQ:
1144 emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, args[0], BRW_MATH_PRECISION_FULL);
1145 break;
1146
1147 case OPCODE_SEQ:
1148 emit_seq(p, dst, args[0], args[1]);
1149 break;
1150 case OPCODE_SIN:
1151 emit_math1(c, BRW_MATH_FUNCTION_SIN, dst, args[0], BRW_MATH_PRECISION_FULL);
1152 break;
1153 case OPCODE_SNE:
1154 emit_sne(p, dst, args[0], args[1]);
1155 break;
1156 case OPCODE_SGE:
1157 emit_sge(p, dst, args[0], args[1]);
1158 break;
1159 case OPCODE_SGT:
1160 emit_sgt(p, dst, args[0], args[1]);
1161 break;
1162 case OPCODE_SLT:
1163 emit_slt(p, dst, args[0], args[1]);
1164 break;
1165 case OPCODE_SLE:
1166 emit_sle(p, dst, args[0], args[1]);
1167 break;
1168 case OPCODE_SUB:
1169 brw_ADD(p, dst, args[0], negate(args[1]));
1170 break;
1171 case OPCODE_SWZ:
1172 /* The args[0] value can't be used here as it won't have
1173 * correctly encoded the full swizzle:
1174 */
1175 emit_swz(c, dst, inst->SrcReg[0] );
1176 break;
1177 case OPCODE_TRUNC:
1178 /* round toward zero */
1179 brw_RNDZ(p, dst, args[0]);
1180 break;
1181 case OPCODE_XPD:
1182 emit_xpd(p, dst, args[0], args[1]);
1183 break;
1184 case OPCODE_IF:
1185 assert(if_insn < MAX_IFSN);
1186 if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8);
1187 break;
1188 case OPCODE_ELSE:
1189 if_inst[if_insn-1] = brw_ELSE(p, if_inst[if_insn-1]);
1190 break;
1191 case OPCODE_ENDIF:
1192 assert(if_insn > 0);
1193 brw_ENDIF(p, if_inst[--if_insn]);
1194 break;
1195 case OPCODE_BRA:
1196 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
1197 brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1198 brw_set_predicate_control_flag_value(p, 0xff);
1199 break;
1200 case OPCODE_CAL:
1201 brw_set_access_mode(p, BRW_ALIGN_1);
1202 brw_ADD(p, deref_1d(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
1203 brw_set_access_mode(p, BRW_ALIGN_16);
1204 brw_ADD(p, get_addr_reg(stack_index),
1205 get_addr_reg(stack_index), brw_imm_d(4));
1206 inst->Data = &p->store[p->nr_insn];
1207 brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1208 break;
1209 case OPCODE_RET:
1210 brw_ADD(p, get_addr_reg(stack_index),
1211 get_addr_reg(stack_index), brw_imm_d(-4));
1212 brw_set_access_mode(p, BRW_ALIGN_1);
1213 brw_MOV(p, brw_ip_reg(), deref_1d(stack_index, 0));
1214 brw_set_access_mode(p, BRW_ALIGN_16);
1215 case OPCODE_END:
1216 brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1217 break;
1218 case OPCODE_PRINT:
1219 case OPCODE_BGNSUB:
1220 case OPCODE_ENDSUB:
1221 /* no-op instructions */
1222 break;
1223 default:
1224 _mesa_problem(NULL, "Unsupported opcode %i (%s) in vertex shader",
1225 inst->Opcode, inst->Opcode < MAX_OPCODE ?
1226 _mesa_opcode_string(inst->Opcode) :
1227 "unknown");
1228 }
1229
1230 if ((inst->DstReg.File == PROGRAM_OUTPUT)
1231 && (inst->DstReg.Index != VERT_RESULT_HPOS)
1232 && c->output_regs[inst->DstReg.Index].used_in_src) {
1233 brw_MOV(p, get_dst(c, inst->DstReg), dst);
1234 }
1235
1236 /* Result color clamping.
1237 *
1238 * When destination register is an output register and
1239 * it's primary/secondary front/back color, we have to clamp
1240 * the result to [0,1]. This is done by enabling the
1241 * saturation bit for the last instruction.
1242 *
1243 * We don't use brw_set_saturate() as it modifies
1244 * p->current->header.saturate, which affects all the subsequent
1245 * instructions. Instead, we directly modify the header
1246 * of the last (already stored) instruction.
1247 */
1248 if (inst->DstReg.File == PROGRAM_OUTPUT) {
1249 if ((inst->DstReg.Index == VERT_RESULT_COL0)
1250 || (inst->DstReg.Index == VERT_RESULT_COL1)
1251 || (inst->DstReg.Index == VERT_RESULT_BFC0)
1252 || (inst->DstReg.Index == VERT_RESULT_BFC1)) {
1253 p->store[p->nr_insn-1].header.saturate = 1;
1254 }
1255 }
1256
1257 release_tmps(c);
1258 }
1259
1260 end_inst = &p->store[p->nr_insn];
1261 emit_vertex_write(c);
1262 post_vs_emit(c, end_inst);
1263 for (insn = 0; insn < nr_insns; insn++)
1264 c->vp->program.Base.Instructions[insn].Data = NULL;
1265 }