2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/macros.h"
34 #include "shader/program.h"
35 #include "shader/prog_parameter.h"
36 #include "shader/prog_print.h"
37 #include "brw_context.h"
41 static struct brw_reg
get_tmp( struct brw_vs_compile
*c
)
43 struct brw_reg tmp
= brw_vec8_grf(c
->last_tmp
, 0);
45 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
46 c
->prog_data
.total_grf
= c
->last_tmp
;
51 static void release_tmp( struct brw_vs_compile
*c
, struct brw_reg tmp
)
53 if (tmp
.nr
== c
->last_tmp
-1)
57 static void release_tmps( struct brw_vs_compile
*c
)
59 c
->last_tmp
= c
->first_tmp
;
64 * Preallocate GRF register before code emit.
65 * Do things as simply as possible. Allocate and populate all regs
68 static void brw_vs_alloc_regs( struct brw_vs_compile
*c
)
70 struct intel_context
*intel
= &c
->func
.brw
->intel
;
71 GLuint i
, reg
= 0, mrf
;
72 int attributes_in_vue
;
74 /* Determine whether to use a real constant buffer or use a block
75 * of GRF registers for constants. The later is faster but only
76 * works if everything fits in the GRF.
77 * XXX this heuristic/check may need some fine tuning...
79 if (c
->vp
->program
.Base
.Parameters
->NumParameters
+
80 c
->vp
->program
.Base
.NumTemporaries
+ 20 > BRW_MAX_GRF
)
81 c
->vp
->use_const_buffer
= GL_TRUE
;
83 c
->vp
->use_const_buffer
= GL_FALSE
;
85 /*printf("use_const_buffer = %d\n", c->vp->use_const_buffer);*/
87 /* r0 -- reserved as usual
89 c
->r0
= brw_vec8_grf(reg
, 0);
92 /* User clip planes from curbe:
94 if (c
->key
.nr_userclip
) {
95 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
96 c
->userplane
[i
] = stride( brw_vec4_grf(reg
+3+i
/2, (i
%2) * 4), 0, 4, 1);
99 /* Deal with curbe alignment:
101 reg
+= ((6 + c
->key
.nr_userclip
+ 3) / 4) * 2;
104 /* Vertex program parameters from curbe:
106 if (c
->vp
->use_const_buffer
) {
107 int max_constant
= BRW_MAX_GRF
- 20 - c
->vp
->program
.Base
.NumTemporaries
;
110 /* We've got more constants than we can load with the push
111 * mechanism. This is often correlated with reladdr loads where
112 * we should probably be using a pull mechanism anyway to avoid
113 * excessive reading. However, the pull mechanism is slow in
114 * general. So, we try to allocate as many non-reladdr-loaded
115 * constants through the push buffer as we can before giving up.
117 memset(c
->constant_map
, -1, c
->vp
->program
.Base
.Parameters
->NumParameters
);
119 i
< c
->vp
->program
.Base
.NumInstructions
&& constant
< max_constant
;
121 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[i
];
124 for (arg
= 0; arg
< 3 && constant
< max_constant
; arg
++) {
125 if ((inst
->SrcReg
[arg
].File
!= PROGRAM_STATE_VAR
&&
126 inst
->SrcReg
[arg
].File
!= PROGRAM_CONSTANT
&&
127 inst
->SrcReg
[arg
].File
!= PROGRAM_UNIFORM
&&
128 inst
->SrcReg
[arg
].File
!= PROGRAM_ENV_PARAM
&&
129 inst
->SrcReg
[arg
].File
!= PROGRAM_LOCAL_PARAM
) ||
130 inst
->SrcReg
[arg
].RelAddr
)
133 if (c
->constant_map
[inst
->SrcReg
[arg
].Index
] == -1) {
134 c
->constant_map
[inst
->SrcReg
[arg
].Index
] = constant
++;
139 for (i
= 0; i
< constant
; i
++) {
140 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2,
144 reg
+= (constant
+ 1) / 2;
145 c
->prog_data
.curb_read_length
= reg
- 1;
146 /* XXX 0 causes a bug elsewhere... */
147 c
->prog_data
.nr_params
= MAX2(constant
* 4, 4);
150 /* use a section of the GRF for constants */
151 GLuint nr_params
= c
->vp
->program
.Base
.Parameters
->NumParameters
;
152 for (i
= 0; i
< nr_params
; i
++) {
153 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2, (i
%2) * 4), 0, 4, 1);
155 reg
+= (nr_params
+ 1) / 2;
156 c
->prog_data
.curb_read_length
= reg
- 1;
158 c
->prog_data
.nr_params
= nr_params
* 4;
161 /* Allocate input regs:
164 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
165 if (c
->prog_data
.inputs_read
& (1 << i
)) {
167 c
->regs
[PROGRAM_INPUT
][i
] = brw_vec8_grf(reg
, 0);
171 /* If there are no inputs, we'll still be reading one attribute's worth
172 * because it's required -- see urb_read_length setting.
174 if (c
->nr_inputs
== 0)
177 /* Allocate outputs. The non-position outputs go straight into message regs.
180 c
->first_output
= reg
;
181 c
->first_overflow_output
= 0;
183 if (intel
->is_ironlake
)
188 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
189 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(i
)) {
191 assert(i
< Elements(c
->regs
[PROGRAM_OUTPUT
]));
192 if (i
== VERT_RESULT_HPOS
) {
193 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
196 else if (i
== VERT_RESULT_PSIZ
) {
197 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
199 mrf
++; /* just a placeholder? XXX fix later stages & remove this */
203 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_message_reg(mrf
);
207 /* too many vertex results to fit in MRF, use GRF for overflow */
208 if (!c
->first_overflow_output
)
209 c
->first_overflow_output
= i
;
210 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
217 /* Allocate program temporaries:
219 for (i
= 0; i
< c
->vp
->program
.Base
.NumTemporaries
; i
++) {
220 c
->regs
[PROGRAM_TEMPORARY
][i
] = brw_vec8_grf(reg
, 0);
224 /* Address reg(s). Don't try to use the internal address reg until
227 for (i
= 0; i
< c
->vp
->program
.Base
.NumAddressRegs
; i
++) {
228 c
->regs
[PROGRAM_ADDRESS
][i
] = brw_reg(BRW_GENERAL_REGISTER_FILE
,
232 BRW_VERTICAL_STRIDE_8
,
234 BRW_HORIZONTAL_STRIDE_1
,
240 if (c
->vp
->use_const_buffer
) {
241 for (i
= 0; i
< 3; i
++) {
242 c
->current_const
[i
].index
= -1;
243 c
->current_const
[i
].reg
= brw_vec8_grf(reg
, 0);
248 for (i
= 0; i
< 128; i
++) {
249 if (c
->output_regs
[i
].used_in_src
) {
250 c
->output_regs
[i
].reg
= brw_vec8_grf(reg
, 0);
255 if (c
->needs_stack
) {
256 c
->stack
= brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, reg
, 0);
260 /* Some opcodes need an internal temporary:
263 c
->last_tmp
= reg
; /* for allocation purposes */
265 /* Each input reg holds data from two vertices. The
266 * urb_read_length is the number of registers read from *each*
267 * vertex urb, so is half the amount:
269 c
->prog_data
.urb_read_length
= (c
->nr_inputs
+ 1) / 2;
270 /* Setting this field to 0 leads to undefined behavior according to the
271 * the VS_STATE docs. Our VUEs will always have at least one attribute
272 * sitting in them, even if it's padding.
274 if (c
->prog_data
.urb_read_length
== 0)
275 c
->prog_data
.urb_read_length
= 1;
277 /* The VS VUEs are shared by VF (outputting our inputs) and VS, so size
278 * them to fit the biggest thing they need to.
280 attributes_in_vue
= MAX2(c
->nr_outputs
, c
->nr_inputs
);
282 if (intel
->is_ironlake
)
283 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 6 + 3) / 4;
285 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 2 + 3) / 4;
287 c
->prog_data
.total_grf
= reg
;
289 if (INTEL_DEBUG
& DEBUG_VS
) {
290 printf("%s NumAddrRegs %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumAddressRegs
);
291 printf("%s NumTemps %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumTemporaries
);
292 printf("%s reg = %d\n", __FUNCTION__
, reg
);
298 * If an instruction uses a temp reg both as a src and the dest, we
299 * sometimes need to allocate an intermediate temporary.
301 static void unalias1( struct brw_vs_compile
*c
,
304 void (*func
)( struct brw_vs_compile
*,
308 if (dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) {
309 struct brw_compile
*p
= &c
->func
;
310 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
312 brw_MOV(p
, dst
, tmp
);
322 * Checkes if 2-operand instruction needs an intermediate temporary.
324 static void unalias2( struct brw_vs_compile
*c
,
328 void (*func
)( struct brw_vs_compile
*,
333 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
334 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
)) {
335 struct brw_compile
*p
= &c
->func
;
336 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
337 func(c
, tmp
, arg0
, arg1
);
338 brw_MOV(p
, dst
, tmp
);
342 func(c
, dst
, arg0
, arg1
);
348 * Checkes if 3-operand instruction needs an intermediate temporary.
350 static void unalias3( struct brw_vs_compile
*c
,
355 void (*func
)( struct brw_vs_compile
*,
361 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
362 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
) ||
363 (dst
.file
== arg2
.file
&& dst
.nr
== arg2
.nr
)) {
364 struct brw_compile
*p
= &c
->func
;
365 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
366 func(c
, tmp
, arg0
, arg1
, arg2
);
367 brw_MOV(p
, dst
, tmp
);
371 func(c
, dst
, arg0
, arg1
, arg2
);
375 static void emit_sop( struct brw_vs_compile
*c
,
381 struct brw_compile
*p
= &c
->func
;
383 brw_MOV(p
, dst
, brw_imm_f(0.0f
));
384 brw_CMP(p
, brw_null_reg(), cond
, arg0
, arg1
);
385 brw_MOV(p
, dst
, brw_imm_f(1.0f
));
386 brw_set_predicate_control_flag_value(p
, 0xff);
389 static void emit_seq( struct brw_vs_compile
*c
,
392 struct brw_reg arg1
)
394 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_EQ
);
397 static void emit_sne( struct brw_vs_compile
*c
,
400 struct brw_reg arg1
)
402 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_NEQ
);
404 static void emit_slt( struct brw_vs_compile
*c
,
407 struct brw_reg arg1
)
409 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_L
);
412 static void emit_sle( struct brw_vs_compile
*c
,
415 struct brw_reg arg1
)
417 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_LE
);
420 static void emit_sgt( struct brw_vs_compile
*c
,
423 struct brw_reg arg1
)
425 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_G
);
428 static void emit_sge( struct brw_vs_compile
*c
,
431 struct brw_reg arg1
)
433 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_GE
);
436 static void emit_cmp( struct brw_compile
*p
,
440 struct brw_reg arg2
)
442 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, brw_imm_f(0));
443 brw_SEL(p
, dst
, arg1
, arg2
);
444 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
447 static void emit_max( struct brw_compile
*p
,
450 struct brw_reg arg1
)
452 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
453 brw_SEL(p
, dst
, arg1
, arg0
);
454 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
457 static void emit_min( struct brw_compile
*p
,
460 struct brw_reg arg1
)
462 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
463 brw_SEL(p
, dst
, arg0
, arg1
);
464 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
468 static void emit_math1( struct brw_vs_compile
*c
,
474 /* There are various odd behaviours with SEND on the simulator. In
475 * addition there are documented issues with the fact that the GEN4
476 * processor doesn't do dependency control properly on SEND
477 * results. So, on balance, this kludge to get around failures
478 * with writemasked math results looks like it might be necessary
479 * whether that turns out to be a simulator bug or not:
481 struct brw_compile
*p
= &c
->func
;
482 struct brw_reg tmp
= dst
;
483 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
484 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
492 BRW_MATH_SATURATE_NONE
,
495 BRW_MATH_DATA_SCALAR
,
499 brw_MOV(p
, dst
, tmp
);
505 static void emit_math2( struct brw_vs_compile
*c
,
512 struct brw_compile
*p
= &c
->func
;
513 struct brw_reg tmp
= dst
;
514 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
515 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
520 brw_MOV(p
, brw_message_reg(3), arg1
);
525 BRW_MATH_SATURATE_NONE
,
528 BRW_MATH_DATA_SCALAR
,
532 brw_MOV(p
, dst
, tmp
);
538 static void emit_exp_noalias( struct brw_vs_compile
*c
,
540 struct brw_reg arg0
)
542 struct brw_compile
*p
= &c
->func
;
545 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
) {
546 struct brw_reg tmp
= get_tmp(c
);
547 struct brw_reg tmp_d
= retype(tmp
, BRW_REGISTER_TYPE_D
);
549 /* tmp_d = floor(arg0.x) */
550 brw_RNDD(p
, tmp_d
, brw_swizzle1(arg0
, 0));
552 /* result[0] = 2.0 ^ tmp */
554 /* Adjust exponent for floating point:
557 brw_ADD(p
, brw_writemask(tmp_d
, WRITEMASK_X
), tmp_d
, brw_imm_d(127));
559 /* Install exponent and sign.
560 * Excess drops off the edge:
562 brw_SHL(p
, brw_writemask(retype(dst
, BRW_REGISTER_TYPE_D
), WRITEMASK_X
),
563 tmp_d
, brw_imm_d(23));
568 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
) {
569 /* result[1] = arg0.x - floor(arg0.x) */
570 brw_FRC(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
, 0));
573 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
574 /* As with the LOG instruction, we might be better off just
575 * doing a taylor expansion here, seeing as we have to do all
578 * If mathbox partial precision is too low, consider also:
579 * result[3] = result[0] * EXP(result[1])
582 BRW_MATH_FUNCTION_EXP
,
583 brw_writemask(dst
, WRITEMASK_Z
),
584 brw_swizzle1(arg0
, 0),
585 BRW_MATH_PRECISION_FULL
);
588 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
589 /* result[3] = 1.0; */
590 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), brw_imm_f(1));
595 static void emit_log_noalias( struct brw_vs_compile
*c
,
597 struct brw_reg arg0
)
599 struct brw_compile
*p
= &c
->func
;
600 struct brw_reg tmp
= dst
;
601 struct brw_reg tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
602 struct brw_reg arg0_ud
= retype(arg0
, BRW_REGISTER_TYPE_UD
);
603 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
604 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
608 tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
611 /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt
614 * These almost look likey they could be joined up, but not really
617 * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127
618 * result[1].i = (x.i & ((1<<23)-1) + (127<<23)
620 if (dst
.dw1
.bits
.writemask
& WRITEMASK_XZ
) {
622 brw_writemask(tmp_ud
, WRITEMASK_X
),
623 brw_swizzle1(arg0_ud
, 0),
624 brw_imm_ud((1U<<31)-1));
627 brw_writemask(tmp_ud
, WRITEMASK_X
),
632 brw_writemask(tmp
, WRITEMASK_X
),
633 retype(tmp_ud
, BRW_REGISTER_TYPE_D
), /* does it matter? */
637 if (dst
.dw1
.bits
.writemask
& WRITEMASK_YZ
) {
639 brw_writemask(tmp_ud
, WRITEMASK_Y
),
640 brw_swizzle1(arg0_ud
, 0),
641 brw_imm_ud((1<<23)-1));
644 brw_writemask(tmp_ud
, WRITEMASK_Y
),
646 brw_imm_ud(127<<23));
649 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
650 /* result[2] = result[0] + LOG2(result[1]); */
652 /* Why bother? The above is just a hint how to do this with a
653 * taylor series. Maybe we *should* use a taylor series as by
654 * the time all the above has been done it's almost certainly
655 * quicker than calling the mathbox, even with low precision.
658 * - result[0] + mathbox.LOG2(result[1])
659 * - mathbox.LOG2(arg0.x)
660 * - result[0] + inline_taylor_approx(result[1])
663 BRW_MATH_FUNCTION_LOG
,
664 brw_writemask(tmp
, WRITEMASK_Z
),
665 brw_swizzle1(tmp
, 1),
666 BRW_MATH_PRECISION_FULL
);
669 brw_writemask(tmp
, WRITEMASK_Z
),
670 brw_swizzle1(tmp
, 2),
671 brw_swizzle1(tmp
, 0));
674 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
675 /* result[3] = 1.0; */
676 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_W
), brw_imm_f(1));
680 brw_MOV(p
, dst
, tmp
);
686 /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
688 static void emit_dst_noalias( struct brw_vs_compile
*c
,
693 struct brw_compile
*p
= &c
->func
;
695 /* There must be a better way to do this:
697 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
)
698 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_X
), brw_imm_f(1.0));
699 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
)
700 brw_MUL(p
, brw_writemask(dst
, WRITEMASK_Y
), arg0
, arg1
);
701 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
)
702 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Z
), arg0
);
703 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
)
704 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), arg1
);
708 static void emit_xpd( struct brw_compile
*p
,
713 brw_MUL(p
, brw_null_reg(), brw_swizzle(t
, 1,2,0,3), brw_swizzle(u
,2,0,1,3));
714 brw_MAC(p
, dst
, negate(brw_swizzle(t
, 2,0,1,3)), brw_swizzle(u
,1,2,0,3));
718 static void emit_lit_noalias( struct brw_vs_compile
*c
,
720 struct brw_reg arg0
)
722 struct brw_compile
*p
= &c
->func
;
723 struct brw_instruction
*if_insn
;
724 struct brw_reg tmp
= dst
;
725 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
730 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_YZ
), brw_imm_f(0));
731 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_XW
), brw_imm_f(1));
733 /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order
734 * to get all channels active inside the IF. In the clipping code
735 * we run with NoMask, so it's not an option and we can use
736 * BRW_EXECUTE_1 for all comparisions.
738 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,0), brw_imm_f(0));
739 if_insn
= brw_IF(p
, BRW_EXECUTE_8
);
741 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
,0));
743 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,1), brw_imm_f(0));
744 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_Z
), brw_swizzle1(arg0
,1));
745 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
748 BRW_MATH_FUNCTION_POW
,
749 brw_writemask(dst
, WRITEMASK_Z
),
750 brw_swizzle1(tmp
, 2),
751 brw_swizzle1(arg0
, 3),
752 BRW_MATH_PRECISION_PARTIAL
);
755 brw_ENDIF(p
, if_insn
);
760 static void emit_lrp_noalias(struct brw_vs_compile
*c
,
766 struct brw_compile
*p
= &c
->func
;
768 brw_ADD(p
, dst
, negate(arg0
), brw_imm_f(1.0));
769 brw_MUL(p
, brw_null_reg(), dst
, arg2
);
770 brw_MAC(p
, dst
, arg0
, arg1
);
773 /** 3 or 4-component vector normalization */
774 static void emit_nrm( struct brw_vs_compile
*c
,
779 struct brw_compile
*p
= &c
->func
;
780 struct brw_reg tmp
= get_tmp(c
);
782 /* tmp = dot(arg0, arg0) */
784 brw_DP3(p
, tmp
, arg0
, arg0
);
786 brw_DP4(p
, tmp
, arg0
, arg0
);
788 /* tmp = 1 / sqrt(tmp) */
789 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, tmp
, tmp
, BRW_MATH_PRECISION_FULL
);
791 /* dst = arg0 * tmp */
792 brw_MUL(p
, dst
, arg0
, tmp
);
798 static struct brw_reg
799 get_constant(struct brw_vs_compile
*c
,
800 const struct prog_instruction
*inst
,
803 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
804 struct brw_compile
*p
= &c
->func
;
805 struct brw_reg const_reg
= c
->current_const
[argIndex
].reg
;
807 assert(argIndex
< 3);
809 if (c
->current_const
[argIndex
].index
!= src
->Index
) {
810 struct brw_reg addrReg
= c
->regs
[PROGRAM_ADDRESS
][0];
812 /* Keep track of the last constant loaded in this slot, for reuse. */
813 c
->current_const
[argIndex
].index
= src
->Index
;
816 printf(" fetch const[%d] for arg %d into reg %d\n",
817 src
->Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
819 /* need to fetch the constant now */
821 const_reg
, /* writeback dest */
823 0, /* relative indexing? */
824 addrReg
, /* address register */
825 16 * src
->Index
, /* byte offset */
826 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
830 /* replicate lower four floats into upper half (to get XYZWXYZW) */
831 const_reg
= stride(const_reg
, 0, 4, 0);
837 static struct brw_reg
838 get_reladdr_constant(struct brw_vs_compile
*c
,
839 const struct prog_instruction
*inst
,
842 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
843 struct brw_compile
*p
= &c
->func
;
844 struct brw_reg const_reg
= c
->current_const
[argIndex
].reg
;
845 struct brw_reg const2_reg
;
846 struct brw_reg addrReg
= c
->regs
[PROGRAM_ADDRESS
][0];
848 assert(argIndex
< 3);
850 /* Can't reuse a reladdr constant load. */
851 c
->current_const
[argIndex
].index
= -1;
854 printf(" fetch const[a0.x+%d] for arg %d into reg %d\n",
855 src
->Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
858 /* fetch the first vec4 */
860 const_reg
, /* writeback dest */
862 1, /* relative indexing? */
863 addrReg
, /* address register */
864 16 * src
->Index
, /* byte offset */
865 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
868 const2_reg
= get_tmp(c
);
870 /* use upper half of address reg for second read */
871 addrReg
= stride(addrReg
, 0, 4, 0);
875 const2_reg
, /* writeback dest */
877 1, /* relative indexing? */
878 addrReg
, /* address register */
879 16 * src
->Index
, /* byte offset */
880 SURF_INDEX_VERT_CONST_BUFFER
883 /* merge the two Owords into the constant register */
884 /* const_reg[7..4] = const2_reg[7..4] */
886 suboffset(stride(const_reg
, 0, 4, 1), 4),
887 suboffset(stride(const2_reg
, 0, 4, 1), 4));
888 release_tmp(c
, const2_reg
);
895 /* TODO: relative addressing!
897 static struct brw_reg
get_reg( struct brw_vs_compile
*c
,
898 gl_register_file file
,
902 case PROGRAM_TEMPORARY
:
905 assert(c
->regs
[file
][index
].nr
!= 0);
906 return c
->regs
[file
][index
];
907 case PROGRAM_STATE_VAR
:
908 case PROGRAM_CONSTANT
:
909 case PROGRAM_UNIFORM
:
910 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
911 return c
->regs
[PROGRAM_STATE_VAR
][index
];
912 case PROGRAM_ADDRESS
:
914 return c
->regs
[file
][index
];
916 case PROGRAM_UNDEFINED
: /* undef values */
917 return brw_null_reg();
919 case PROGRAM_LOCAL_PARAM
:
920 case PROGRAM_ENV_PARAM
:
921 case PROGRAM_WRITE_ONLY
:
924 return brw_null_reg();
930 * Indirect addressing: get reg[[arg] + offset].
932 static struct brw_reg
deref( struct brw_vs_compile
*c
,
936 struct brw_compile
*p
= &c
->func
;
937 struct brw_reg tmp
= vec4(get_tmp(c
));
938 struct brw_reg addr_reg
= c
->regs
[PROGRAM_ADDRESS
][0];
939 struct brw_reg vp_address
= retype(vec1(addr_reg
), BRW_REGISTER_TYPE_UW
);
940 GLuint byte_offset
= arg
.nr
* 32 + arg
.subnr
+ offset
* 16;
941 struct brw_reg indirect
= brw_vec4_indirect(0,0);
944 brw_push_insn_state(p
);
945 brw_set_access_mode(p
, BRW_ALIGN_1
);
947 /* This is pretty clunky - load the address register twice and
948 * fetch each 4-dword value in turn. There must be a way to do
949 * this in a single pass, but I couldn't get it to work.
951 brw_ADD(p
, brw_address_reg(0), vp_address
, brw_imm_d(byte_offset
));
952 brw_MOV(p
, tmp
, indirect
);
954 brw_ADD(p
, brw_address_reg(0), suboffset(vp_address
, 8), brw_imm_d(byte_offset
));
955 brw_MOV(p
, suboffset(tmp
, 4), indirect
);
957 brw_pop_insn_state(p
);
960 /* NOTE: tmp not released */
966 * Get brw reg corresponding to the instruction's [argIndex] src reg.
967 * TODO: relative addressing!
969 static struct brw_reg
970 get_src_reg( struct brw_vs_compile
*c
,
971 const struct prog_instruction
*inst
,
974 const GLuint file
= inst
->SrcReg
[argIndex
].File
;
975 const GLint index
= inst
->SrcReg
[argIndex
].Index
;
976 const GLboolean relAddr
= inst
->SrcReg
[argIndex
].RelAddr
;
979 case PROGRAM_TEMPORARY
:
983 return deref(c
, c
->regs
[file
][0], index
);
986 assert(c
->regs
[file
][index
].nr
!= 0);
987 return c
->regs
[file
][index
];
990 case PROGRAM_STATE_VAR
:
991 case PROGRAM_CONSTANT
:
992 case PROGRAM_UNIFORM
:
993 case PROGRAM_ENV_PARAM
:
994 case PROGRAM_LOCAL_PARAM
:
995 if (c
->vp
->use_const_buffer
) {
996 if (!relAddr
&& c
->constant_map
[index
] != -1) {
997 assert(c
->regs
[PROGRAM_STATE_VAR
][c
->constant_map
[index
]].nr
!= 0);
998 return c
->regs
[PROGRAM_STATE_VAR
][c
->constant_map
[index
]];
1000 return get_reladdr_constant(c
, inst
, argIndex
);
1002 return get_constant(c
, inst
, argIndex
);
1005 return deref(c
, c
->regs
[PROGRAM_STATE_VAR
][0], index
);
1008 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
1009 return c
->regs
[PROGRAM_STATE_VAR
][index
];
1011 case PROGRAM_ADDRESS
:
1013 return c
->regs
[file
][index
];
1015 case PROGRAM_UNDEFINED
:
1016 /* this is a normal case since we loop over all three src args */
1017 return brw_null_reg();
1019 case PROGRAM_WRITE_ONLY
:
1022 return brw_null_reg();
1027 static void emit_arl( struct brw_vs_compile
*c
,
1029 struct brw_reg arg0
)
1031 struct brw_compile
*p
= &c
->func
;
1032 struct brw_reg tmp
= dst
;
1033 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
1038 brw_RNDD(p
, tmp
, arg0
); /* tmp = round(arg0) */
1039 brw_MUL(p
, dst
, tmp
, brw_imm_d(16)); /* dst = tmp * 16 */
1042 release_tmp(c
, tmp
);
1047 * Return the brw reg for the given instruction's src argument.
1048 * Will return mangled results for SWZ op. The emit_swz() function
1049 * ignores this result and recalculates taking extended swizzles into
1052 static struct brw_reg
get_arg( struct brw_vs_compile
*c
,
1053 const struct prog_instruction
*inst
,
1056 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
1059 if (src
->File
== PROGRAM_UNDEFINED
)
1060 return brw_null_reg();
1062 reg
= get_src_reg(c
, inst
, argIndex
);
1064 /* Convert 3-bit swizzle to 2-bit.
1066 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(GET_SWZ(src
->Swizzle
, 0),
1067 GET_SWZ(src
->Swizzle
, 1),
1068 GET_SWZ(src
->Swizzle
, 2),
1069 GET_SWZ(src
->Swizzle
, 3));
1071 /* Note this is ok for non-swizzle instructions:
1073 reg
.negate
= src
->Negate
? 1 : 0;
1080 * Get brw register for the given program dest register.
1082 static struct brw_reg
get_dst( struct brw_vs_compile
*c
,
1083 struct prog_dst_register dst
)
1088 case PROGRAM_TEMPORARY
:
1089 case PROGRAM_OUTPUT
:
1090 assert(c
->regs
[dst
.File
][dst
.Index
].nr
!= 0);
1091 reg
= c
->regs
[dst
.File
][dst
.Index
];
1093 case PROGRAM_ADDRESS
:
1094 assert(dst
.Index
== 0);
1095 reg
= c
->regs
[dst
.File
][dst
.Index
];
1097 case PROGRAM_UNDEFINED
:
1098 /* we may hit this for OPCODE_END, OPCODE_KIL, etc */
1099 reg
= brw_null_reg();
1103 reg
= brw_null_reg();
1106 reg
.dw1
.bits
.writemask
= dst
.WriteMask
;
1112 static void emit_swz( struct brw_vs_compile
*c
,
1114 const struct prog_instruction
*inst
)
1116 const GLuint argIndex
= 0;
1117 const struct prog_src_register src
= inst
->SrcReg
[argIndex
];
1118 struct brw_compile
*p
= &c
->func
;
1119 GLuint zeros_mask
= 0;
1120 GLuint ones_mask
= 0;
1121 GLuint src_mask
= 0;
1123 GLboolean need_tmp
= (src
.Negate
&&
1124 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
1125 struct brw_reg tmp
= dst
;
1131 for (i
= 0; i
< 4; i
++) {
1132 if (dst
.dw1
.bits
.writemask
& (1<<i
)) {
1133 GLubyte s
= GET_SWZ(src
.Swizzle
, i
);
1152 /* Do src first, in case dst aliases src:
1155 struct brw_reg arg0
;
1157 arg0
= get_src_reg(c
, inst
, argIndex
);
1159 arg0
= brw_swizzle(arg0
,
1160 src_swz
[0], src_swz
[1],
1161 src_swz
[2], src_swz
[3]);
1163 brw_MOV(p
, brw_writemask(tmp
, src_mask
), arg0
);
1167 brw_MOV(p
, brw_writemask(tmp
, zeros_mask
), brw_imm_f(0));
1170 brw_MOV(p
, brw_writemask(tmp
, ones_mask
), brw_imm_f(1));
1173 brw_MOV(p
, brw_writemask(tmp
, src
.Negate
), negate(tmp
));
1176 brw_MOV(p
, dst
, tmp
);
1177 release_tmp(c
, tmp
);
1183 * Post-vertex-program processing. Send the results to the URB.
1185 static void emit_vertex_write( struct brw_vs_compile
*c
)
1187 struct brw_compile
*p
= &c
->func
;
1188 struct brw_context
*brw
= p
->brw
;
1189 struct intel_context
*intel
= &brw
->intel
;
1190 struct brw_reg m0
= brw_message_reg(0);
1191 struct brw_reg pos
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_HPOS
];
1194 GLuint len_vertext_header
= 2;
1196 if (c
->key
.copy_edgeflag
) {
1198 get_reg(c
, PROGRAM_OUTPUT
, VERT_RESULT_EDGE
),
1199 get_reg(c
, PROGRAM_INPUT
, VERT_ATTRIB_EDGEFLAG
));
1202 /* Build ndc coords */
1204 /* ndc = 1.0 / pos.w */
1205 emit_math1(c
, BRW_MATH_FUNCTION_INV
, ndc
, brw_swizzle1(pos
, 3), BRW_MATH_PRECISION_FULL
);
1206 /* ndc.xyz = pos * ndc */
1207 brw_MUL(p
, brw_writemask(ndc
, WRITEMASK_XYZ
), pos
, ndc
);
1209 /* Update the header for point size, user clipping flags, and -ve rhw
1212 if ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
1213 c
->key
.nr_userclip
|| brw
->has_negative_rhw_bug
)
1215 struct brw_reg header1
= retype(get_tmp(c
), BRW_REGISTER_TYPE_UD
);
1218 brw_MOV(p
, header1
, brw_imm_ud(0));
1220 brw_set_access_mode(p
, BRW_ALIGN_16
);
1222 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1223 struct brw_reg psiz
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_PSIZ
];
1224 brw_MUL(p
, brw_writemask(header1
, WRITEMASK_W
), brw_swizzle1(psiz
, 0), brw_imm_f(1<<11));
1225 brw_AND(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(0x7ff<<8));
1228 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1229 brw_set_conditionalmod(p
, BRW_CONDITIONAL_L
);
1230 brw_DP4(p
, brw_null_reg(), pos
, c
->userplane
[i
]);
1231 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<i
));
1232 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1235 /* i965 clipping workaround:
1236 * 1) Test for -ve rhw
1238 * set ndc = (0,0,0,0)
1241 * Later, clipping will detect ucp[6] and ensure the primitive is
1242 * clipped against all fixed planes.
1244 if (brw
->has_negative_rhw_bug
) {
1246 vec8(brw_null_reg()),
1248 brw_swizzle1(ndc
, 3),
1251 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1252 brw_MOV(p
, ndc
, brw_imm_f(0));
1253 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1256 brw_set_access_mode(p
, BRW_ALIGN_1
); /* why? */
1257 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), header1
);
1258 brw_set_access_mode(p
, BRW_ALIGN_16
);
1260 release_tmp(c
, header1
);
1263 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
1266 /* Emit the (interleaved) headers for the two vertices - an 8-reg
1267 * of zeros followed by two sets of NDC coordinates:
1269 brw_set_access_mode(p
, BRW_ALIGN_1
);
1270 brw_MOV(p
, offset(m0
, 2), ndc
);
1272 if (intel
->is_ironlake
) {
1273 /* There are 20 DWs (D0-D19) in VUE vertex header on Ironlake */
1274 brw_MOV(p
, offset(m0
, 3), pos
); /* a portion of vertex header */
1275 /* m4, m5 contain the distances from vertex to the user clip planeXXX.
1276 * Seems it is useless for us.
1277 * m6 is used for aligning, so that the remainder of vertex element is
1280 brw_MOV(p
, offset(m0
, 7), pos
); /* the remainder of vertex element */
1281 len_vertext_header
= 6;
1283 brw_MOV(p
, offset(m0
, 3), pos
);
1284 len_vertext_header
= 2;
1287 eot
= (c
->first_overflow_output
== 0);
1290 brw_null_reg(), /* dest */
1291 0, /* starting mrf reg nr */
1295 MIN2(c
->nr_outputs
+ 1 + len_vertext_header
, (BRW_MAX_MRF
-1)), /* msg len */
1296 0, /* response len */
1298 eot
, /* writes complete */
1299 0, /* urb destination offset */
1300 BRW_URB_SWIZZLE_INTERLEAVE
);
1302 if (c
->first_overflow_output
> 0) {
1303 /* Not all of the vertex outputs/results fit into the MRF.
1304 * Move the overflowed attributes from the GRF to the MRF and
1305 * issue another brw_urb_WRITE().
1307 /* XXX I'm not 100% sure about which MRF regs to use here. Starting
1311 for (i
= c
->first_overflow_output
; i
< VERT_RESULT_MAX
; i
++) {
1312 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(i
)) {
1313 /* move from GRF to MRF */
1314 brw_MOV(p
, brw_message_reg(4+mrf
), c
->regs
[PROGRAM_OUTPUT
][i
]);
1320 brw_null_reg(), /* dest */
1321 4, /* starting mrf reg nr */
1325 mrf
+1, /* msg len */
1326 0, /* response len */
1328 1, /* writes complete */
1329 BRW_MAX_MRF
-1, /* urb destination offset */
1330 BRW_URB_SWIZZLE_INTERLEAVE
);
1336 * Called after code generation to resolve subroutine calls and the
1338 * \param end_inst points to brw code for END instruction
1339 * \param last_inst points to last instruction emitted before vertex write
1342 post_vs_emit( struct brw_vs_compile
*c
,
1343 struct brw_instruction
*end_inst
,
1344 struct brw_instruction
*last_inst
)
1348 brw_resolve_cals(&c
->func
);
1350 /* patch up the END code to jump past subroutines, etc */
1351 offset
= last_inst
- end_inst
;
1353 brw_set_src1(end_inst
, brw_imm_d(offset
* 16));
1355 end_inst
->header
.opcode
= BRW_OPCODE_NOP
;
1360 accumulator_contains(struct brw_vs_compile
*c
, struct brw_reg val
)
1362 struct brw_compile
*p
= &c
->func
;
1363 struct brw_instruction
*prev_insn
= &p
->store
[p
->nr_insn
- 1];
1365 if (p
->nr_insn
== 0)
1368 if (val
.address_mode
!= BRW_ADDRESS_DIRECT
)
1371 switch (prev_insn
->header
.opcode
) {
1372 case BRW_OPCODE_MOV
:
1373 case BRW_OPCODE_MAC
:
1374 case BRW_OPCODE_MUL
:
1375 if (prev_insn
->header
.access_mode
== BRW_ALIGN_16
&&
1376 prev_insn
->header
.execution_size
== val
.width
&&
1377 prev_insn
->bits1
.da1
.dest_reg_file
== val
.file
&&
1378 prev_insn
->bits1
.da1
.dest_reg_type
== val
.type
&&
1379 prev_insn
->bits1
.da1
.dest_address_mode
== val
.address_mode
&&
1380 prev_insn
->bits1
.da1
.dest_reg_nr
== val
.nr
&&
1381 prev_insn
->bits1
.da16
.dest_subreg_nr
== val
.subnr
/ 16 &&
1382 prev_insn
->bits1
.da16
.dest_writemask
== 0xf)
1392 get_predicate(const struct prog_instruction
*inst
)
1394 if (inst
->DstReg
.CondMask
== COND_TR
)
1395 return BRW_PREDICATE_NONE
;
1397 /* All of GLSL only produces predicates for COND_NE and one channel per
1398 * vector. Fail badly if someone starts doing something else, as it might
1399 * mean infinite looping or something.
1401 * We'd like to support all the condition codes, but our hardware doesn't
1402 * quite match the Mesa IR, which is modeled after the NV extensions. For
1403 * those, the instruction may update the condition codes or not, then any
1404 * later instruction may use one of those condition codes. For gen4, the
1405 * instruction may update the flags register based on one of the condition
1406 * codes output by the instruction, and then further instructions may
1407 * predicate on that. We can probably support this, but it won't
1408 * necessarily be easy.
1410 assert(inst
->DstReg
.CondMask
== COND_NE
);
1412 switch (inst
->DstReg
.CondSwizzle
) {
1414 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1416 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1418 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1420 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1422 _mesa_problem(NULL
, "Unexpected predicate: 0x%08x\n",
1423 inst
->DstReg
.CondMask
);
1424 return BRW_PREDICATE_NORMAL
;
1428 /* Emit the vertex program instructions here.
1430 void brw_vs_emit(struct brw_vs_compile
*c
)
1432 #define MAX_IF_DEPTH 32
1433 #define MAX_LOOP_DEPTH 32
1434 struct brw_compile
*p
= &c
->func
;
1435 struct brw_context
*brw
= p
->brw
;
1436 struct intel_context
*intel
= &brw
->intel
;
1437 const GLuint nr_insns
= c
->vp
->program
.Base
.NumInstructions
;
1438 GLuint insn
, if_depth
= 0, loop_depth
= 0;
1439 GLuint end_offset
= 0;
1440 struct brw_instruction
*end_inst
, *last_inst
;
1441 struct brw_instruction
*if_inst
[MAX_IF_DEPTH
], *loop_inst
[MAX_LOOP_DEPTH
] = { 0 };
1442 const struct brw_indirect stack_index
= brw_indirect(0, 0);
1446 if (INTEL_DEBUG
& DEBUG_VS
) {
1447 printf("vs-mesa:\n");
1448 _mesa_print_program(&c
->vp
->program
.Base
);
1452 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1453 brw_set_access_mode(p
, BRW_ALIGN_16
);
1455 for (insn
= 0; insn
< nr_insns
; insn
++) {
1457 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1459 /* Message registers can't be read, so copy the output into GRF
1460 * register if they are used in source registers
1462 for (i
= 0; i
< 3; i
++) {
1463 struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1464 GLuint index
= src
->Index
;
1465 GLuint file
= src
->File
;
1466 if (file
== PROGRAM_OUTPUT
&& index
!= VERT_RESULT_HPOS
)
1467 c
->output_regs
[index
].used_in_src
= GL_TRUE
;
1470 switch (inst
->Opcode
) {
1473 c
->needs_stack
= GL_TRUE
;
1480 /* Static register allocation
1482 brw_vs_alloc_regs(c
);
1485 brw_MOV(p
, get_addr_reg(stack_index
), brw_address(c
->stack
));
1487 for (insn
= 0; insn
< nr_insns
; insn
++) {
1489 const struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1490 struct brw_reg args
[3], dst
;
1494 printf("%d: ", insn
);
1495 _mesa_print_instruction(inst
);
1498 /* Get argument regs. SWZ is special and does this itself.
1500 if (inst
->Opcode
!= OPCODE_SWZ
)
1501 for (i
= 0; i
< 3; i
++) {
1502 const struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1505 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1506 args
[i
] = c
->output_regs
[index
].reg
;
1508 args
[i
] = get_arg(c
, inst
, i
);
1511 /* Get dest regs. Note that it is possible for a reg to be both
1512 * dst and arg, given the static allocation of registers. So
1513 * care needs to be taken emitting multi-operation instructions.
1515 index
= inst
->DstReg
.Index
;
1516 file
= inst
->DstReg
.File
;
1517 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1518 dst
= c
->output_regs
[index
].reg
;
1520 dst
= get_dst(c
, inst
->DstReg
);
1522 if (inst
->SaturateMode
!= SATURATE_OFF
) {
1523 _mesa_problem(NULL
, "Unsupported saturate %d in vertex shader",
1524 inst
->SaturateMode
);
1527 switch (inst
->Opcode
) {
1529 brw_MOV(p
, dst
, brw_abs(args
[0]));
1532 brw_ADD(p
, dst
, args
[0], args
[1]);
1535 emit_math1(c
, BRW_MATH_FUNCTION_COS
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1538 brw_DP3(p
, dst
, args
[0], args
[1]);
1541 brw_DP4(p
, dst
, args
[0], args
[1]);
1544 brw_DPH(p
, dst
, args
[0], args
[1]);
1547 emit_nrm(c
, dst
, args
[0], 3);
1550 emit_nrm(c
, dst
, args
[0], 4);
1553 unalias2(c
, dst
, args
[0], args
[1], emit_dst_noalias
);
1556 unalias1(c
, dst
, args
[0], emit_exp_noalias
);
1559 emit_math1(c
, BRW_MATH_FUNCTION_EXP
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1562 emit_arl(c
, dst
, args
[0]);
1565 brw_RNDD(p
, dst
, args
[0]);
1568 brw_FRC(p
, dst
, args
[0]);
1571 unalias1(c
, dst
, args
[0], emit_log_noalias
);
1574 emit_math1(c
, BRW_MATH_FUNCTION_LOG
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1577 unalias1(c
, dst
, args
[0], emit_lit_noalias
);
1580 unalias3(c
, dst
, args
[0], args
[1], args
[2], emit_lrp_noalias
);
1583 if (!accumulator_contains(c
, args
[2]))
1584 brw_MOV(p
, brw_acc_reg(), args
[2]);
1585 brw_MAC(p
, dst
, args
[0], args
[1]);
1588 emit_cmp(p
, dst
, args
[0], args
[1], args
[2]);
1591 emit_max(p
, dst
, args
[0], args
[1]);
1594 emit_min(p
, dst
, args
[0], args
[1]);
1597 brw_MOV(p
, dst
, args
[0]);
1600 brw_MUL(p
, dst
, args
[0], args
[1]);
1603 emit_math2(c
, BRW_MATH_FUNCTION_POW
, dst
, args
[0], args
[1], BRW_MATH_PRECISION_FULL
);
1606 emit_math1(c
, BRW_MATH_FUNCTION_INV
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1609 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1613 unalias2(c
, dst
, args
[0], args
[1], emit_seq
);
1616 emit_math1(c
, BRW_MATH_FUNCTION_SIN
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1619 unalias2(c
, dst
, args
[0], args
[1], emit_sne
);
1622 unalias2(c
, dst
, args
[0], args
[1], emit_sge
);
1625 unalias2(c
, dst
, args
[0], args
[1], emit_sgt
);
1628 unalias2(c
, dst
, args
[0], args
[1], emit_slt
);
1631 unalias2(c
, dst
, args
[0], args
[1], emit_sle
);
1634 brw_ADD(p
, dst
, args
[0], negate(args
[1]));
1637 /* The args[0] value can't be used here as it won't have
1638 * correctly encoded the full swizzle:
1640 emit_swz(c
, dst
, inst
);
1643 /* round toward zero */
1644 brw_RNDZ(p
, dst
, args
[0]);
1647 emit_xpd(p
, dst
, args
[0], args
[1]);
1650 assert(if_depth
< MAX_IF_DEPTH
);
1651 if_inst
[if_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1652 /* Note that brw_IF smashes the predicate_control field. */
1653 if_inst
[if_depth
]->header
.predicate_control
= get_predicate(inst
);
1657 if_inst
[if_depth
-1] = brw_ELSE(p
, if_inst
[if_depth
-1]);
1660 assert(if_depth
> 0);
1661 brw_ENDIF(p
, if_inst
[--if_depth
]);
1663 case OPCODE_BGNLOOP
:
1664 loop_inst
[loop_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
1667 brw_set_predicate_control(p
, get_predicate(inst
));
1669 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1672 brw_set_predicate_control(p
, get_predicate(inst
));
1674 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1676 case OPCODE_ENDLOOP
:
1678 struct brw_instruction
*inst0
, *inst1
;
1683 if (intel
->is_ironlake
)
1686 inst0
= inst1
= brw_WHILE(p
, loop_inst
[loop_depth
]);
1687 /* patch all the BREAK/CONT instructions from last BEGINLOOP */
1688 while (inst0
> loop_inst
[loop_depth
]) {
1690 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
) {
1691 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
1692 inst0
->bits3
.if_else
.pop_count
= 0;
1694 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
) {
1695 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
1696 inst0
->bits3
.if_else
.pop_count
= 0;
1702 brw_set_predicate_control(p
, get_predicate(inst
));
1703 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1704 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1707 brw_set_access_mode(p
, BRW_ALIGN_1
);
1708 brw_ADD(p
, deref_1d(stack_index
, 0), brw_ip_reg(), brw_imm_d(3*16));
1709 brw_set_access_mode(p
, BRW_ALIGN_16
);
1710 brw_ADD(p
, get_addr_reg(stack_index
),
1711 get_addr_reg(stack_index
), brw_imm_d(4));
1712 brw_save_call(p
, inst
->Comment
, p
->nr_insn
);
1713 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1716 brw_ADD(p
, get_addr_reg(stack_index
),
1717 get_addr_reg(stack_index
), brw_imm_d(-4));
1718 brw_set_access_mode(p
, BRW_ALIGN_1
);
1719 brw_MOV(p
, brw_ip_reg(), deref_1d(stack_index
, 0));
1720 brw_set_access_mode(p
, BRW_ALIGN_16
);
1723 end_offset
= p
->nr_insn
;
1724 /* this instruction will get patched later to jump past subroutine
1727 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1733 brw_save_label(p
, inst
->Comment
, p
->nr_insn
);
1739 _mesa_problem(NULL
, "Unsupported opcode %i (%s) in vertex shader",
1740 inst
->Opcode
, inst
->Opcode
< MAX_OPCODE
?
1741 _mesa_opcode_string(inst
->Opcode
) :
1745 /* Set the predication update on the last instruction of the native
1746 * instruction sequence.
1748 * This would be problematic if it was set on a math instruction,
1749 * but that shouldn't be the case with the current GLSL compiler.
1751 if (inst
->CondUpdate
) {
1752 struct brw_instruction
*hw_insn
= &p
->store
[p
->nr_insn
- 1];
1754 assert(hw_insn
->header
.destreg__conditionalmod
== 0);
1755 hw_insn
->header
.destreg__conditionalmod
= BRW_CONDITIONAL_NZ
;
1758 if ((inst
->DstReg
.File
== PROGRAM_OUTPUT
)
1759 && (inst
->DstReg
.Index
!= VERT_RESULT_HPOS
)
1760 && c
->output_regs
[inst
->DstReg
.Index
].used_in_src
) {
1761 brw_MOV(p
, get_dst(c
, inst
->DstReg
), dst
);
1764 /* Result color clamping.
1766 * When destination register is an output register and
1767 * it's primary/secondary front/back color, we have to clamp
1768 * the result to [0,1]. This is done by enabling the
1769 * saturation bit for the last instruction.
1771 * We don't use brw_set_saturate() as it modifies
1772 * p->current->header.saturate, which affects all the subsequent
1773 * instructions. Instead, we directly modify the header
1774 * of the last (already stored) instruction.
1776 if (inst
->DstReg
.File
== PROGRAM_OUTPUT
) {
1777 if ((inst
->DstReg
.Index
== VERT_RESULT_COL0
)
1778 || (inst
->DstReg
.Index
== VERT_RESULT_COL1
)
1779 || (inst
->DstReg
.Index
== VERT_RESULT_BFC0
)
1780 || (inst
->DstReg
.Index
== VERT_RESULT_BFC1
)) {
1781 p
->store
[p
->nr_insn
-1].header
.saturate
= 1;
1788 end_inst
= &p
->store
[end_offset
];
1789 last_inst
= &p
->store
[p
->nr_insn
];
1791 /* The END instruction will be patched to jump to this code */
1792 emit_vertex_write(c
);
1794 post_vs_emit(c
, end_inst
, last_inst
);
1796 if (INTEL_DEBUG
& DEBUG_VS
) {
1799 printf("vs-native:\n");
1800 for (i
= 0; i
< p
->nr_insn
; i
++)
1801 brw_disasm(stderr
, &p
->store
[i
]);