2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/macros.h"
34 #include "shader/program.h"
35 #include "shader/prog_parameter.h"
36 #include "shader/prog_print.h"
37 #include "brw_context.h"
41 static struct brw_reg
get_tmp( struct brw_vs_compile
*c
)
43 struct brw_reg tmp
= brw_vec8_grf(c
->last_tmp
, 0);
45 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
46 c
->prog_data
.total_grf
= c
->last_tmp
;
51 static void release_tmp( struct brw_vs_compile
*c
, struct brw_reg tmp
)
53 if (tmp
.nr
== c
->last_tmp
-1)
57 static void release_tmps( struct brw_vs_compile
*c
)
59 c
->last_tmp
= c
->first_tmp
;
64 * Preallocate GRF register before code emit.
65 * Do things as simply as possible. Allocate and populate all regs
68 static void brw_vs_alloc_regs( struct brw_vs_compile
*c
)
70 GLuint i
, reg
= 0, mrf
;
73 if (c
->vp
->program
.Base
.Parameters
->NumParameters
>= 6)
74 c
->vp
->use_const_buffer
= 1;
77 c
->vp
->use_const_buffer
= GL_FALSE
;
78 /*printf("use_const_buffer = %d\n", c->use_const_buffer);*/
80 /* r0 -- reserved as usual
82 c
->r0
= brw_vec8_grf(reg
, 0);
85 /* User clip planes from curbe:
87 if (c
->key
.nr_userclip
) {
88 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
89 c
->userplane
[i
] = stride( brw_vec4_grf(reg
+3+i
/2, (i
%2) * 4), 0, 4, 1);
92 /* Deal with curbe alignment:
94 reg
+= ((6 + c
->key
.nr_userclip
+ 3) / 4) * 2;
97 /* Vertex program parameters from curbe:
99 if (c
->vp
->use_const_buffer
) {
100 /* get constants from a real constant buffer */
101 c
->prog_data
.curb_read_length
= 0;
102 c
->prog_data
.nr_params
= 4; /* XXX 0 causes a bug elsewhere... */
105 /* use a section of the GRF for constants */
106 GLuint nr_params
= c
->vp
->program
.Base
.Parameters
->NumParameters
;
107 for (i
= 0; i
< nr_params
; i
++) {
108 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2, (i
%2) * 4), 0, 4, 1);
110 reg
+= (nr_params
+ 1) / 2;
111 c
->prog_data
.curb_read_length
= reg
- 1;
113 c
->prog_data
.nr_params
= nr_params
* 4;
116 /* Allocate input regs:
119 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
120 if (c
->prog_data
.inputs_read
& (1 << i
)) {
122 c
->regs
[PROGRAM_INPUT
][i
] = brw_vec8_grf(reg
, 0);
127 /* Allocate outputs: TODO: could organize the non-position outputs
128 * to go straight into message regs.
131 c
->first_output
= reg
;
133 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
134 if (c
->prog_data
.outputs_written
& (1 << i
)) {
136 if (i
== VERT_RESULT_HPOS
) {
137 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
140 else if (i
== VERT_RESULT_PSIZ
) {
141 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
143 mrf
++; /* just a placeholder? XXX fix later stages & remove this */
146 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_message_reg(mrf
);
152 /* Allocate program temporaries:
154 for (i
= 0; i
< c
->vp
->program
.Base
.NumTemporaries
; i
++) {
155 c
->regs
[PROGRAM_TEMPORARY
][i
] = brw_vec8_grf(reg
, 0);
159 /* Address reg(s). Don't try to use the internal address reg until
162 for (i
= 0; i
< c
->vp
->program
.Base
.NumAddressRegs
; i
++) {
163 c
->regs
[PROGRAM_ADDRESS
][i
] = brw_reg(BRW_GENERAL_REGISTER_FILE
,
167 BRW_VERTICAL_STRIDE_8
,
169 BRW_HORIZONTAL_STRIDE_1
,
175 if (c
->vp
->use_const_buffer
) {
176 for (i
= 0; i
< 3; i
++) {
177 c
->current_const
[i
].index
= -1;
178 c
->current_const
[i
].reg
= brw_vec8_grf(reg
, 0);
183 for (i
= 0; i
< 128; i
++) {
184 if (c
->output_regs
[i
].used_in_src
) {
185 c
->output_regs
[i
].reg
= brw_vec8_grf(reg
, 0);
190 c
->stack
= brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, reg
, 0);
193 /* Some opcodes need an internal temporary:
196 c
->last_tmp
= reg
; /* for allocation purposes */
198 /* Each input reg holds data from two vertices. The
199 * urb_read_length is the number of registers read from *each*
200 * vertex urb, so is half the amount:
202 c
->prog_data
.urb_read_length
= (c
->nr_inputs
+ 1) / 2;
204 c
->prog_data
.urb_entry_size
= (c
->nr_outputs
+ 2 + 3) / 4;
205 c
->prog_data
.total_grf
= reg
;
207 if (INTEL_DEBUG
& DEBUG_VS
) {
208 _mesa_printf("%s NumAddrRegs %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumAddressRegs
);
209 _mesa_printf("%s NumTemps %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumTemporaries
);
210 _mesa_printf("%s reg = %d\n", __FUNCTION__
, reg
);
216 * If an instruction uses a temp reg both as a src and the dest, we
217 * sometimes need to allocate an intermediate temporary.
219 static void unalias1( struct brw_vs_compile
*c
,
222 void (*func
)( struct brw_vs_compile
*,
226 if (dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) {
227 struct brw_compile
*p
= &c
->func
;
228 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
230 brw_MOV(p
, dst
, tmp
);
240 * Checkes if 2-operand instruction needs an intermediate temporary.
242 static void unalias2( struct brw_vs_compile
*c
,
246 void (*func
)( struct brw_vs_compile
*,
251 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
252 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
)) {
253 struct brw_compile
*p
= &c
->func
;
254 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
255 func(c
, tmp
, arg0
, arg1
);
256 brw_MOV(p
, dst
, tmp
);
260 func(c
, dst
, arg0
, arg1
);
266 * Checkes if 3-operand instruction needs an intermediate temporary.
268 static void unalias3( struct brw_vs_compile
*c
,
273 void (*func
)( struct brw_vs_compile
*,
279 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
280 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
) ||
281 (dst
.file
== arg2
.file
&& dst
.nr
== arg2
.nr
)) {
282 struct brw_compile
*p
= &c
->func
;
283 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
284 func(c
, tmp
, arg0
, arg1
, arg2
);
285 brw_MOV(p
, dst
, tmp
);
289 func(c
, dst
, arg0
, arg1
, arg2
);
293 static void emit_sop( struct brw_compile
*p
,
299 brw_MOV(p
, dst
, brw_imm_f(0.0f
));
300 brw_CMP(p
, brw_null_reg(), cond
, arg0
, arg1
);
301 brw_MOV(p
, dst
, brw_imm_f(1.0f
));
302 brw_set_predicate_control_flag_value(p
, 0xff);
305 static void emit_seq( struct brw_compile
*p
,
308 struct brw_reg arg1
)
310 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_EQ
);
313 static void emit_sne( struct brw_compile
*p
,
316 struct brw_reg arg1
)
318 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_NEQ
);
320 static void emit_slt( struct brw_compile
*p
,
323 struct brw_reg arg1
)
325 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_L
);
328 static void emit_sle( struct brw_compile
*p
,
331 struct brw_reg arg1
)
333 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_LE
);
336 static void emit_sgt( struct brw_compile
*p
,
339 struct brw_reg arg1
)
341 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_G
);
344 static void emit_sge( struct brw_compile
*p
,
347 struct brw_reg arg1
)
349 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_GE
);
352 static void emit_max( struct brw_compile
*p
,
355 struct brw_reg arg1
)
357 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
358 brw_SEL(p
, dst
, arg1
, arg0
);
359 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
362 static void emit_min( struct brw_compile
*p
,
365 struct brw_reg arg1
)
367 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
368 brw_SEL(p
, dst
, arg0
, arg1
);
369 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
373 static void emit_math1( struct brw_vs_compile
*c
,
379 /* There are various odd behaviours with SEND on the simulator. In
380 * addition there are documented issues with the fact that the GEN4
381 * processor doesn't do dependency control properly on SEND
382 * results. So, on balance, this kludge to get around failures
383 * with writemasked math results looks like it might be necessary
384 * whether that turns out to be a simulator bug or not:
386 struct brw_compile
*p
= &c
->func
;
387 struct brw_reg tmp
= dst
;
388 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
389 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
397 BRW_MATH_SATURATE_NONE
,
400 BRW_MATH_DATA_SCALAR
,
404 brw_MOV(p
, dst
, tmp
);
410 static void emit_math2( struct brw_vs_compile
*c
,
417 struct brw_compile
*p
= &c
->func
;
418 struct brw_reg tmp
= dst
;
419 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
420 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
425 brw_MOV(p
, brw_message_reg(3), arg1
);
430 BRW_MATH_SATURATE_NONE
,
433 BRW_MATH_DATA_SCALAR
,
437 brw_MOV(p
, dst
, tmp
);
443 static void emit_exp_noalias( struct brw_vs_compile
*c
,
445 struct brw_reg arg0
)
447 struct brw_compile
*p
= &c
->func
;
450 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
) {
451 struct brw_reg tmp
= get_tmp(c
);
452 struct brw_reg tmp_d
= retype(tmp
, BRW_REGISTER_TYPE_D
);
454 /* tmp_d = floor(arg0.x) */
455 brw_RNDD(p
, tmp_d
, brw_swizzle1(arg0
, 0));
457 /* result[0] = 2.0 ^ tmp */
459 /* Adjust exponent for floating point:
462 brw_ADD(p
, brw_writemask(tmp_d
, WRITEMASK_X
), tmp_d
, brw_imm_d(127));
464 /* Install exponent and sign.
465 * Excess drops off the edge:
467 brw_SHL(p
, brw_writemask(retype(dst
, BRW_REGISTER_TYPE_D
), WRITEMASK_X
),
468 tmp_d
, brw_imm_d(23));
473 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
) {
474 /* result[1] = arg0.x - floor(arg0.x) */
475 brw_FRC(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
, 0));
478 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
479 /* As with the LOG instruction, we might be better off just
480 * doing a taylor expansion here, seeing as we have to do all
483 * If mathbox partial precision is too low, consider also:
484 * result[3] = result[0] * EXP(result[1])
487 BRW_MATH_FUNCTION_EXP
,
488 brw_writemask(dst
, WRITEMASK_Z
),
489 brw_swizzle1(arg0
, 0),
490 BRW_MATH_PRECISION_FULL
);
493 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
494 /* result[3] = 1.0; */
495 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), brw_imm_f(1));
500 static void emit_log_noalias( struct brw_vs_compile
*c
,
502 struct brw_reg arg0
)
504 struct brw_compile
*p
= &c
->func
;
505 struct brw_reg tmp
= dst
;
506 struct brw_reg tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
507 struct brw_reg arg0_ud
= retype(arg0
, BRW_REGISTER_TYPE_UD
);
508 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
509 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
513 tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
516 /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt
519 * These almost look likey they could be joined up, but not really
522 * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127
523 * result[1].i = (x.i & ((1<<23)-1) + (127<<23)
525 if (dst
.dw1
.bits
.writemask
& WRITEMASK_XZ
) {
527 brw_writemask(tmp_ud
, WRITEMASK_X
),
528 brw_swizzle1(arg0_ud
, 0),
529 brw_imm_ud((1U<<31)-1));
532 brw_writemask(tmp_ud
, WRITEMASK_X
),
537 brw_writemask(tmp
, WRITEMASK_X
),
538 retype(tmp_ud
, BRW_REGISTER_TYPE_D
), /* does it matter? */
542 if (dst
.dw1
.bits
.writemask
& WRITEMASK_YZ
) {
544 brw_writemask(tmp_ud
, WRITEMASK_Y
),
545 brw_swizzle1(arg0_ud
, 0),
546 brw_imm_ud((1<<23)-1));
549 brw_writemask(tmp_ud
, WRITEMASK_Y
),
551 brw_imm_ud(127<<23));
554 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
555 /* result[2] = result[0] + LOG2(result[1]); */
557 /* Why bother? The above is just a hint how to do this with a
558 * taylor series. Maybe we *should* use a taylor series as by
559 * the time all the above has been done it's almost certainly
560 * quicker than calling the mathbox, even with low precision.
563 * - result[0] + mathbox.LOG2(result[1])
564 * - mathbox.LOG2(arg0.x)
565 * - result[0] + inline_taylor_approx(result[1])
568 BRW_MATH_FUNCTION_LOG
,
569 brw_writemask(tmp
, WRITEMASK_Z
),
570 brw_swizzle1(tmp
, 1),
571 BRW_MATH_PRECISION_FULL
);
574 brw_writemask(tmp
, WRITEMASK_Z
),
575 brw_swizzle1(tmp
, 2),
576 brw_swizzle1(tmp
, 0));
579 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
580 /* result[3] = 1.0; */
581 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_W
), brw_imm_f(1));
585 brw_MOV(p
, dst
, tmp
);
591 /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
593 static void emit_dst_noalias( struct brw_vs_compile
*c
,
598 struct brw_compile
*p
= &c
->func
;
600 /* There must be a better way to do this:
602 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
)
603 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_X
), brw_imm_f(1.0));
604 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
)
605 brw_MUL(p
, brw_writemask(dst
, WRITEMASK_Y
), arg0
, arg1
);
606 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
)
607 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Z
), arg0
);
608 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
)
609 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), arg1
);
613 static void emit_xpd( struct brw_compile
*p
,
618 brw_MUL(p
, brw_null_reg(), brw_swizzle(t
, 1,2,0,3), brw_swizzle(u
,2,0,1,3));
619 brw_MAC(p
, dst
, negate(brw_swizzle(t
, 2,0,1,3)), brw_swizzle(u
,1,2,0,3));
623 static void emit_lit_noalias( struct brw_vs_compile
*c
,
625 struct brw_reg arg0
)
627 struct brw_compile
*p
= &c
->func
;
628 struct brw_instruction
*if_insn
;
629 struct brw_reg tmp
= dst
;
630 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
635 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_YZ
), brw_imm_f(0));
636 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_XW
), brw_imm_f(1));
638 /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order
639 * to get all channels active inside the IF. In the clipping code
640 * we run with NoMask, so it's not an option and we can use
641 * BRW_EXECUTE_1 for all comparisions.
643 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,0), brw_imm_f(0));
644 if_insn
= brw_IF(p
, BRW_EXECUTE_8
);
646 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
,0));
648 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,1), brw_imm_f(0));
649 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_Z
), brw_swizzle1(arg0
,1));
650 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
653 BRW_MATH_FUNCTION_POW
,
654 brw_writemask(dst
, WRITEMASK_Z
),
655 brw_swizzle1(tmp
, 2),
656 brw_swizzle1(arg0
, 3),
657 BRW_MATH_PRECISION_PARTIAL
);
660 brw_ENDIF(p
, if_insn
);
665 static void emit_lrp_noalias(struct brw_vs_compile
*c
,
671 struct brw_compile
*p
= &c
->func
;
673 brw_ADD(p
, dst
, negate(arg0
), brw_imm_f(1.0));
674 brw_MUL(p
, brw_null_reg(), dst
, arg2
);
675 brw_MAC(p
, dst
, arg0
, arg1
);
678 /** 3 or 4-component vector normalization */
679 static void emit_nrm( struct brw_vs_compile
*c
,
684 struct brw_compile
*p
= &c
->func
;
685 struct brw_reg tmp
= get_tmp(c
);
687 /* tmp = dot(arg0, arg0) */
689 brw_DP3(p
, tmp
, arg0
, arg0
);
691 brw_DP4(p
, tmp
, arg0
, arg0
);
693 /* tmp = 1 / sqrt(tmp) */
694 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, tmp
, tmp
, BRW_MATH_PRECISION_FULL
);
696 /* dst = arg0 * tmp */
697 brw_MUL(p
, dst
, arg0
, tmp
);
703 static struct brw_reg
704 get_constant(struct brw_vs_compile
*c
,
705 const struct prog_instruction
*inst
,
708 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
709 struct brw_compile
*p
= &c
->func
;
710 struct brw_reg const_reg
;
711 struct brw_reg const2_reg
;
713 assert(argIndex
< 3);
715 if (c
->current_const
[argIndex
].index
!= src
->Index
|| src
->RelAddr
) {
716 struct brw_reg addrReg
= c
->regs
[PROGRAM_ADDRESS
][0];
718 c
->current_const
[argIndex
].index
= src
->Index
;
721 printf(" fetch const[%d] for arg %d into reg %d\n",
722 src
->Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
724 /* need to fetch the constant now */
726 c
->current_const
[argIndex
].reg
,/* writeback dest */
728 src
->RelAddr
, /* relative indexing? */
729 addrReg
, /* address register */
730 16 * src
->Index
, /* byte offset */
731 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
736 const2_reg
= get_tmp(c
);
738 /* use upper half of address reg for second read */
739 addrReg
= stride(addrReg
, 0, 4, 0);
743 const2_reg
, /* writeback dest */
745 src
->RelAddr
, /* relative indexing? */
746 addrReg
, /* address register */
747 16 * src
->Index
, /* byte offset */
748 SURF_INDEX_VERT_CONST_BUFFER
753 const_reg
= c
->current_const
[argIndex
].reg
;
756 /* merge the two Owords into the constant register */
757 /* const_reg[7..4] = const2_reg[7..4] */
759 suboffset(stride(const_reg
, 0, 4, 1), 4),
760 suboffset(stride(const2_reg
, 0, 4, 1), 4));
761 release_tmp(c
, const2_reg
);
764 /* replicate lower four floats into upper half (to get XYZWXYZW) */
765 const_reg
= stride(const_reg
, 0, 4, 0);
774 /* TODO: relative addressing!
776 static struct brw_reg
get_reg( struct brw_vs_compile
*c
,
777 gl_register_file file
,
781 case PROGRAM_TEMPORARY
:
784 assert(c
->regs
[file
][index
].nr
!= 0);
785 return c
->regs
[file
][index
];
786 case PROGRAM_STATE_VAR
:
787 case PROGRAM_CONSTANT
:
788 case PROGRAM_UNIFORM
:
789 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
790 return c
->regs
[PROGRAM_STATE_VAR
][index
];
791 case PROGRAM_ADDRESS
:
793 return c
->regs
[file
][index
];
795 case PROGRAM_UNDEFINED
: /* undef values */
796 return brw_null_reg();
798 case PROGRAM_LOCAL_PARAM
:
799 case PROGRAM_ENV_PARAM
:
800 case PROGRAM_WRITE_ONLY
:
803 return brw_null_reg();
809 * Indirect addressing: get reg[[arg] + offset].
811 static struct brw_reg
deref( struct brw_vs_compile
*c
,
815 struct brw_compile
*p
= &c
->func
;
816 struct brw_reg tmp
= vec4(get_tmp(c
));
817 struct brw_reg addr_reg
= c
->regs
[PROGRAM_ADDRESS
][0];
818 struct brw_reg vp_address
= retype(vec1(addr_reg
), BRW_REGISTER_TYPE_UW
);
819 GLuint byte_offset
= arg
.nr
* 32 + arg
.subnr
+ offset
* 16;
820 struct brw_reg indirect
= brw_vec4_indirect(0,0);
823 brw_push_insn_state(p
);
824 brw_set_access_mode(p
, BRW_ALIGN_1
);
826 /* This is pretty clunky - load the address register twice and
827 * fetch each 4-dword value in turn. There must be a way to do
828 * this in a single pass, but I couldn't get it to work.
830 brw_ADD(p
, brw_address_reg(0), vp_address
, brw_imm_d(byte_offset
));
831 brw_MOV(p
, tmp
, indirect
);
833 brw_ADD(p
, brw_address_reg(0), suboffset(vp_address
, 8), brw_imm_d(byte_offset
));
834 brw_MOV(p
, suboffset(tmp
, 4), indirect
);
836 brw_pop_insn_state(p
);
839 /* NOTE: tmp not released */
845 * Get brw reg corresponding to the instruction's [argIndex] src reg.
846 * TODO: relative addressing!
848 static struct brw_reg
849 get_src_reg( struct brw_vs_compile
*c
,
850 const struct prog_instruction
*inst
,
853 const GLuint file
= inst
->SrcReg
[argIndex
].File
;
854 const GLint index
= inst
->SrcReg
[argIndex
].Index
;
855 const GLboolean relAddr
= inst
->SrcReg
[argIndex
].RelAddr
;
858 case PROGRAM_TEMPORARY
:
862 return deref(c
, c
->regs
[file
][0], index
);
865 assert(c
->regs
[file
][index
].nr
!= 0);
866 return c
->regs
[file
][index
];
869 case PROGRAM_STATE_VAR
:
870 case PROGRAM_CONSTANT
:
871 case PROGRAM_UNIFORM
:
872 if (c
->vp
->use_const_buffer
) {
873 return get_constant(c
, inst
, argIndex
);
876 return deref(c
, c
->regs
[PROGRAM_STATE_VAR
][0], index
);
879 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
880 return c
->regs
[PROGRAM_STATE_VAR
][index
];
882 case PROGRAM_ADDRESS
:
884 return c
->regs
[file
][index
];
886 case PROGRAM_UNDEFINED
:
887 /* this is a normal case since we loop over all three src args */
888 return brw_null_reg();
890 case PROGRAM_LOCAL_PARAM
:
891 case PROGRAM_ENV_PARAM
:
892 case PROGRAM_WRITE_ONLY
:
895 return brw_null_reg();
900 static void emit_arl( struct brw_vs_compile
*c
,
902 struct brw_reg arg0
)
904 struct brw_compile
*p
= &c
->func
;
905 struct brw_reg tmp
= dst
;
906 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
911 brw_RNDD(p
, tmp
, arg0
); /* tmp = round(arg0) */
912 brw_MUL(p
, dst
, tmp
, brw_imm_d(16)); /* dst = tmp * 16 */
920 * Return the brw reg for the given instruction's src argument.
921 * Will return mangled results for SWZ op. The emit_swz() function
922 * ignores this result and recalculates taking extended swizzles into
925 static struct brw_reg
get_arg( struct brw_vs_compile
*c
,
926 const struct prog_instruction
*inst
,
929 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
932 if (src
->File
== PROGRAM_UNDEFINED
)
933 return brw_null_reg();
935 reg
= get_src_reg(c
, inst
, argIndex
);
937 /* Convert 3-bit swizzle to 2-bit.
939 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(GET_SWZ(src
->Swizzle
, 0),
940 GET_SWZ(src
->Swizzle
, 1),
941 GET_SWZ(src
->Swizzle
, 2),
942 GET_SWZ(src
->Swizzle
, 3));
944 /* Note this is ok for non-swizzle instructions:
946 reg
.negate
= src
->Negate
? 1 : 0;
953 * Get brw register for the given program dest register.
955 static struct brw_reg
get_dst( struct brw_vs_compile
*c
,
956 struct prog_dst_register dst
)
961 case PROGRAM_TEMPORARY
:
963 assert(c
->regs
[dst
.File
][dst
.Index
].nr
!= 0);
964 reg
= c
->regs
[dst
.File
][dst
.Index
];
966 case PROGRAM_ADDRESS
:
967 assert(dst
.Index
== 0);
968 reg
= c
->regs
[dst
.File
][dst
.Index
];
970 case PROGRAM_UNDEFINED
:
971 /* we may hit this for OPCODE_END, OPCODE_KIL, etc */
972 reg
= brw_null_reg();
976 reg
= brw_null_reg();
979 reg
.dw1
.bits
.writemask
= dst
.WriteMask
;
985 static void emit_swz( struct brw_vs_compile
*c
,
987 const struct prog_instruction
*inst
)
989 const GLuint argIndex
= 0;
990 const struct prog_src_register src
= inst
->SrcReg
[argIndex
];
991 struct brw_compile
*p
= &c
->func
;
992 GLuint zeros_mask
= 0;
993 GLuint ones_mask
= 0;
996 GLboolean need_tmp
= (src
.Negate
&&
997 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
998 struct brw_reg tmp
= dst
;
1004 for (i
= 0; i
< 4; i
++) {
1005 if (dst
.dw1
.bits
.writemask
& (1<<i
)) {
1006 GLubyte s
= GET_SWZ(src
.Swizzle
, i
);
1025 /* Do src first, in case dst aliases src:
1028 struct brw_reg arg0
;
1030 arg0
= get_src_reg(c
, inst
, argIndex
);
1032 arg0
= brw_swizzle(arg0
,
1033 src_swz
[0], src_swz
[1],
1034 src_swz
[2], src_swz
[3]);
1036 brw_MOV(p
, brw_writemask(tmp
, src_mask
), arg0
);
1040 brw_MOV(p
, brw_writemask(tmp
, zeros_mask
), brw_imm_f(0));
1043 brw_MOV(p
, brw_writemask(tmp
, ones_mask
), brw_imm_f(1));
1046 brw_MOV(p
, brw_writemask(tmp
, src
.Negate
), negate(tmp
));
1049 brw_MOV(p
, dst
, tmp
);
1050 release_tmp(c
, tmp
);
1056 * Post-vertex-program processing. Send the results to the URB.
1058 static void emit_vertex_write( struct brw_vs_compile
*c
)
1060 struct brw_compile
*p
= &c
->func
;
1061 struct brw_reg m0
= brw_message_reg(0);
1062 struct brw_reg pos
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_HPOS
];
1065 if (c
->key
.copy_edgeflag
) {
1067 get_reg(c
, PROGRAM_OUTPUT
, VERT_RESULT_EDGE
),
1068 get_reg(c
, PROGRAM_INPUT
, VERT_ATTRIB_EDGEFLAG
));
1071 /* Build ndc coords */
1073 emit_math1(c
, BRW_MATH_FUNCTION_INV
, ndc
, brw_swizzle1(pos
, 3), BRW_MATH_PRECISION_FULL
);
1074 brw_MUL(p
, brw_writemask(ndc
, WRITEMASK_XYZ
), pos
, ndc
);
1076 /* Update the header for point size, user clipping flags, and -ve rhw
1079 if ((c
->prog_data
.outputs_written
& (1<<VERT_RESULT_PSIZ
)) ||
1080 c
->key
.nr_userclip
|| !BRW_IS_G4X(p
->brw
))
1082 struct brw_reg header1
= retype(get_tmp(c
), BRW_REGISTER_TYPE_UD
);
1085 brw_MOV(p
, header1
, brw_imm_ud(0));
1087 brw_set_access_mode(p
, BRW_ALIGN_16
);
1089 if (c
->prog_data
.outputs_written
& (1<<VERT_RESULT_PSIZ
)) {
1090 struct brw_reg psiz
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_PSIZ
];
1091 brw_MUL(p
, brw_writemask(header1
, WRITEMASK_W
), brw_swizzle1(psiz
, 0), brw_imm_f(1<<11));
1092 brw_AND(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(0x7ff<<8));
1095 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1096 brw_set_conditionalmod(p
, BRW_CONDITIONAL_L
);
1097 brw_DP4(p
, brw_null_reg(), pos
, c
->userplane
[i
]);
1098 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<i
));
1099 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1102 /* i965 clipping workaround:
1103 * 1) Test for -ve rhw
1105 * set ndc = (0,0,0,0)
1108 * Later, clipping will detect ucp[6] and ensure the primitive is
1109 * clipped against all fixed planes.
1111 if (!BRW_IS_G4X(p
->brw
)) {
1113 vec8(brw_null_reg()),
1115 brw_swizzle1(ndc
, 3),
1118 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1119 brw_MOV(p
, ndc
, brw_imm_f(0));
1120 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1123 brw_set_access_mode(p
, BRW_ALIGN_1
); /* why? */
1124 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), header1
);
1125 brw_set_access_mode(p
, BRW_ALIGN_16
);
1127 release_tmp(c
, header1
);
1130 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
1133 /* Emit the (interleaved) headers for the two vertices - an 8-reg
1134 * of zeros followed by two sets of NDC coordinates:
1136 brw_set_access_mode(p
, BRW_ALIGN_1
);
1137 brw_MOV(p
, offset(m0
, 2), ndc
);
1138 brw_MOV(p
, offset(m0
, 3), pos
);
1141 brw_null_reg(), /* dest */
1142 0, /* starting mrf reg nr */
1146 c
->nr_outputs
+ 3, /* msg len */
1147 0, /* response len */
1149 1, /* writes complete */
1150 0, /* urb destination offset */
1151 BRW_URB_SWIZZLE_INTERLEAVE
);
1156 * Called after code generation to resolve subroutine calls and the
1158 * \param end_inst points to brw code for END instruction
1159 * \param last_inst points to last instruction emitted before vertex write
1162 post_vs_emit( struct brw_vs_compile
*c
,
1163 struct brw_instruction
*end_inst
,
1164 struct brw_instruction
*last_inst
)
1168 brw_resolve_cals(&c
->func
);
1170 /* patch up the END code to jump past subroutines, etc */
1171 offset
= last_inst
- end_inst
;
1172 brw_set_src1(end_inst
, brw_imm_d(offset
* 16));
1176 /* Emit the vertex program instructions here.
1178 void brw_vs_emit(struct brw_vs_compile
*c
)
1181 struct brw_compile
*p
= &c
->func
;
1182 GLuint nr_insns
= c
->vp
->program
.Base
.NumInstructions
;
1183 GLuint insn
, if_insn
= 0;
1184 GLuint end_offset
= 0;
1185 struct brw_instruction
*end_inst
, *last_inst
;
1186 struct brw_instruction
*if_inst
[MAX_IFSN
];
1187 struct brw_indirect stack_index
= brw_indirect(0, 0);
1192 if (INTEL_DEBUG
& DEBUG_VS
) {
1193 _mesa_printf("vs-emit:\n");
1194 _mesa_print_program(&c
->vp
->program
.Base
);
1198 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1199 brw_set_access_mode(p
, BRW_ALIGN_16
);
1201 /* Message registers can't be read, so copy the output into GRF register
1202 if they are used in source registers */
1203 for (insn
= 0; insn
< nr_insns
; insn
++) {
1205 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1206 for (i
= 0; i
< 3; i
++) {
1207 struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1208 GLuint index
= src
->Index
;
1209 GLuint file
= src
->File
;
1210 if (file
== PROGRAM_OUTPUT
&& index
!= VERT_RESULT_HPOS
)
1211 c
->output_regs
[index
].used_in_src
= GL_TRUE
;
1215 /* Static register allocation
1217 brw_vs_alloc_regs(c
);
1218 brw_MOV(p
, get_addr_reg(stack_index
), brw_address(c
->stack
));
1220 for (insn
= 0; insn
< nr_insns
; insn
++) {
1222 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1223 struct brw_reg args
[3], dst
;
1227 printf("%d: ", insn
);
1228 _mesa_print_instruction(inst
);
1231 /* Get argument regs. SWZ is special and does this itself.
1233 if (inst
->Opcode
!= OPCODE_SWZ
)
1234 for (i
= 0; i
< 3; i
++) {
1235 struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1238 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1239 args
[i
] = c
->output_regs
[index
].reg
;
1241 args
[i
] = get_arg(c
, inst
, i
);
1244 /* Get dest regs. Note that it is possible for a reg to be both
1245 * dst and arg, given the static allocation of registers. So
1246 * care needs to be taken emitting multi-operation instructions.
1248 index
= inst
->DstReg
.Index
;
1249 file
= inst
->DstReg
.File
;
1250 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1251 dst
= c
->output_regs
[index
].reg
;
1253 dst
= get_dst(c
, inst
->DstReg
);
1255 if (inst
->SaturateMode
!= SATURATE_OFF
) {
1256 _mesa_problem(NULL
, "Unsupported saturate %d in vertex shader",
1257 inst
->SaturateMode
);
1260 switch (inst
->Opcode
) {
1262 brw_MOV(p
, dst
, brw_abs(args
[0]));
1265 brw_ADD(p
, dst
, args
[0], args
[1]);
1268 emit_math1(c
, BRW_MATH_FUNCTION_COS
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1271 brw_DP3(p
, dst
, args
[0], args
[1]);
1274 brw_DP4(p
, dst
, args
[0], args
[1]);
1277 brw_DPH(p
, dst
, args
[0], args
[1]);
1280 emit_nrm(c
, dst
, args
[0], 3);
1283 emit_nrm(c
, dst
, args
[0], 4);
1286 unalias2(c
, dst
, args
[0], args
[1], emit_dst_noalias
);
1289 unalias1(c
, dst
, args
[0], emit_exp_noalias
);
1292 emit_math1(c
, BRW_MATH_FUNCTION_EXP
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1295 emit_arl(c
, dst
, args
[0]);
1298 brw_RNDD(p
, dst
, args
[0]);
1301 brw_FRC(p
, dst
, args
[0]);
1304 unalias1(c
, dst
, args
[0], emit_log_noalias
);
1307 emit_math1(c
, BRW_MATH_FUNCTION_LOG
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1310 unalias1(c
, dst
, args
[0], emit_lit_noalias
);
1313 unalias3(c
, dst
, args
[0], args
[1], args
[2], emit_lrp_noalias
);
1316 brw_MOV(p
, brw_acc_reg(), args
[2]);
1317 brw_MAC(p
, dst
, args
[0], args
[1]);
1320 emit_max(p
, dst
, args
[0], args
[1]);
1323 emit_min(p
, dst
, args
[0], args
[1]);
1326 brw_MOV(p
, dst
, args
[0]);
1329 brw_MUL(p
, dst
, args
[0], args
[1]);
1332 emit_math2(c
, BRW_MATH_FUNCTION_POW
, dst
, args
[0], args
[1], BRW_MATH_PRECISION_FULL
);
1335 emit_math1(c
, BRW_MATH_FUNCTION_INV
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1338 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1342 emit_seq(p
, dst
, args
[0], args
[1]);
1345 emit_math1(c
, BRW_MATH_FUNCTION_SIN
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1348 emit_sne(p
, dst
, args
[0], args
[1]);
1351 emit_sge(p
, dst
, args
[0], args
[1]);
1354 emit_sgt(p
, dst
, args
[0], args
[1]);
1357 emit_slt(p
, dst
, args
[0], args
[1]);
1360 emit_sle(p
, dst
, args
[0], args
[1]);
1363 brw_ADD(p
, dst
, args
[0], negate(args
[1]));
1366 /* The args[0] value can't be used here as it won't have
1367 * correctly encoded the full swizzle:
1369 emit_swz(c
, dst
, inst
);
1372 /* round toward zero */
1373 brw_RNDZ(p
, dst
, args
[0]);
1376 emit_xpd(p
, dst
, args
[0], args
[1]);
1379 assert(if_insn
< MAX_IFSN
);
1380 if_inst
[if_insn
++] = brw_IF(p
, BRW_EXECUTE_8
);
1383 if_inst
[if_insn
-1] = brw_ELSE(p
, if_inst
[if_insn
-1]);
1386 assert(if_insn
> 0);
1387 brw_ENDIF(p
, if_inst
[--if_insn
]);
1390 brw_set_predicate_control(p
, BRW_PREDICATE_NORMAL
);
1391 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1392 brw_set_predicate_control_flag_value(p
, 0xff);
1395 brw_set_access_mode(p
, BRW_ALIGN_1
);
1396 brw_ADD(p
, deref_1d(stack_index
, 0), brw_ip_reg(), brw_imm_d(3*16));
1397 brw_set_access_mode(p
, BRW_ALIGN_16
);
1398 brw_ADD(p
, get_addr_reg(stack_index
),
1399 get_addr_reg(stack_index
), brw_imm_d(4));
1400 brw_save_call(p
, inst
->Comment
, p
->nr_insn
);
1401 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1404 brw_ADD(p
, get_addr_reg(stack_index
),
1405 get_addr_reg(stack_index
), brw_imm_d(-4));
1406 brw_set_access_mode(p
, BRW_ALIGN_1
);
1407 brw_MOV(p
, brw_ip_reg(), deref_1d(stack_index
, 0));
1408 brw_set_access_mode(p
, BRW_ALIGN_16
);
1411 end_offset
= p
->nr_insn
;
1412 /* this instruction will get patched later to jump past subroutine
1415 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1421 brw_save_label(p
, inst
->Comment
, p
->nr_insn
);
1427 _mesa_problem(NULL
, "Unsupported opcode %i (%s) in vertex shader",
1428 inst
->Opcode
, inst
->Opcode
< MAX_OPCODE
?
1429 _mesa_opcode_string(inst
->Opcode
) :
1433 if ((inst
->DstReg
.File
== PROGRAM_OUTPUT
)
1434 && (inst
->DstReg
.Index
!= VERT_RESULT_HPOS
)
1435 && c
->output_regs
[inst
->DstReg
.Index
].used_in_src
) {
1436 brw_MOV(p
, get_dst(c
, inst
->DstReg
), dst
);
1439 /* Result color clamping.
1441 * When destination register is an output register and
1442 * it's primary/secondary front/back color, we have to clamp
1443 * the result to [0,1]. This is done by enabling the
1444 * saturation bit for the last instruction.
1446 * We don't use brw_set_saturate() as it modifies
1447 * p->current->header.saturate, which affects all the subsequent
1448 * instructions. Instead, we directly modify the header
1449 * of the last (already stored) instruction.
1451 if (inst
->DstReg
.File
== PROGRAM_OUTPUT
) {
1452 if ((inst
->DstReg
.Index
== VERT_RESULT_COL0
)
1453 || (inst
->DstReg
.Index
== VERT_RESULT_COL1
)
1454 || (inst
->DstReg
.Index
== VERT_RESULT_BFC0
)
1455 || (inst
->DstReg
.Index
== VERT_RESULT_BFC1
)) {
1456 p
->store
[p
->nr_insn
-1].header
.saturate
= 1;
1463 end_inst
= &p
->store
[end_offset
];
1464 last_inst
= &p
->store
[p
->nr_insn
];
1466 /* The END instruction will be patched to jump to this code */
1467 emit_vertex_write(c
);
1469 post_vs_emit(c
, end_inst
, last_inst
);