2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_context.h"
35 #include "program_instruction.h"
41 /* Do things as simply as possible. Allocate and populate all regs
44 static void brw_vs_alloc_regs( struct brw_vs_compile
*c
)
46 GLuint i
, reg
= 0, mrf
;
49 /* r0 -- reserved as usual
51 c
->r0
= brw_vec8_grf(reg
, 0); reg
++;
53 /* User clip planes from curbe:
55 if (c
->key
.nr_userclip
) {
56 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
57 c
->userplane
[i
] = stride( brw_vec4_grf(reg
+3+i
/2, (i
%2) * 4), 0, 4, 1);
60 /* Deal with curbe alignment:
62 reg
+= ((6+c
->key
.nr_userclip
+3)/4)*2;
65 /* Vertex program parameters from curbe:
67 nr_params
= c
->vp
->program
.Base
.Parameters
->NumParameters
;
68 for (i
= 0; i
< nr_params
; i
++) {
69 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2, (i
%2) * 4), 0, 4, 1);
71 reg
+= (nr_params
+1)/2;
73 c
->prog_data
.curb_read_length
= reg
- 1;
77 /* Allocate input regs:
80 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
81 if (c
->prog_data
.inputs_read
& (1<<i
)) {
83 c
->regs
[PROGRAM_INPUT
][i
] = brw_vec8_grf(reg
, 0);
89 /* Allocate outputs: TODO: could organize the non-position outputs
90 * to go straight into message regs.
93 c
->first_output
= reg
;
95 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
96 if (c
->prog_data
.outputs_written
& (1<<i
)) {
98 if (i
== VERT_RESULT_HPOS
) {
99 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
102 else if (i
== VERT_RESULT_PSIZ
) {
103 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
105 mrf
++; /* just a placeholder? XXX fix later stages & remove this */
108 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_message_reg(mrf
);
114 /* Allocate program temporaries:
116 for (i
= 0; i
< c
->vp
->program
.Base
.NumTemporaries
; i
++) {
117 c
->regs
[PROGRAM_TEMPORARY
][i
] = brw_vec8_grf(reg
, 0);
121 /* Address reg(s). Don't try to use the internal address reg until
124 for (i
= 0; i
< c
->vp
->program
.Base
.NumAddressRegs
; i
++) {
125 c
->regs
[PROGRAM_ADDRESS
][i
] = brw_reg(BRW_GENERAL_REGISTER_FILE
,
129 BRW_VERTICAL_STRIDE_8
,
131 BRW_HORIZONTAL_STRIDE_1
,
138 /* Some opcodes need an internal temporary:
141 c
->last_tmp
= reg
; /* for allocation purposes */
143 /* Each input reg holds data from two vertices. The
144 * urb_read_length is the number of registers read from *each*
145 * vertex urb, so is half the amount:
147 c
->prog_data
.urb_read_length
= (c
->nr_inputs
+1)/2;
149 c
->prog_data
.urb_entry_size
= (c
->nr_outputs
+2+3)/4;
150 c
->prog_data
.total_grf
= reg
;
154 static struct brw_reg
get_tmp( struct brw_vs_compile
*c
)
156 struct brw_reg tmp
= brw_vec8_grf(c
->last_tmp
, 0);
158 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
159 c
->prog_data
.total_grf
= c
->last_tmp
;
164 static void release_tmp( struct brw_vs_compile
*c
, struct brw_reg tmp
)
166 if (tmp
.nr
== c
->last_tmp
-1)
170 static void release_tmps( struct brw_vs_compile
*c
)
172 c
->last_tmp
= c
->first_tmp
;
176 static void unalias1( struct brw_vs_compile
*c
,
179 void (*func
)( struct brw_vs_compile
*,
183 if (dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) {
184 struct brw_compile
*p
= &c
->func
;
185 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
187 brw_MOV(p
, dst
, tmp
);
194 static void unalias2( struct brw_vs_compile
*c
,
198 void (*func
)( struct brw_vs_compile
*,
203 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) &&
204 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
)) {
205 struct brw_compile
*p
= &c
->func
;
206 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
207 func(c
, tmp
, arg0
, arg1
);
208 brw_MOV(p
, dst
, tmp
);
211 func(c
, dst
, arg0
, arg1
);
218 static void emit_slt( struct brw_compile
*p
,
221 struct brw_reg arg1
)
223 /* Could be done with an if/else/endif, but this method uses half
224 * the instructions. Note that we are careful to reference the
225 * arguments before writing the dest. That means we emit the
226 * instructions in an odd order and have to play with the flag
229 brw_push_insn_state(p
);
230 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_GE
, arg0
, arg1
);
232 /* Write all values to 1:
234 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
235 brw_MOV(p
, dst
, brw_imm_f(1.0));
237 /* Where the test succeeded, overwite with zero:
239 brw_set_predicate_control(p
, BRW_PREDICATE_NORMAL
);
240 brw_MOV(p
, dst
, brw_imm_f(0.0));
241 brw_pop_insn_state(p
);
245 static void emit_sge( struct brw_compile
*p
,
248 struct brw_reg arg1
)
250 brw_push_insn_state(p
);
251 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_GE
, arg0
, arg1
);
253 /* Write all values to zero:
255 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
256 brw_MOV(p
, dst
, brw_imm_f(0));
258 /* Where the test succeeded, overwite with 1:
260 brw_set_predicate_control(p
, BRW_PREDICATE_NORMAL
);
261 brw_MOV(p
, dst
, brw_imm_f(1.0));
262 brw_pop_insn_state(p
);
266 static void emit_max( struct brw_compile
*p
,
269 struct brw_reg arg1
)
271 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
272 brw_SEL(p
, dst
, arg1
, arg0
);
273 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
276 static void emit_min( struct brw_compile
*p
,
279 struct brw_reg arg1
)
281 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
282 brw_SEL(p
, dst
, arg0
, arg1
);
283 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
287 static void emit_math1( struct brw_vs_compile
*c
,
293 /* There are various odd behaviours with SEND on the simulator. In
294 * addition there are documented issues with the fact that the GEN4
295 * processor doesn't do dependency control properly on SEND
296 * results. So, on balance, this kludge to get around failures
297 * with writemasked math results looks like it might be necessary
298 * whether that turns out to be a simulator bug or not:
300 struct brw_compile
*p
= &c
->func
;
301 struct brw_reg tmp
= dst
;
302 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
303 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
311 BRW_MATH_SATURATE_NONE
,
314 BRW_MATH_DATA_SCALAR
,
318 brw_MOV(p
, dst
, tmp
);
323 static void emit_math2( struct brw_vs_compile
*c
,
330 struct brw_compile
*p
= &c
->func
;
331 struct brw_reg tmp
= dst
;
332 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
333 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
338 brw_MOV(p
, brw_message_reg(3), arg1
);
343 BRW_MATH_SATURATE_NONE
,
346 BRW_MATH_DATA_SCALAR
,
350 brw_MOV(p
, dst
, tmp
);
357 static void emit_exp_noalias( struct brw_vs_compile
*c
,
359 struct brw_reg arg0
)
361 struct brw_compile
*p
= &c
->func
;
364 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
) {
365 struct brw_reg tmp
= get_tmp(c
);
366 struct brw_reg tmp_d
= retype(tmp
, BRW_REGISTER_TYPE_D
);
368 /* tmp_d = floor(arg0.x) */
369 brw_RNDD(p
, tmp_d
, brw_swizzle1(arg0
, 0));
371 /* result[0] = 2.0 ^ tmp */
373 /* Adjust exponent for floating point:
376 brw_ADD(p
, brw_writemask(tmp_d
, WRITEMASK_X
), tmp_d
, brw_imm_d(127));
378 /* Install exponent and sign.
379 * Excess drops off the edge:
381 brw_SHL(p
, brw_writemask(retype(dst
, BRW_REGISTER_TYPE_D
), WRITEMASK_X
),
382 tmp_d
, brw_imm_d(23));
387 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
) {
388 /* result[1] = arg0.x - floor(arg0.x) */
389 brw_FRC(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
, 0));
392 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
393 /* As with the LOG instruction, we might be better off just
394 * doing a taylor expansion here, seeing as we have to do all
397 * If mathbox partial precision is too low, consider also:
398 * result[3] = result[0] * EXP(result[1])
401 BRW_MATH_FUNCTION_EXP
,
402 brw_writemask(dst
, WRITEMASK_Z
),
403 brw_swizzle1(arg0
, 0),
404 BRW_MATH_PRECISION_PARTIAL
);
407 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
408 /* result[3] = 1.0; */
409 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), brw_imm_f(1));
414 static void emit_log_noalias( struct brw_vs_compile
*c
,
416 struct brw_reg arg0
)
418 struct brw_compile
*p
= &c
->func
;
419 struct brw_reg tmp
= dst
;
420 struct brw_reg tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
421 struct brw_reg arg0_ud
= retype(arg0
, BRW_REGISTER_TYPE_UD
);
422 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
423 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
427 tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
430 /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt
433 * These almost look likey they could be joined up, but not really
436 * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127
437 * result[1].i = (x.i & ((1<<23)-1) + (127<<23)
439 if (dst
.dw1
.bits
.writemask
& WRITEMASK_XZ
) {
441 brw_writemask(tmp_ud
, WRITEMASK_X
),
442 brw_swizzle1(arg0_ud
, 0),
443 brw_imm_ud((1U<<31)-1));
446 brw_writemask(tmp_ud
, WRITEMASK_X
),
451 brw_writemask(tmp
, WRITEMASK_X
),
452 retype(tmp_ud
, BRW_REGISTER_TYPE_D
), /* does it matter? */
456 if (dst
.dw1
.bits
.writemask
& WRITEMASK_YZ
) {
458 brw_writemask(tmp_ud
, WRITEMASK_Y
),
459 brw_swizzle1(arg0_ud
, 0),
460 brw_imm_ud((1<<23)-1));
463 brw_writemask(tmp_ud
, WRITEMASK_Y
),
465 brw_imm_ud(127<<23));
468 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
469 /* result[2] = result[0] + LOG2(result[1]); */
471 /* Why bother? The above is just a hint how to do this with a
472 * taylor series. Maybe we *should* use a taylor series as by
473 * the time all the above has been done it's almost certainly
474 * quicker than calling the mathbox, even with low precision.
477 * - result[0] + mathbox.LOG2(result[1])
478 * - mathbox.LOG2(arg0.x)
479 * - result[0] + inline_taylor_approx(result[1])
482 BRW_MATH_FUNCTION_LOG
,
483 brw_writemask(tmp
, WRITEMASK_Z
),
484 brw_swizzle1(tmp
, 1),
485 BRW_MATH_PRECISION_FULL
);
488 brw_writemask(tmp
, WRITEMASK_Z
),
489 brw_swizzle1(tmp
, 2),
490 brw_swizzle1(tmp
, 0));
493 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
494 /* result[3] = 1.0; */
495 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_W
), brw_imm_f(1));
499 brw_MOV(p
, dst
, tmp
);
507 /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
509 static void emit_dst_noalias( struct brw_vs_compile
*c
,
514 struct brw_compile
*p
= &c
->func
;
516 /* There must be a better way to do this:
518 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
)
519 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_X
), brw_imm_f(1.0));
520 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
)
521 brw_MUL(p
, brw_writemask(dst
, WRITEMASK_Y
), arg0
, arg1
);
522 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
)
523 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Z
), arg0
);
524 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
)
525 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), arg1
);
528 static void emit_xpd( struct brw_compile
*p
,
533 brw_MUL(p
, brw_null_reg(), brw_swizzle(t
, 1,2,0,3), brw_swizzle(u
,2,0,1,3));
534 brw_MAC(p
, dst
, negate(brw_swizzle(t
, 2,0,1,3)), brw_swizzle(u
,1,2,0,3));
539 static void emit_lit_noalias( struct brw_vs_compile
*c
,
541 struct brw_reg arg0
)
543 struct brw_compile
*p
= &c
->func
;
544 struct brw_instruction
*if_insn
;
545 struct brw_reg tmp
= dst
;
546 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
551 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_YZ
), brw_imm_f(0));
552 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_XW
), brw_imm_f(1));
554 /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order
555 * to get all channels active inside the IF. In the clipping code
556 * we run with NoMask, so it's not an option and we can use
557 * BRW_EXECUTE_1 for all comparisions.
559 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,0), brw_imm_f(0));
560 if_insn
= brw_IF(p
, BRW_EXECUTE_8
);
562 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
,0));
564 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,1), brw_imm_f(0));
565 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_Z
), brw_swizzle1(arg0
,1));
566 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
569 BRW_MATH_FUNCTION_POW
,
570 brw_writemask(dst
, WRITEMASK_Z
),
571 brw_swizzle1(tmp
, 2),
572 brw_swizzle1(arg0
, 3),
573 BRW_MATH_PRECISION_PARTIAL
);
576 brw_ENDIF(p
, if_insn
);
583 /* TODO: relative addressing!
585 static struct brw_reg
get_reg( struct brw_vs_compile
*c
,
591 case PROGRAM_TEMPORARY
:
594 case PROGRAM_STATE_VAR
:
595 assert(c
->regs
[file
][index
].nr
!= 0);
596 return c
->regs
[file
][index
];
597 case PROGRAM_ADDRESS
:
599 return c
->regs
[file
][index
];
601 case PROGRAM_UNDEFINED
: /* undef values */
602 return brw_null_reg();
604 case PROGRAM_LOCAL_PARAM
:
605 case PROGRAM_ENV_PARAM
:
606 case PROGRAM_WRITE_ONLY
:
609 return brw_null_reg();
615 static struct brw_reg
deref( struct brw_vs_compile
*c
,
619 struct brw_compile
*p
= &c
->func
;
620 struct brw_reg tmp
= vec4(get_tmp(c
));
621 struct brw_reg vp_address
= retype(vec1(get_reg(c
, PROGRAM_ADDRESS
, 0)), BRW_REGISTER_TYPE_UW
);
622 GLuint byte_offset
= arg
.nr
* 32 + arg
.subnr
+ offset
* 16;
623 struct brw_reg indirect
= brw_vec4_indirect(0,0);
626 brw_push_insn_state(p
);
627 brw_set_access_mode(p
, BRW_ALIGN_1
);
629 /* This is pretty clunky - load the address register twice and
630 * fetch each 4-dword value in turn. There must be a way to do
631 * this in a single pass, but I couldn't get it to work.
633 brw_ADD(p
, brw_address_reg(0), vp_address
, brw_imm_d(byte_offset
));
634 brw_MOV(p
, tmp
, indirect
);
636 brw_ADD(p
, brw_address_reg(0), suboffset(vp_address
, 8), brw_imm_d(byte_offset
));
637 brw_MOV(p
, suboffset(tmp
, 4), indirect
);
639 brw_pop_insn_state(p
);
646 static void emit_arl( struct brw_vs_compile
*c
,
648 struct brw_reg arg0
)
650 struct brw_compile
*p
= &c
->func
;
651 struct brw_reg tmp
= dst
;
652 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
657 brw_RNDD(p
, tmp
, arg0
);
658 brw_MUL(p
, dst
, tmp
, brw_imm_d(16));
665 /* Will return mangled results for SWZ op. The emit_swz() function
666 * ignores this result and recalculates taking extended swizzles into
669 static struct brw_reg
get_arg( struct brw_vs_compile
*c
,
670 struct prog_src_register src
)
674 if (src
.File
== PROGRAM_UNDEFINED
)
675 return brw_null_reg();
678 reg
= deref(c
, c
->regs
[PROGRAM_STATE_VAR
][0], src
.Index
);
680 reg
= get_reg(c
, src
.File
, src
.Index
);
682 /* Convert 3-bit swizzle to 2-bit.
684 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(GET_SWZ(src
.Swizzle
, 0),
685 GET_SWZ(src
.Swizzle
, 1),
686 GET_SWZ(src
.Swizzle
, 2),
687 GET_SWZ(src
.Swizzle
, 3));
689 /* Note this is ok for non-swizzle instructions:
691 reg
.negate
= src
.NegateBase
? 1 : 0;
697 static struct brw_reg
get_dst( struct brw_vs_compile
*c
,
698 struct prog_dst_register dst
)
700 struct brw_reg reg
= get_reg(c
, dst
.File
, dst
.Index
);
702 reg
.dw1
.bits
.writemask
= dst
.WriteMask
;
710 static void emit_swz( struct brw_vs_compile
*c
,
712 struct prog_src_register src
)
714 struct brw_compile
*p
= &c
->func
;
715 GLuint zeros_mask
= 0;
716 GLuint ones_mask
= 0;
719 GLboolean need_tmp
= (src
.NegateBase
&&
720 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
721 struct brw_reg tmp
= dst
;
727 for (i
= 0; i
< 4; i
++) {
728 if (dst
.dw1
.bits
.writemask
& (1<<i
)) {
729 GLubyte s
= GET_SWZ(src
.Swizzle
, i
);
748 /* Do src first, in case dst aliases src:
754 arg0
= deref(c
, c
->regs
[PROGRAM_STATE_VAR
][0], src
.Index
);
756 arg0
= get_reg(c
, src
.File
, src
.Index
);
758 arg0
= brw_swizzle(arg0
,
759 src_swz
[0], src_swz
[1],
760 src_swz
[2], src_swz
[3]);
762 brw_MOV(p
, brw_writemask(tmp
, src_mask
), arg0
);
766 brw_MOV(p
, brw_writemask(tmp
, zeros_mask
), brw_imm_f(0));
769 brw_MOV(p
, brw_writemask(tmp
, ones_mask
), brw_imm_f(1));
772 brw_MOV(p
, brw_writemask(tmp
, src
.NegateBase
), negate(tmp
));
775 brw_MOV(p
, dst
, tmp
);
782 /* Post-vertex-program processing. Send the results to the URB.
784 static void emit_vertex_write( struct brw_vs_compile
*c
)
786 struct brw_compile
*p
= &c
->func
;
787 struct brw_reg m0
= brw_message_reg(0);
788 struct brw_reg pos
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_HPOS
];
791 if (c
->key
.copy_edgeflag
) {
793 get_reg(c
, PROGRAM_OUTPUT
, VERT_RESULT_EDGE
),
794 get_reg(c
, PROGRAM_INPUT
, VERT_ATTRIB_EDGEFLAG
));
798 /* Build ndc coords? TODO: Shortcircuit when w is known to be one.
800 if (!c
->key
.know_w_is_one
) {
802 emit_math1(c
, BRW_MATH_FUNCTION_INV
, ndc
, brw_swizzle1(pos
, 3), BRW_MATH_PRECISION_FULL
);
803 brw_MUL(p
, brw_writemask(ndc
, WRITEMASK_XYZ
), pos
, ndc
);
809 /* This includes the workaround for -ve rhw, so is no longer an
812 if ((c
->prog_data
.outputs_written
& (1<<VERT_RESULT_PSIZ
)) ||
813 c
->key
.nr_userclip
||
814 !c
->key
.know_w_is_one
)
816 struct brw_reg header1
= retype(get_tmp(c
), BRW_REGISTER_TYPE_UD
);
819 brw_MOV(p
, header1
, brw_imm_ud(0));
821 brw_set_access_mode(p
, BRW_ALIGN_16
);
823 if (c
->prog_data
.outputs_written
& (1<<VERT_RESULT_PSIZ
)) {
824 struct brw_reg psiz
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_PSIZ
];
825 brw_MUL(p
, brw_writemask(header1
, WRITEMASK_W
), brw_swizzle1(psiz
, 0), brw_imm_f(1<<11));
826 brw_AND(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(0x7ff<<8));
830 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
831 brw_set_conditionalmod(p
, BRW_CONDITIONAL_L
);
832 brw_DP4(p
, brw_null_reg(), pos
, c
->userplane
[i
]);
833 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<i
));
834 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
838 /* i965 clipping workaround:
839 * 1) Test for -ve rhw
841 * set ndc = (0,0,0,0)
844 * Later, clipping will detect ucp[6] and ensure the primitive is
845 * clipped against all fixed planes.
847 if (!c
->key
.know_w_is_one
) {
849 vec8(brw_null_reg()),
851 brw_swizzle1(ndc
, 3),
854 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
855 brw_MOV(p
, ndc
, brw_imm_f(0));
856 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
859 brw_set_access_mode(p
, BRW_ALIGN_1
); /* why? */
860 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), header1
);
861 brw_set_access_mode(p
, BRW_ALIGN_16
);
863 release_tmp(c
, header1
);
866 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
870 /* Emit the (interleaved) headers for the two vertices - an 8-reg
871 * of zeros followed by two sets of NDC coordinates:
873 brw_set_access_mode(p
, BRW_ALIGN_1
);
874 brw_MOV(p
, offset(m0
, 2), ndc
);
875 brw_MOV(p
, offset(m0
, 3), pos
);
879 brw_null_reg(), /* dest */
880 0, /* starting mrf reg nr */
884 c
->nr_outputs
+ 3, /* msg len */
885 0, /* response len */
887 1, /* writes complete */
888 0, /* urb destination offset */
889 BRW_URB_SWIZZLE_INTERLEAVE
);
896 /* Emit the fragment program instructions here.
898 void brw_vs_emit( struct brw_vs_compile
*c
)
900 struct brw_compile
*p
= &c
->func
;
901 GLuint nr_insns
= c
->vp
->program
.Base
.NumInstructions
;
905 if (INTEL_DEBUG
& DEBUG_VS
) {
906 _mesa_printf("\n\n\nvs-emit:\n");
907 _mesa_print_program(&c
->vp
->program
.Base
);
911 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
912 brw_set_access_mode(p
, BRW_ALIGN_16
);
914 /* Static register allocation
916 brw_vs_alloc_regs(c
);
918 for (insn
= 0; insn
< nr_insns
; insn
++) {
920 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
921 struct brw_reg args
[3], dst
;
924 /* Get argument regs. SWZ is special and does this itself.
926 if (inst
->Opcode
!= OPCODE_SWZ
)
927 for (i
= 0; i
< 3; i
++)
928 args
[i
] = get_arg(c
, inst
->SrcReg
[i
]);
930 /* Get dest regs. Note that it is possible for a reg to be both
931 * dst and arg, given the static allocation of registers. So
932 * care needs to be taken emitting multi-operation instructions.
934 dst
= get_dst(c
, inst
->DstReg
);
937 switch (inst
->Opcode
) {
939 brw_MOV(p
, dst
, brw_abs(args
[0]));
942 brw_ADD(p
, dst
, args
[0], args
[1]);
945 brw_DP3(p
, dst
, args
[0], args
[1]);
948 brw_DP4(p
, dst
, args
[0], args
[1]);
951 brw_DPH(p
, dst
, args
[0], args
[1]);
954 unalias2(c
, dst
, args
[0], args
[1], emit_dst_noalias
);
957 unalias1(c
, dst
, args
[0], emit_exp_noalias
);
960 emit_math1(c
, BRW_MATH_FUNCTION_EXP
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
963 emit_arl(c
, dst
, args
[0]);
966 brw_RNDD(p
, dst
, args
[0]);
969 brw_FRC(p
, dst
, args
[0]);
972 unalias1(c
, dst
, args
[0], emit_log_noalias
);
975 emit_math1(c
, BRW_MATH_FUNCTION_LOG
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
978 unalias1(c
, dst
, args
[0], emit_lit_noalias
);
981 brw_MOV(p
, brw_acc_reg(), args
[2]);
982 brw_MAC(p
, dst
, args
[0], args
[1]);
985 emit_max(p
, dst
, args
[0], args
[1]);
988 emit_min(p
, dst
, args
[0], args
[1]);
991 brw_MOV(p
, dst
, args
[0]);
994 brw_MUL(p
, dst
, args
[0], args
[1]);
997 emit_math2(c
, BRW_MATH_FUNCTION_POW
, dst
, args
[0], args
[1], BRW_MATH_PRECISION_FULL
);
1000 emit_math1(c
, BRW_MATH_FUNCTION_INV
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1003 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1006 emit_sge(p
, dst
, args
[0], args
[1]);
1009 emit_slt(p
, dst
, args
[0], args
[1]);
1012 brw_ADD(p
, dst
, args
[0], negate(args
[1]));
1015 /* The args[0] value can't be used here as it won't have
1016 * correctly encoded the full swizzle:
1018 emit_swz(c
, dst
, inst
->SrcReg
[0] );
1021 emit_xpd(p
, dst
, args
[0], args
[1]);
1033 emit_vertex_write(c
);