2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/macros.h"
34 #include "program/program.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "brw_context.h"
40 /* Return the SrcReg index of the channels that can be immediate float operands
41 * instead of usage of PROGRAM_CONSTANT values through push/pull.
44 brw_vs_arg_can_be_immediate(enum prog_opcode opcode
, int arg
)
46 int opcode_array
[] = {
64 /* These opcodes get broken down in a way that allow two
65 * args to be immediates.
67 if (opcode
== OPCODE_MAD
|| opcode
== OPCODE_LRP
) {
68 if (arg
== 1 || arg
== 2)
72 if (opcode
> ARRAY_SIZE(opcode_array
))
75 return arg
== opcode_array
[opcode
] - 1;
78 static struct brw_reg
get_tmp( struct brw_vs_compile
*c
)
80 struct brw_reg tmp
= brw_vec8_grf(c
->last_tmp
, 0);
82 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
83 c
->prog_data
.total_grf
= c
->last_tmp
;
88 static void release_tmp( struct brw_vs_compile
*c
, struct brw_reg tmp
)
90 if (tmp
.nr
== c
->last_tmp
-1)
94 static void release_tmps( struct brw_vs_compile
*c
)
96 c
->last_tmp
= c
->first_tmp
;
101 * Preallocate GRF register before code emit.
102 * Do things as simply as possible. Allocate and populate all regs
105 static void brw_vs_alloc_regs( struct brw_vs_compile
*c
)
107 struct intel_context
*intel
= &c
->func
.brw
->intel
;
108 GLuint i
, reg
= 0, mrf
;
109 int attributes_in_vue
;
111 /* Determine whether to use a real constant buffer or use a block
112 * of GRF registers for constants. The later is faster but only
113 * works if everything fits in the GRF.
114 * XXX this heuristic/check may need some fine tuning...
116 if (c
->vp
->program
.Base
.Parameters
->NumParameters
+
117 c
->vp
->program
.Base
.NumTemporaries
+ 20 > BRW_MAX_GRF
)
118 c
->vp
->use_const_buffer
= GL_TRUE
;
120 c
->vp
->use_const_buffer
= GL_FALSE
;
122 /*printf("use_const_buffer = %d\n", c->vp->use_const_buffer);*/
124 /* r0 -- reserved as usual
126 c
->r0
= brw_vec8_grf(reg
, 0);
129 /* User clip planes from curbe:
131 if (c
->key
.nr_userclip
) {
132 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
133 c
->userplane
[i
] = stride( brw_vec4_grf(reg
+3+i
/2, (i
%2) * 4), 0, 4, 1);
136 /* Deal with curbe alignment:
138 reg
+= ((6 + c
->key
.nr_userclip
+ 3) / 4) * 2;
141 /* Vertex program parameters from curbe:
143 if (c
->vp
->use_const_buffer
) {
144 int max_constant
= BRW_MAX_GRF
- 20 - c
->vp
->program
.Base
.NumTemporaries
;
147 /* We've got more constants than we can load with the push
148 * mechanism. This is often correlated with reladdr loads where
149 * we should probably be using a pull mechanism anyway to avoid
150 * excessive reading. However, the pull mechanism is slow in
151 * general. So, we try to allocate as many non-reladdr-loaded
152 * constants through the push buffer as we can before giving up.
154 memset(c
->constant_map
, -1, c
->vp
->program
.Base
.Parameters
->NumParameters
);
156 i
< c
->vp
->program
.Base
.NumInstructions
&& constant
< max_constant
;
158 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[i
];
161 for (arg
= 0; arg
< 3 && constant
< max_constant
; arg
++) {
162 if ((inst
->SrcReg
[arg
].File
!= PROGRAM_STATE_VAR
&&
163 inst
->SrcReg
[arg
].File
!= PROGRAM_CONSTANT
&&
164 inst
->SrcReg
[arg
].File
!= PROGRAM_UNIFORM
&&
165 inst
->SrcReg
[arg
].File
!= PROGRAM_ENV_PARAM
&&
166 inst
->SrcReg
[arg
].File
!= PROGRAM_LOCAL_PARAM
) ||
167 inst
->SrcReg
[arg
].RelAddr
)
170 if (c
->constant_map
[inst
->SrcReg
[arg
].Index
] == -1) {
171 c
->constant_map
[inst
->SrcReg
[arg
].Index
] = constant
++;
176 for (i
= 0; i
< constant
; i
++) {
177 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2,
181 reg
+= (constant
+ 1) / 2;
182 c
->prog_data
.curb_read_length
= reg
- 1;
183 /* XXX 0 causes a bug elsewhere... */
184 c
->prog_data
.nr_params
= MAX2(constant
* 4, 4);
187 /* use a section of the GRF for constants */
188 GLuint nr_params
= c
->vp
->program
.Base
.Parameters
->NumParameters
;
189 for (i
= 0; i
< nr_params
; i
++) {
190 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2, (i
%2) * 4), 0, 4, 1);
192 reg
+= (nr_params
+ 1) / 2;
193 c
->prog_data
.curb_read_length
= reg
- 1;
195 c
->prog_data
.nr_params
= nr_params
* 4;
198 /* Allocate input regs:
201 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
202 if (c
->prog_data
.inputs_read
& (1 << i
)) {
204 c
->regs
[PROGRAM_INPUT
][i
] = brw_vec8_grf(reg
, 0);
208 /* If there are no inputs, we'll still be reading one attribute's worth
209 * because it's required -- see urb_read_length setting.
211 if (c
->nr_inputs
== 0)
214 /* Allocate outputs. The non-position outputs go straight into message regs.
217 c
->first_output
= reg
;
218 c
->first_overflow_output
= 0;
222 else if (intel
->gen
== 5)
227 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
228 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(i
)) {
230 assert(i
< Elements(c
->regs
[PROGRAM_OUTPUT
]));
231 if (i
== VERT_RESULT_HPOS
) {
232 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
235 else if (i
== VERT_RESULT_PSIZ
) {
236 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
238 mrf
++; /* just a placeholder? XXX fix later stages & remove this */
241 /* Two restrictions on our compute-to-MRF here. The
242 * message length for all SEND messages is restricted to
243 * [1,15], so we can't use mrf 15, as that means a length
246 * Additionally, URB writes are aligned to URB rows, so we
247 * need to put an even number of registers of URB data in
248 * each URB write so that the later write is aligned. A
249 * message length of 15 means 1 message header reg plus 14
252 * For attributes beyond the compute-to-MRF, we compute to
253 * GRFs and they will be written in the second URB_WRITE.
256 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_message_reg(mrf
);
260 if (!c
->first_overflow_output
)
261 c
->first_overflow_output
= i
;
262 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
269 /* Allocate program temporaries:
271 for (i
= 0; i
< c
->vp
->program
.Base
.NumTemporaries
; i
++) {
272 c
->regs
[PROGRAM_TEMPORARY
][i
] = brw_vec8_grf(reg
, 0);
276 /* Address reg(s). Don't try to use the internal address reg until
279 for (i
= 0; i
< c
->vp
->program
.Base
.NumAddressRegs
; i
++) {
280 c
->regs
[PROGRAM_ADDRESS
][i
] = brw_reg(BRW_GENERAL_REGISTER_FILE
,
284 BRW_VERTICAL_STRIDE_8
,
286 BRW_HORIZONTAL_STRIDE_1
,
292 if (c
->vp
->use_const_buffer
) {
293 for (i
= 0; i
< 3; i
++) {
294 c
->current_const
[i
].index
= -1;
295 c
->current_const
[i
].reg
= brw_vec8_grf(reg
, 0);
300 for (i
= 0; i
< 128; i
++) {
301 if (c
->output_regs
[i
].used_in_src
) {
302 c
->output_regs
[i
].reg
= brw_vec8_grf(reg
, 0);
307 if (c
->needs_stack
) {
308 c
->stack
= brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, reg
, 0);
312 /* Some opcodes need an internal temporary:
315 c
->last_tmp
= reg
; /* for allocation purposes */
317 /* Each input reg holds data from two vertices. The
318 * urb_read_length is the number of registers read from *each*
319 * vertex urb, so is half the amount:
321 c
->prog_data
.urb_read_length
= (c
->nr_inputs
+ 1) / 2;
322 /* Setting this field to 0 leads to undefined behavior according to the
323 * the VS_STATE docs. Our VUEs will always have at least one attribute
324 * sitting in them, even if it's padding.
326 if (c
->prog_data
.urb_read_length
== 0)
327 c
->prog_data
.urb_read_length
= 1;
329 /* The VS VUEs are shared by VF (outputting our inputs) and VS, so size
330 * them to fit the biggest thing they need to.
332 attributes_in_vue
= MAX2(c
->nr_outputs
, c
->nr_inputs
);
334 /* See emit_vertex_write() for where the VUE's overhead on top of the
335 * attributes comes from.
338 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 2 + 7) / 8;
339 else if (intel
->gen
== 5)
340 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 6 + 3) / 4;
342 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 2 + 3) / 4;
344 c
->prog_data
.total_grf
= reg
;
346 if (INTEL_DEBUG
& DEBUG_VS
) {
347 printf("%s NumAddrRegs %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumAddressRegs
);
348 printf("%s NumTemps %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumTemporaries
);
349 printf("%s reg = %d\n", __FUNCTION__
, reg
);
355 * If an instruction uses a temp reg both as a src and the dest, we
356 * sometimes need to allocate an intermediate temporary.
358 static void unalias1( struct brw_vs_compile
*c
,
361 void (*func
)( struct brw_vs_compile
*,
365 if (dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) {
366 struct brw_compile
*p
= &c
->func
;
367 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
369 brw_MOV(p
, dst
, tmp
);
379 * Checkes if 2-operand instruction needs an intermediate temporary.
381 static void unalias2( struct brw_vs_compile
*c
,
385 void (*func
)( struct brw_vs_compile
*,
390 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
391 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
)) {
392 struct brw_compile
*p
= &c
->func
;
393 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
394 func(c
, tmp
, arg0
, arg1
);
395 brw_MOV(p
, dst
, tmp
);
399 func(c
, dst
, arg0
, arg1
);
405 * Checkes if 3-operand instruction needs an intermediate temporary.
407 static void unalias3( struct brw_vs_compile
*c
,
412 void (*func
)( struct brw_vs_compile
*,
418 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
419 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
) ||
420 (dst
.file
== arg2
.file
&& dst
.nr
== arg2
.nr
)) {
421 struct brw_compile
*p
= &c
->func
;
422 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
423 func(c
, tmp
, arg0
, arg1
, arg2
);
424 brw_MOV(p
, dst
, tmp
);
428 func(c
, dst
, arg0
, arg1
, arg2
);
432 static void emit_sop( struct brw_vs_compile
*c
,
438 struct brw_compile
*p
= &c
->func
;
440 brw_MOV(p
, dst
, brw_imm_f(0.0f
));
441 brw_CMP(p
, brw_null_reg(), cond
, arg0
, arg1
);
442 brw_MOV(p
, dst
, brw_imm_f(1.0f
));
443 brw_set_predicate_control_flag_value(p
, 0xff);
446 static void emit_seq( struct brw_vs_compile
*c
,
449 struct brw_reg arg1
)
451 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_EQ
);
454 static void emit_sne( struct brw_vs_compile
*c
,
457 struct brw_reg arg1
)
459 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_NEQ
);
461 static void emit_slt( struct brw_vs_compile
*c
,
464 struct brw_reg arg1
)
466 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_L
);
469 static void emit_sle( struct brw_vs_compile
*c
,
472 struct brw_reg arg1
)
474 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_LE
);
477 static void emit_sgt( struct brw_vs_compile
*c
,
480 struct brw_reg arg1
)
482 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_G
);
485 static void emit_sge( struct brw_vs_compile
*c
,
488 struct brw_reg arg1
)
490 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_GE
);
493 static void emit_cmp( struct brw_compile
*p
,
497 struct brw_reg arg2
)
499 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, brw_imm_f(0));
500 brw_SEL(p
, dst
, arg1
, arg2
);
501 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
504 static void emit_max( struct brw_compile
*p
,
507 struct brw_reg arg1
)
509 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_GE
, arg0
, arg1
);
510 brw_SEL(p
, dst
, arg0
, arg1
);
511 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
514 static void emit_min( struct brw_compile
*p
,
517 struct brw_reg arg1
)
519 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
520 brw_SEL(p
, dst
, arg0
, arg1
);
521 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
525 static void emit_math1( struct brw_vs_compile
*c
,
531 /* There are various odd behaviours with SEND on the simulator. In
532 * addition there are documented issues with the fact that the GEN4
533 * processor doesn't do dependency control properly on SEND
534 * results. So, on balance, this kludge to get around failures
535 * with writemasked math results looks like it might be necessary
536 * whether that turns out to be a simulator bug or not:
538 struct brw_compile
*p
= &c
->func
;
539 struct intel_context
*intel
= &p
->brw
->intel
;
540 struct brw_reg tmp
= dst
;
541 GLboolean need_tmp
= (intel
->gen
< 6 &&
542 (dst
.dw1
.bits
.writemask
!= 0xf ||
543 dst
.file
!= BRW_GENERAL_REGISTER_FILE
));
551 BRW_MATH_SATURATE_NONE
,
554 BRW_MATH_DATA_SCALAR
,
558 brw_MOV(p
, dst
, tmp
);
564 static void emit_math2( struct brw_vs_compile
*c
,
571 struct brw_compile
*p
= &c
->func
;
572 struct intel_context
*intel
= &p
->brw
->intel
;
573 struct brw_reg tmp
= dst
;
574 GLboolean need_tmp
= (intel
->gen
< 6 &&
575 (dst
.dw1
.bits
.writemask
!= 0xf ||
576 dst
.file
!= BRW_GENERAL_REGISTER_FILE
));
581 brw_MOV(p
, brw_message_reg(3), arg1
);
586 BRW_MATH_SATURATE_NONE
,
589 BRW_MATH_DATA_SCALAR
,
593 brw_MOV(p
, dst
, tmp
);
599 static void emit_exp_noalias( struct brw_vs_compile
*c
,
601 struct brw_reg arg0
)
603 struct brw_compile
*p
= &c
->func
;
606 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
) {
607 struct brw_reg tmp
= get_tmp(c
);
608 struct brw_reg tmp_d
= retype(tmp
, BRW_REGISTER_TYPE_D
);
610 /* tmp_d = floor(arg0.x) */
611 brw_RNDD(p
, tmp_d
, brw_swizzle1(arg0
, 0));
613 /* result[0] = 2.0 ^ tmp */
615 /* Adjust exponent for floating point:
618 brw_ADD(p
, brw_writemask(tmp_d
, WRITEMASK_X
), tmp_d
, brw_imm_d(127));
620 /* Install exponent and sign.
621 * Excess drops off the edge:
623 brw_SHL(p
, brw_writemask(retype(dst
, BRW_REGISTER_TYPE_D
), WRITEMASK_X
),
624 tmp_d
, brw_imm_d(23));
629 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
) {
630 /* result[1] = arg0.x - floor(arg0.x) */
631 brw_FRC(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
, 0));
634 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
635 /* As with the LOG instruction, we might be better off just
636 * doing a taylor expansion here, seeing as we have to do all
639 * If mathbox partial precision is too low, consider also:
640 * result[3] = result[0] * EXP(result[1])
643 BRW_MATH_FUNCTION_EXP
,
644 brw_writemask(dst
, WRITEMASK_Z
),
645 brw_swizzle1(arg0
, 0),
646 BRW_MATH_PRECISION_FULL
);
649 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
650 /* result[3] = 1.0; */
651 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), brw_imm_f(1));
656 static void emit_log_noalias( struct brw_vs_compile
*c
,
658 struct brw_reg arg0
)
660 struct brw_compile
*p
= &c
->func
;
661 struct brw_reg tmp
= dst
;
662 struct brw_reg tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
663 struct brw_reg arg0_ud
= retype(arg0
, BRW_REGISTER_TYPE_UD
);
664 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
665 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
669 tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
672 /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt
675 * These almost look likey they could be joined up, but not really
678 * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127
679 * result[1].i = (x.i & ((1<<23)-1) + (127<<23)
681 if (dst
.dw1
.bits
.writemask
& WRITEMASK_XZ
) {
683 brw_writemask(tmp_ud
, WRITEMASK_X
),
684 brw_swizzle1(arg0_ud
, 0),
685 brw_imm_ud((1U<<31)-1));
688 brw_writemask(tmp_ud
, WRITEMASK_X
),
693 brw_writemask(tmp
, WRITEMASK_X
),
694 retype(tmp_ud
, BRW_REGISTER_TYPE_D
), /* does it matter? */
698 if (dst
.dw1
.bits
.writemask
& WRITEMASK_YZ
) {
700 brw_writemask(tmp_ud
, WRITEMASK_Y
),
701 brw_swizzle1(arg0_ud
, 0),
702 brw_imm_ud((1<<23)-1));
705 brw_writemask(tmp_ud
, WRITEMASK_Y
),
707 brw_imm_ud(127<<23));
710 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
711 /* result[2] = result[0] + LOG2(result[1]); */
713 /* Why bother? The above is just a hint how to do this with a
714 * taylor series. Maybe we *should* use a taylor series as by
715 * the time all the above has been done it's almost certainly
716 * quicker than calling the mathbox, even with low precision.
719 * - result[0] + mathbox.LOG2(result[1])
720 * - mathbox.LOG2(arg0.x)
721 * - result[0] + inline_taylor_approx(result[1])
724 BRW_MATH_FUNCTION_LOG
,
725 brw_writemask(tmp
, WRITEMASK_Z
),
726 brw_swizzle1(tmp
, 1),
727 BRW_MATH_PRECISION_FULL
);
730 brw_writemask(tmp
, WRITEMASK_Z
),
731 brw_swizzle1(tmp
, 2),
732 brw_swizzle1(tmp
, 0));
735 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
736 /* result[3] = 1.0; */
737 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_W
), brw_imm_f(1));
741 brw_MOV(p
, dst
, tmp
);
747 /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
749 static void emit_dst_noalias( struct brw_vs_compile
*c
,
754 struct brw_compile
*p
= &c
->func
;
756 /* There must be a better way to do this:
758 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
)
759 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_X
), brw_imm_f(1.0));
760 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
)
761 brw_MUL(p
, brw_writemask(dst
, WRITEMASK_Y
), arg0
, arg1
);
762 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
)
763 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Z
), arg0
);
764 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
)
765 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), arg1
);
769 static void emit_xpd( struct brw_compile
*p
,
774 brw_MUL(p
, brw_null_reg(), brw_swizzle(t
, 1,2,0,3), brw_swizzle(u
,2,0,1,3));
775 brw_MAC(p
, dst
, negate(brw_swizzle(t
, 2,0,1,3)), brw_swizzle(u
,1,2,0,3));
779 static void emit_lit_noalias( struct brw_vs_compile
*c
,
781 struct brw_reg arg0
)
783 struct brw_compile
*p
= &c
->func
;
784 struct brw_instruction
*if_insn
;
785 struct brw_reg tmp
= dst
;
786 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
791 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_YZ
), brw_imm_f(0));
792 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_XW
), brw_imm_f(1));
794 /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order
795 * to get all channels active inside the IF. In the clipping code
796 * we run with NoMask, so it's not an option and we can use
797 * BRW_EXECUTE_1 for all comparisions.
799 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,0), brw_imm_f(0));
800 if_insn
= brw_IF(p
, BRW_EXECUTE_8
);
802 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
,0));
804 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,1), brw_imm_f(0));
805 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_Z
), brw_swizzle1(arg0
,1));
806 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
809 BRW_MATH_FUNCTION_POW
,
810 brw_writemask(dst
, WRITEMASK_Z
),
811 brw_swizzle1(tmp
, 2),
812 brw_swizzle1(arg0
, 3),
813 BRW_MATH_PRECISION_PARTIAL
);
816 brw_ENDIF(p
, if_insn
);
821 static void emit_lrp_noalias(struct brw_vs_compile
*c
,
827 struct brw_compile
*p
= &c
->func
;
829 brw_ADD(p
, dst
, negate(arg0
), brw_imm_f(1.0));
830 brw_MUL(p
, brw_null_reg(), dst
, arg2
);
831 brw_MAC(p
, dst
, arg0
, arg1
);
834 /** 3 or 4-component vector normalization */
835 static void emit_nrm( struct brw_vs_compile
*c
,
840 struct brw_compile
*p
= &c
->func
;
841 struct brw_reg tmp
= get_tmp(c
);
843 /* tmp = dot(arg0, arg0) */
845 brw_DP3(p
, tmp
, arg0
, arg0
);
847 brw_DP4(p
, tmp
, arg0
, arg0
);
849 /* tmp = 1 / sqrt(tmp) */
850 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, tmp
, tmp
, BRW_MATH_PRECISION_FULL
);
852 /* dst = arg0 * tmp */
853 brw_MUL(p
, dst
, arg0
, tmp
);
859 static struct brw_reg
860 get_constant(struct brw_vs_compile
*c
,
861 const struct prog_instruction
*inst
,
864 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
865 struct brw_compile
*p
= &c
->func
;
866 struct brw_reg const_reg
= c
->current_const
[argIndex
].reg
;
868 assert(argIndex
< 3);
870 if (c
->current_const
[argIndex
].index
!= src
->Index
) {
871 /* Keep track of the last constant loaded in this slot, for reuse. */
872 c
->current_const
[argIndex
].index
= src
->Index
;
875 printf(" fetch const[%d] for arg %d into reg %d\n",
876 src
->Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
878 /* need to fetch the constant now */
880 const_reg
, /* writeback dest */
881 16 * src
->Index
, /* byte offset */
882 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
886 /* replicate lower four floats into upper half (to get XYZWXYZW) */
887 const_reg
= stride(const_reg
, 0, 4, 0);
893 static struct brw_reg
894 get_reladdr_constant(struct brw_vs_compile
*c
,
895 const struct prog_instruction
*inst
,
898 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
899 struct brw_compile
*p
= &c
->func
;
900 struct brw_reg const_reg
= c
->current_const
[argIndex
].reg
;
901 struct brw_reg addrReg
= c
->regs
[PROGRAM_ADDRESS
][0];
903 assert(argIndex
< 3);
905 /* Can't reuse a reladdr constant load. */
906 c
->current_const
[argIndex
].index
= -1;
909 printf(" fetch const[a0.x+%d] for arg %d into reg %d\n",
910 src
->Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
913 /* fetch the first vec4 */
914 brw_dp_READ_4_vs_relative(p
,
915 const_reg
, /* writeback dest */
916 addrReg
, /* address register */
917 16 * src
->Index
, /* byte offset */
918 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
926 /* TODO: relative addressing!
928 static struct brw_reg
get_reg( struct brw_vs_compile
*c
,
929 gl_register_file file
,
933 case PROGRAM_TEMPORARY
:
936 assert(c
->regs
[file
][index
].nr
!= 0);
937 return c
->regs
[file
][index
];
938 case PROGRAM_STATE_VAR
:
939 case PROGRAM_CONSTANT
:
940 case PROGRAM_UNIFORM
:
941 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
942 return c
->regs
[PROGRAM_STATE_VAR
][index
];
943 case PROGRAM_ADDRESS
:
945 return c
->regs
[file
][index
];
947 case PROGRAM_UNDEFINED
: /* undef values */
948 return brw_null_reg();
950 case PROGRAM_LOCAL_PARAM
:
951 case PROGRAM_ENV_PARAM
:
952 case PROGRAM_WRITE_ONLY
:
955 return brw_null_reg();
961 * Indirect addressing: get reg[[arg] + offset].
963 static struct brw_reg
deref( struct brw_vs_compile
*c
,
967 struct brw_compile
*p
= &c
->func
;
968 struct brw_reg tmp
= vec4(get_tmp(c
));
969 struct brw_reg addr_reg
= c
->regs
[PROGRAM_ADDRESS
][0];
970 struct brw_reg vp_address
= retype(vec1(addr_reg
), BRW_REGISTER_TYPE_UW
);
971 GLuint byte_offset
= arg
.nr
* 32 + arg
.subnr
+ offset
* 16;
972 struct brw_reg indirect
= brw_vec4_indirect(0,0);
975 brw_push_insn_state(p
);
976 brw_set_access_mode(p
, BRW_ALIGN_1
);
978 /* This is pretty clunky - load the address register twice and
979 * fetch each 4-dword value in turn. There must be a way to do
980 * this in a single pass, but I couldn't get it to work.
982 brw_ADD(p
, brw_address_reg(0), vp_address
, brw_imm_d(byte_offset
));
983 brw_MOV(p
, tmp
, indirect
);
985 brw_ADD(p
, brw_address_reg(0), suboffset(vp_address
, 8), brw_imm_d(byte_offset
));
986 brw_MOV(p
, suboffset(tmp
, 4), indirect
);
988 brw_pop_insn_state(p
);
991 /* NOTE: tmp not released */
997 * Get brw reg corresponding to the instruction's [argIndex] src reg.
998 * TODO: relative addressing!
1000 static struct brw_reg
1001 get_src_reg( struct brw_vs_compile
*c
,
1002 const struct prog_instruction
*inst
,
1005 const GLuint file
= inst
->SrcReg
[argIndex
].File
;
1006 const GLint index
= inst
->SrcReg
[argIndex
].Index
;
1007 const GLboolean relAddr
= inst
->SrcReg
[argIndex
].RelAddr
;
1009 if (brw_vs_arg_can_be_immediate(inst
->Opcode
, argIndex
)) {
1010 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
1012 if (src
->Swizzle
== MAKE_SWIZZLE4(SWIZZLE_ZERO
,
1016 return brw_imm_f(0.0f
);
1017 } else if (src
->Swizzle
== MAKE_SWIZZLE4(SWIZZLE_ONE
,
1022 return brw_imm_f(-1.0F
);
1024 return brw_imm_f(1.0F
);
1025 } else if (src
->File
== PROGRAM_CONSTANT
) {
1026 const struct gl_program_parameter_list
*params
;
1030 switch (src
->Swizzle
) {
1045 if (component
>= 0) {
1046 params
= c
->vp
->program
.Base
.Parameters
;
1047 f
= params
->ParameterValues
[src
->Index
][component
];
1053 return brw_imm_f(f
);
1059 case PROGRAM_TEMPORARY
:
1061 case PROGRAM_OUTPUT
:
1063 return deref(c
, c
->regs
[file
][0], index
);
1066 assert(c
->regs
[file
][index
].nr
!= 0);
1067 return c
->regs
[file
][index
];
1070 case PROGRAM_STATE_VAR
:
1071 case PROGRAM_CONSTANT
:
1072 case PROGRAM_UNIFORM
:
1073 case PROGRAM_ENV_PARAM
:
1074 case PROGRAM_LOCAL_PARAM
:
1075 if (c
->vp
->use_const_buffer
) {
1076 if (!relAddr
&& c
->constant_map
[index
] != -1) {
1077 assert(c
->regs
[PROGRAM_STATE_VAR
][c
->constant_map
[index
]].nr
!= 0);
1078 return c
->regs
[PROGRAM_STATE_VAR
][c
->constant_map
[index
]];
1080 return get_reladdr_constant(c
, inst
, argIndex
);
1082 return get_constant(c
, inst
, argIndex
);
1085 return deref(c
, c
->regs
[PROGRAM_STATE_VAR
][0], index
);
1088 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
1089 return c
->regs
[PROGRAM_STATE_VAR
][index
];
1091 case PROGRAM_ADDRESS
:
1093 return c
->regs
[file
][index
];
1095 case PROGRAM_UNDEFINED
:
1096 /* this is a normal case since we loop over all three src args */
1097 return brw_null_reg();
1099 case PROGRAM_WRITE_ONLY
:
1102 return brw_null_reg();
1107 static void emit_arl( struct brw_vs_compile
*c
,
1109 struct brw_reg arg0
)
1111 struct brw_compile
*p
= &c
->func
;
1112 struct brw_reg tmp
= dst
;
1113 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
1118 brw_RNDD(p
, tmp
, arg0
); /* tmp = round(arg0) */
1119 brw_MUL(p
, dst
, tmp
, brw_imm_d(16)); /* dst = tmp * 16 */
1122 release_tmp(c
, tmp
);
1127 * Return the brw reg for the given instruction's src argument.
1128 * Will return mangled results for SWZ op. The emit_swz() function
1129 * ignores this result and recalculates taking extended swizzles into
1132 static struct brw_reg
get_arg( struct brw_vs_compile
*c
,
1133 const struct prog_instruction
*inst
,
1136 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
1139 if (src
->File
== PROGRAM_UNDEFINED
)
1140 return brw_null_reg();
1142 reg
= get_src_reg(c
, inst
, argIndex
);
1144 /* Convert 3-bit swizzle to 2-bit.
1146 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(GET_SWZ(src
->Swizzle
, 0),
1147 GET_SWZ(src
->Swizzle
, 1),
1148 GET_SWZ(src
->Swizzle
, 2),
1149 GET_SWZ(src
->Swizzle
, 3));
1151 /* Note this is ok for non-swizzle instructions:
1153 reg
.negate
= src
->Negate
? 1 : 0;
1160 * Get brw register for the given program dest register.
1162 static struct brw_reg
get_dst( struct brw_vs_compile
*c
,
1163 struct prog_dst_register dst
)
1168 case PROGRAM_TEMPORARY
:
1169 case PROGRAM_OUTPUT
:
1170 assert(c
->regs
[dst
.File
][dst
.Index
].nr
!= 0);
1171 reg
= c
->regs
[dst
.File
][dst
.Index
];
1173 case PROGRAM_ADDRESS
:
1174 assert(dst
.Index
== 0);
1175 reg
= c
->regs
[dst
.File
][dst
.Index
];
1177 case PROGRAM_UNDEFINED
:
1178 /* we may hit this for OPCODE_END, OPCODE_KIL, etc */
1179 reg
= brw_null_reg();
1183 reg
= brw_null_reg();
1186 reg
.dw1
.bits
.writemask
= dst
.WriteMask
;
1192 static void emit_swz( struct brw_vs_compile
*c
,
1194 const struct prog_instruction
*inst
)
1196 const GLuint argIndex
= 0;
1197 const struct prog_src_register src
= inst
->SrcReg
[argIndex
];
1198 struct brw_compile
*p
= &c
->func
;
1199 GLuint zeros_mask
= 0;
1200 GLuint ones_mask
= 0;
1201 GLuint src_mask
= 0;
1203 GLboolean need_tmp
= (src
.Negate
&&
1204 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
1205 struct brw_reg tmp
= dst
;
1211 for (i
= 0; i
< 4; i
++) {
1212 if (dst
.dw1
.bits
.writemask
& (1<<i
)) {
1213 GLubyte s
= GET_SWZ(src
.Swizzle
, i
);
1232 /* Do src first, in case dst aliases src:
1235 struct brw_reg arg0
;
1237 arg0
= get_src_reg(c
, inst
, argIndex
);
1239 arg0
= brw_swizzle(arg0
,
1240 src_swz
[0], src_swz
[1],
1241 src_swz
[2], src_swz
[3]);
1243 brw_MOV(p
, brw_writemask(tmp
, src_mask
), arg0
);
1247 brw_MOV(p
, brw_writemask(tmp
, zeros_mask
), brw_imm_f(0));
1250 brw_MOV(p
, brw_writemask(tmp
, ones_mask
), brw_imm_f(1));
1253 brw_MOV(p
, brw_writemask(tmp
, src
.Negate
), negate(tmp
));
1256 brw_MOV(p
, dst
, tmp
);
1257 release_tmp(c
, tmp
);
1263 * Post-vertex-program processing. Send the results to the URB.
1265 static void emit_vertex_write( struct brw_vs_compile
*c
)
1267 struct brw_compile
*p
= &c
->func
;
1268 struct brw_context
*brw
= p
->brw
;
1269 struct intel_context
*intel
= &brw
->intel
;
1270 struct brw_reg pos
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_HPOS
];
1273 GLuint len_vertex_header
= 2;
1275 if (c
->key
.copy_edgeflag
) {
1277 get_reg(c
, PROGRAM_OUTPUT
, VERT_RESULT_EDGE
),
1278 get_reg(c
, PROGRAM_INPUT
, VERT_ATTRIB_EDGEFLAG
));
1281 if (intel
->gen
< 6) {
1282 /* Build ndc coords */
1284 /* ndc = 1.0 / pos.w */
1285 emit_math1(c
, BRW_MATH_FUNCTION_INV
, ndc
, brw_swizzle1(pos
, 3), BRW_MATH_PRECISION_FULL
);
1286 /* ndc.xyz = pos * ndc */
1287 brw_MUL(p
, brw_writemask(ndc
, WRITEMASK_XYZ
), pos
, ndc
);
1290 /* Update the header for point size, user clipping flags, and -ve rhw
1293 if ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
1294 c
->key
.nr_userclip
|| brw
->has_negative_rhw_bug
)
1296 struct brw_reg header1
= retype(get_tmp(c
), BRW_REGISTER_TYPE_UD
);
1299 brw_MOV(p
, header1
, brw_imm_ud(0));
1301 brw_set_access_mode(p
, BRW_ALIGN_16
);
1303 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1304 struct brw_reg psiz
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_PSIZ
];
1305 brw_MUL(p
, brw_writemask(header1
, WRITEMASK_W
), brw_swizzle1(psiz
, 0), brw_imm_f(1<<11));
1306 brw_AND(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(0x7ff<<8));
1309 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1310 brw_set_conditionalmod(p
, BRW_CONDITIONAL_L
);
1311 brw_DP4(p
, brw_null_reg(), pos
, c
->userplane
[i
]);
1312 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<i
));
1313 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1316 /* i965 clipping workaround:
1317 * 1) Test for -ve rhw
1319 * set ndc = (0,0,0,0)
1322 * Later, clipping will detect ucp[6] and ensure the primitive is
1323 * clipped against all fixed planes.
1325 if (brw
->has_negative_rhw_bug
) {
1327 vec8(brw_null_reg()),
1329 brw_swizzle1(ndc
, 3),
1332 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1333 brw_MOV(p
, ndc
, brw_imm_f(0));
1334 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1337 brw_set_access_mode(p
, BRW_ALIGN_1
); /* why? */
1338 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), header1
);
1339 brw_set_access_mode(p
, BRW_ALIGN_16
);
1341 release_tmp(c
, header1
);
1344 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
1347 /* Emit the (interleaved) headers for the two vertices - an 8-reg
1348 * of zeros followed by two sets of NDC coordinates:
1350 brw_set_access_mode(p
, BRW_ALIGN_1
);
1352 /* The VUE layout is documented in Volume 2a. */
1353 if (intel
->gen
>= 6) {
1354 /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
1355 * dword 0-3 (m1) of the header is indices, point width, clip flags.
1356 * dword 4-7 (m2) is the 4D space position
1357 * dword 8-15 (m3,m4) of the vertex header is the user clip distance if
1358 * enabled. We don't use it, so skip it.
1359 * m3 is the first vertex element data we fill, which is the vertex
1362 brw_MOV(p
, brw_message_reg(2), pos
);
1363 brw_MOV(p
, brw_message_reg(3), pos
);
1364 len_vertex_header
= 2;
1365 } else if (intel
->gen
== 5) {
1366 /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
1367 * dword 0-3 (m1) of the header is indices, point width, clip flags.
1368 * dword 4-7 (m2) is the ndc position (set above)
1369 * dword 8-11 (m3) of the vertex header is the 4D space position
1370 * dword 12-19 (m4,m5) of the vertex header is the user clip distance.
1371 * m6 is a pad so that the vertex element data is aligned
1372 * m7 is the first vertex data we fill, which is the vertex position.
1374 brw_MOV(p
, brw_message_reg(2), ndc
);
1375 brw_MOV(p
, brw_message_reg(3), pos
);
1376 brw_MOV(p
, brw_message_reg(7), pos
);
1377 len_vertex_header
= 6;
1379 /* There are 8 dwords in VUE header pre-Ironlake:
1380 * dword 0-3 (m1) is indices, point width, clip flags.
1381 * dword 4-7 (m2) is ndc position (set above)
1383 * dword 8-11 (m3) is the first vertex data, which we always have be the
1386 brw_MOV(p
, brw_message_reg(2), ndc
);
1387 brw_MOV(p
, brw_message_reg(3), pos
);
1388 len_vertex_header
= 2;
1391 eot
= (c
->first_overflow_output
== 0);
1394 brw_null_reg(), /* dest */
1395 0, /* starting mrf reg nr */
1399 MIN2(c
->nr_outputs
+ 1 + len_vertex_header
, (BRW_MAX_MRF
-1)), /* msg len */
1400 0, /* response len */
1402 eot
, /* writes complete */
1403 0, /* urb destination offset */
1404 BRW_URB_SWIZZLE_INTERLEAVE
);
1406 if (c
->first_overflow_output
> 0) {
1407 /* Not all of the vertex outputs/results fit into the MRF.
1408 * Move the overflowed attributes from the GRF to the MRF and
1409 * issue another brw_urb_WRITE().
1412 for (i
= c
->first_overflow_output
; i
< VERT_RESULT_MAX
; i
++) {
1413 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(i
)) {
1414 /* move from GRF to MRF */
1415 brw_MOV(p
, brw_message_reg(mrf
), c
->regs
[PROGRAM_OUTPUT
][i
]);
1421 brw_null_reg(), /* dest */
1422 0, /* starting mrf reg nr */
1427 0, /* response len */
1429 1, /* writes complete */
1430 14 / 2, /* urb destination offset */
1431 BRW_URB_SWIZZLE_INTERLEAVE
);
1436 accumulator_contains(struct brw_vs_compile
*c
, struct brw_reg val
)
1438 struct brw_compile
*p
= &c
->func
;
1439 struct brw_instruction
*prev_insn
= &p
->store
[p
->nr_insn
- 1];
1441 if (p
->nr_insn
== 0)
1444 if (val
.address_mode
!= BRW_ADDRESS_DIRECT
)
1447 switch (prev_insn
->header
.opcode
) {
1448 case BRW_OPCODE_MOV
:
1449 case BRW_OPCODE_MAC
:
1450 case BRW_OPCODE_MUL
:
1451 if (prev_insn
->header
.access_mode
== BRW_ALIGN_16
&&
1452 prev_insn
->header
.execution_size
== val
.width
&&
1453 prev_insn
->bits1
.da1
.dest_reg_file
== val
.file
&&
1454 prev_insn
->bits1
.da1
.dest_reg_type
== val
.type
&&
1455 prev_insn
->bits1
.da1
.dest_address_mode
== val
.address_mode
&&
1456 prev_insn
->bits1
.da1
.dest_reg_nr
== val
.nr
&&
1457 prev_insn
->bits1
.da16
.dest_subreg_nr
== val
.subnr
/ 16 &&
1458 prev_insn
->bits1
.da16
.dest_writemask
== 0xf)
1468 get_predicate(const struct prog_instruction
*inst
)
1470 if (inst
->DstReg
.CondMask
== COND_TR
)
1471 return BRW_PREDICATE_NONE
;
1473 /* All of GLSL only produces predicates for COND_NE and one channel per
1474 * vector. Fail badly if someone starts doing something else, as it might
1475 * mean infinite looping or something.
1477 * We'd like to support all the condition codes, but our hardware doesn't
1478 * quite match the Mesa IR, which is modeled after the NV extensions. For
1479 * those, the instruction may update the condition codes or not, then any
1480 * later instruction may use one of those condition codes. For gen4, the
1481 * instruction may update the flags register based on one of the condition
1482 * codes output by the instruction, and then further instructions may
1483 * predicate on that. We can probably support this, but it won't
1484 * necessarily be easy.
1486 assert(inst
->DstReg
.CondMask
== COND_NE
);
1488 switch (inst
->DstReg
.CondSwizzle
) {
1490 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1492 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1494 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1496 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1498 _mesa_problem(NULL
, "Unexpected predicate: 0x%08x\n",
1499 inst
->DstReg
.CondMask
);
1500 return BRW_PREDICATE_NORMAL
;
1504 /* Emit the vertex program instructions here.
1506 void brw_vs_emit(struct brw_vs_compile
*c
)
1508 #define MAX_IF_DEPTH 32
1509 #define MAX_LOOP_DEPTH 32
1510 struct brw_compile
*p
= &c
->func
;
1511 struct brw_context
*brw
= p
->brw
;
1512 struct intel_context
*intel
= &brw
->intel
;
1513 const GLuint nr_insns
= c
->vp
->program
.Base
.NumInstructions
;
1514 GLuint insn
, if_depth
= 0, loop_depth
= 0;
1515 struct brw_instruction
*if_inst
[MAX_IF_DEPTH
], *loop_inst
[MAX_LOOP_DEPTH
] = { 0 };
1516 const struct brw_indirect stack_index
= brw_indirect(0, 0);
1520 if (INTEL_DEBUG
& DEBUG_VS
) {
1521 printf("vs-mesa:\n");
1522 _mesa_print_program(&c
->vp
->program
.Base
);
1526 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1527 brw_set_access_mode(p
, BRW_ALIGN_16
);
1529 for (insn
= 0; insn
< nr_insns
; insn
++) {
1531 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1533 /* Message registers can't be read, so copy the output into GRF
1534 * register if they are used in source registers
1536 for (i
= 0; i
< 3; i
++) {
1537 struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1538 GLuint index
= src
->Index
;
1539 GLuint file
= src
->File
;
1540 if (file
== PROGRAM_OUTPUT
&& index
!= VERT_RESULT_HPOS
)
1541 c
->output_regs
[index
].used_in_src
= GL_TRUE
;
1544 switch (inst
->Opcode
) {
1547 c
->needs_stack
= GL_TRUE
;
1554 /* Static register allocation
1556 brw_vs_alloc_regs(c
);
1559 brw_MOV(p
, get_addr_reg(stack_index
), brw_address(c
->stack
));
1561 for (insn
= 0; insn
< nr_insns
; insn
++) {
1563 const struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1564 struct brw_reg args
[3], dst
;
1568 printf("%d: ", insn
);
1569 _mesa_print_instruction(inst
);
1572 /* Get argument regs. SWZ is special and does this itself.
1574 if (inst
->Opcode
!= OPCODE_SWZ
)
1575 for (i
= 0; i
< 3; i
++) {
1576 const struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1579 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1580 args
[i
] = c
->output_regs
[index
].reg
;
1582 args
[i
] = get_arg(c
, inst
, i
);
1585 /* Get dest regs. Note that it is possible for a reg to be both
1586 * dst and arg, given the static allocation of registers. So
1587 * care needs to be taken emitting multi-operation instructions.
1589 index
= inst
->DstReg
.Index
;
1590 file
= inst
->DstReg
.File
;
1591 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1592 dst
= c
->output_regs
[index
].reg
;
1594 dst
= get_dst(c
, inst
->DstReg
);
1596 if (inst
->SaturateMode
!= SATURATE_OFF
) {
1597 _mesa_problem(NULL
, "Unsupported saturate %d in vertex shader",
1598 inst
->SaturateMode
);
1601 switch (inst
->Opcode
) {
1603 brw_MOV(p
, dst
, brw_abs(args
[0]));
1606 brw_ADD(p
, dst
, args
[0], args
[1]);
1609 emit_math1(c
, BRW_MATH_FUNCTION_COS
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1612 brw_DP3(p
, dst
, args
[0], args
[1]);
1615 brw_DP4(p
, dst
, args
[0], args
[1]);
1618 brw_DPH(p
, dst
, args
[0], args
[1]);
1621 emit_nrm(c
, dst
, args
[0], 3);
1624 emit_nrm(c
, dst
, args
[0], 4);
1627 unalias2(c
, dst
, args
[0], args
[1], emit_dst_noalias
);
1630 unalias1(c
, dst
, args
[0], emit_exp_noalias
);
1633 emit_math1(c
, BRW_MATH_FUNCTION_EXP
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1636 emit_arl(c
, dst
, args
[0]);
1639 brw_RNDD(p
, dst
, args
[0]);
1642 brw_FRC(p
, dst
, args
[0]);
1645 unalias1(c
, dst
, args
[0], emit_log_noalias
);
1648 emit_math1(c
, BRW_MATH_FUNCTION_LOG
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1651 unalias1(c
, dst
, args
[0], emit_lit_noalias
);
1654 unalias3(c
, dst
, args
[0], args
[1], args
[2], emit_lrp_noalias
);
1657 if (!accumulator_contains(c
, args
[2]))
1658 brw_MOV(p
, brw_acc_reg(), args
[2]);
1659 brw_MAC(p
, dst
, args
[0], args
[1]);
1662 emit_cmp(p
, dst
, args
[0], args
[1], args
[2]);
1665 emit_max(p
, dst
, args
[0], args
[1]);
1668 emit_min(p
, dst
, args
[0], args
[1]);
1671 brw_MOV(p
, dst
, args
[0]);
1674 brw_MUL(p
, dst
, args
[0], args
[1]);
1677 emit_math2(c
, BRW_MATH_FUNCTION_POW
, dst
, args
[0], args
[1], BRW_MATH_PRECISION_FULL
);
1680 emit_math1(c
, BRW_MATH_FUNCTION_INV
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1683 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1687 unalias2(c
, dst
, args
[0], args
[1], emit_seq
);
1690 emit_math1(c
, BRW_MATH_FUNCTION_SIN
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1693 unalias2(c
, dst
, args
[0], args
[1], emit_sne
);
1696 unalias2(c
, dst
, args
[0], args
[1], emit_sge
);
1699 unalias2(c
, dst
, args
[0], args
[1], emit_sgt
);
1702 unalias2(c
, dst
, args
[0], args
[1], emit_slt
);
1705 unalias2(c
, dst
, args
[0], args
[1], emit_sle
);
1708 brw_ADD(p
, dst
, args
[0], negate(args
[1]));
1711 /* The args[0] value can't be used here as it won't have
1712 * correctly encoded the full swizzle:
1714 emit_swz(c
, dst
, inst
);
1717 /* round toward zero */
1718 brw_RNDZ(p
, dst
, args
[0]);
1721 emit_xpd(p
, dst
, args
[0], args
[1]);
1724 assert(if_depth
< MAX_IF_DEPTH
);
1725 if_inst
[if_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1726 /* Note that brw_IF smashes the predicate_control field. */
1727 if_inst
[if_depth
]->header
.predicate_control
= get_predicate(inst
);
1731 assert(if_depth
> 0);
1732 if_inst
[if_depth
-1] = brw_ELSE(p
, if_inst
[if_depth
-1]);
1735 assert(if_depth
> 0);
1736 brw_ENDIF(p
, if_inst
[--if_depth
]);
1738 case OPCODE_BGNLOOP
:
1739 loop_inst
[loop_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
1742 brw_set_predicate_control(p
, get_predicate(inst
));
1744 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1747 brw_set_predicate_control(p
, get_predicate(inst
));
1749 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1751 case OPCODE_ENDLOOP
:
1753 struct brw_instruction
*inst0
, *inst1
;
1758 if (intel
->gen
== 5)
1761 inst0
= inst1
= brw_WHILE(p
, loop_inst
[loop_depth
]);
1762 /* patch all the BREAK/CONT instructions from last BEGINLOOP */
1763 while (inst0
> loop_inst
[loop_depth
]) {
1765 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
1766 inst0
->bits3
.if_else
.jump_count
== 0) {
1767 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
1768 inst0
->bits3
.if_else
.pop_count
= 0;
1770 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
1771 inst0
->bits3
.if_else
.jump_count
== 0) {
1772 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
1773 inst0
->bits3
.if_else
.pop_count
= 0;
1779 brw_set_predicate_control(p
, get_predicate(inst
));
1780 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1781 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1784 brw_set_access_mode(p
, BRW_ALIGN_1
);
1785 brw_ADD(p
, deref_1d(stack_index
, 0), brw_ip_reg(), brw_imm_d(3*16));
1786 brw_set_access_mode(p
, BRW_ALIGN_16
);
1787 brw_ADD(p
, get_addr_reg(stack_index
),
1788 get_addr_reg(stack_index
), brw_imm_d(4));
1789 brw_save_call(p
, inst
->Comment
, p
->nr_insn
);
1790 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1793 brw_ADD(p
, get_addr_reg(stack_index
),
1794 get_addr_reg(stack_index
), brw_imm_d(-4));
1795 brw_set_access_mode(p
, BRW_ALIGN_1
);
1796 brw_MOV(p
, brw_ip_reg(), deref_1d(stack_index
, 0));
1797 brw_set_access_mode(p
, BRW_ALIGN_16
);
1800 emit_vertex_write(c
);
1806 brw_save_label(p
, inst
->Comment
, p
->nr_insn
);
1812 _mesa_problem(NULL
, "Unsupported opcode %i (%s) in vertex shader",
1813 inst
->Opcode
, inst
->Opcode
< MAX_OPCODE
?
1814 _mesa_opcode_string(inst
->Opcode
) :
1818 /* Set the predication update on the last instruction of the native
1819 * instruction sequence.
1821 * This would be problematic if it was set on a math instruction,
1822 * but that shouldn't be the case with the current GLSL compiler.
1824 if (inst
->CondUpdate
) {
1825 struct brw_instruction
*hw_insn
= &p
->store
[p
->nr_insn
- 1];
1827 assert(hw_insn
->header
.destreg__conditionalmod
== 0);
1828 hw_insn
->header
.destreg__conditionalmod
= BRW_CONDITIONAL_NZ
;
1831 if ((inst
->DstReg
.File
== PROGRAM_OUTPUT
)
1832 && (inst
->DstReg
.Index
!= VERT_RESULT_HPOS
)
1833 && c
->output_regs
[inst
->DstReg
.Index
].used_in_src
) {
1834 brw_MOV(p
, get_dst(c
, inst
->DstReg
), dst
);
1837 /* Result color clamping.
1839 * When destination register is an output register and
1840 * it's primary/secondary front/back color, we have to clamp
1841 * the result to [0,1]. This is done by enabling the
1842 * saturation bit for the last instruction.
1844 * We don't use brw_set_saturate() as it modifies
1845 * p->current->header.saturate, which affects all the subsequent
1846 * instructions. Instead, we directly modify the header
1847 * of the last (already stored) instruction.
1849 if (inst
->DstReg
.File
== PROGRAM_OUTPUT
) {
1850 if ((inst
->DstReg
.Index
== VERT_RESULT_COL0
)
1851 || (inst
->DstReg
.Index
== VERT_RESULT_COL1
)
1852 || (inst
->DstReg
.Index
== VERT_RESULT_BFC0
)
1853 || (inst
->DstReg
.Index
== VERT_RESULT_BFC1
)) {
1854 p
->store
[p
->nr_insn
-1].header
.saturate
= 1;
1861 brw_resolve_cals(p
);
1865 if (INTEL_DEBUG
& DEBUG_VS
) {
1868 printf("vs-native:\n");
1869 for (i
= 0; i
< p
->nr_insn
; i
++)
1870 brw_disasm(stderr
, &p
->store
[i
], intel
->gen
);