2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/macros.h"
34 #include "shader/program.h"
35 #include "shader/prog_parameter.h"
36 #include "shader/prog_print.h"
37 #include "brw_context.h"
40 /* Return the SrcReg index of the channels that can be immediate float operands
41 * instead of usage of PROGRAM_CONSTANT values through push/pull.
44 brw_vs_arg_can_be_immediate(enum prog_opcode opcode
, int arg
)
46 int opcode_array
[] = {
64 /* These opcodes get broken down in a way that allow two
65 * args to be immediates.
67 if (opcode
== OPCODE_MAD
|| opcode
== OPCODE_LRP
) {
68 if (arg
== 1 || arg
== 2)
72 if (opcode
> ARRAY_SIZE(opcode_array
))
75 return arg
== opcode_array
[opcode
] - 1;
78 static struct brw_reg
get_tmp( struct brw_vs_compile
*c
)
80 struct brw_reg tmp
= brw_vec8_grf(c
->last_tmp
, 0);
82 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
83 c
->prog_data
.total_grf
= c
->last_tmp
;
88 static void release_tmp( struct brw_vs_compile
*c
, struct brw_reg tmp
)
90 if (tmp
.nr
== c
->last_tmp
-1)
94 static void release_tmps( struct brw_vs_compile
*c
)
96 c
->last_tmp
= c
->first_tmp
;
101 * Preallocate GRF register before code emit.
102 * Do things as simply as possible. Allocate and populate all regs
105 static void brw_vs_alloc_regs( struct brw_vs_compile
*c
)
107 struct intel_context
*intel
= &c
->func
.brw
->intel
;
108 GLuint i
, reg
= 0, mrf
;
109 int attributes_in_vue
;
111 /* Determine whether to use a real constant buffer or use a block
112 * of GRF registers for constants. The later is faster but only
113 * works if everything fits in the GRF.
114 * XXX this heuristic/check may need some fine tuning...
116 if (c
->vp
->program
.Base
.Parameters
->NumParameters
+
117 c
->vp
->program
.Base
.NumTemporaries
+ 20 > BRW_MAX_GRF
)
118 c
->vp
->use_const_buffer
= GL_TRUE
;
120 c
->vp
->use_const_buffer
= GL_FALSE
;
122 /*printf("use_const_buffer = %d\n", c->vp->use_const_buffer);*/
124 /* r0 -- reserved as usual
126 c
->r0
= brw_vec8_grf(reg
, 0);
129 /* User clip planes from curbe:
131 if (c
->key
.nr_userclip
) {
132 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
133 c
->userplane
[i
] = stride( brw_vec4_grf(reg
+3+i
/2, (i
%2) * 4), 0, 4, 1);
136 /* Deal with curbe alignment:
138 reg
+= ((6 + c
->key
.nr_userclip
+ 3) / 4) * 2;
141 /* Vertex program parameters from curbe:
143 if (c
->vp
->use_const_buffer
) {
144 int max_constant
= BRW_MAX_GRF
- 20 - c
->vp
->program
.Base
.NumTemporaries
;
147 /* We've got more constants than we can load with the push
148 * mechanism. This is often correlated with reladdr loads where
149 * we should probably be using a pull mechanism anyway to avoid
150 * excessive reading. However, the pull mechanism is slow in
151 * general. So, we try to allocate as many non-reladdr-loaded
152 * constants through the push buffer as we can before giving up.
154 memset(c
->constant_map
, -1, c
->vp
->program
.Base
.Parameters
->NumParameters
);
156 i
< c
->vp
->program
.Base
.NumInstructions
&& constant
< max_constant
;
158 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[i
];
161 for (arg
= 0; arg
< 3 && constant
< max_constant
; arg
++) {
162 if ((inst
->SrcReg
[arg
].File
!= PROGRAM_STATE_VAR
&&
163 inst
->SrcReg
[arg
].File
!= PROGRAM_CONSTANT
&&
164 inst
->SrcReg
[arg
].File
!= PROGRAM_UNIFORM
&&
165 inst
->SrcReg
[arg
].File
!= PROGRAM_ENV_PARAM
&&
166 inst
->SrcReg
[arg
].File
!= PROGRAM_LOCAL_PARAM
) ||
167 inst
->SrcReg
[arg
].RelAddr
)
170 if (c
->constant_map
[inst
->SrcReg
[arg
].Index
] == -1) {
171 c
->constant_map
[inst
->SrcReg
[arg
].Index
] = constant
++;
176 for (i
= 0; i
< constant
; i
++) {
177 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2,
181 reg
+= (constant
+ 1) / 2;
182 c
->prog_data
.curb_read_length
= reg
- 1;
183 /* XXX 0 causes a bug elsewhere... */
184 c
->prog_data
.nr_params
= MAX2(constant
* 4, 4);
187 /* use a section of the GRF for constants */
188 GLuint nr_params
= c
->vp
->program
.Base
.Parameters
->NumParameters
;
189 for (i
= 0; i
< nr_params
; i
++) {
190 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2, (i
%2) * 4), 0, 4, 1);
192 reg
+= (nr_params
+ 1) / 2;
193 c
->prog_data
.curb_read_length
= reg
- 1;
195 c
->prog_data
.nr_params
= nr_params
* 4;
198 /* Allocate input regs:
201 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
202 if (c
->prog_data
.inputs_read
& (1 << i
)) {
204 c
->regs
[PROGRAM_INPUT
][i
] = brw_vec8_grf(reg
, 0);
208 /* If there are no inputs, we'll still be reading one attribute's worth
209 * because it's required -- see urb_read_length setting.
211 if (c
->nr_inputs
== 0)
214 /* Allocate outputs. The non-position outputs go straight into message regs.
217 c
->first_output
= reg
;
218 c
->first_overflow_output
= 0;
222 else if (intel
->gen
== 5)
227 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
228 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(i
)) {
230 assert(i
< Elements(c
->regs
[PROGRAM_OUTPUT
]));
231 if (i
== VERT_RESULT_HPOS
) {
232 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
235 else if (i
== VERT_RESULT_PSIZ
) {
236 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
238 mrf
++; /* just a placeholder? XXX fix later stages & remove this */
242 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_message_reg(mrf
);
246 /* too many vertex results to fit in MRF, use GRF for overflow */
247 if (!c
->first_overflow_output
)
248 c
->first_overflow_output
= i
;
249 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
256 /* Allocate program temporaries:
258 for (i
= 0; i
< c
->vp
->program
.Base
.NumTemporaries
; i
++) {
259 c
->regs
[PROGRAM_TEMPORARY
][i
] = brw_vec8_grf(reg
, 0);
263 /* Address reg(s). Don't try to use the internal address reg until
266 for (i
= 0; i
< c
->vp
->program
.Base
.NumAddressRegs
; i
++) {
267 c
->regs
[PROGRAM_ADDRESS
][i
] = brw_reg(BRW_GENERAL_REGISTER_FILE
,
271 BRW_VERTICAL_STRIDE_8
,
273 BRW_HORIZONTAL_STRIDE_1
,
279 if (c
->vp
->use_const_buffer
) {
280 for (i
= 0; i
< 3; i
++) {
281 c
->current_const
[i
].index
= -1;
282 c
->current_const
[i
].reg
= brw_vec8_grf(reg
, 0);
287 for (i
= 0; i
< 128; i
++) {
288 if (c
->output_regs
[i
].used_in_src
) {
289 c
->output_regs
[i
].reg
= brw_vec8_grf(reg
, 0);
294 if (c
->needs_stack
) {
295 c
->stack
= brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, reg
, 0);
299 /* Some opcodes need an internal temporary:
302 c
->last_tmp
= reg
; /* for allocation purposes */
304 /* Each input reg holds data from two vertices. The
305 * urb_read_length is the number of registers read from *each*
306 * vertex urb, so is half the amount:
308 c
->prog_data
.urb_read_length
= (c
->nr_inputs
+ 1) / 2;
309 /* Setting this field to 0 leads to undefined behavior according to the
310 * the VS_STATE docs. Our VUEs will always have at least one attribute
311 * sitting in them, even if it's padding.
313 if (c
->prog_data
.urb_read_length
== 0)
314 c
->prog_data
.urb_read_length
= 1;
316 /* The VS VUEs are shared by VF (outputting our inputs) and VS, so size
317 * them to fit the biggest thing they need to.
319 attributes_in_vue
= MAX2(c
->nr_outputs
, c
->nr_inputs
);
322 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 4 + 7) / 8;
323 else if (intel
->gen
== 5)
324 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 6 + 3) / 4;
326 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 2 + 3) / 4;
328 c
->prog_data
.total_grf
= reg
;
330 if (INTEL_DEBUG
& DEBUG_VS
) {
331 printf("%s NumAddrRegs %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumAddressRegs
);
332 printf("%s NumTemps %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumTemporaries
);
333 printf("%s reg = %d\n", __FUNCTION__
, reg
);
339 * If an instruction uses a temp reg both as a src and the dest, we
340 * sometimes need to allocate an intermediate temporary.
342 static void unalias1( struct brw_vs_compile
*c
,
345 void (*func
)( struct brw_vs_compile
*,
349 if (dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) {
350 struct brw_compile
*p
= &c
->func
;
351 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
353 brw_MOV(p
, dst
, tmp
);
363 * Checkes if 2-operand instruction needs an intermediate temporary.
365 static void unalias2( struct brw_vs_compile
*c
,
369 void (*func
)( struct brw_vs_compile
*,
374 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
375 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
)) {
376 struct brw_compile
*p
= &c
->func
;
377 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
378 func(c
, tmp
, arg0
, arg1
);
379 brw_MOV(p
, dst
, tmp
);
383 func(c
, dst
, arg0
, arg1
);
389 * Checkes if 3-operand instruction needs an intermediate temporary.
391 static void unalias3( struct brw_vs_compile
*c
,
396 void (*func
)( struct brw_vs_compile
*,
402 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
403 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
) ||
404 (dst
.file
== arg2
.file
&& dst
.nr
== arg2
.nr
)) {
405 struct brw_compile
*p
= &c
->func
;
406 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
407 func(c
, tmp
, arg0
, arg1
, arg2
);
408 brw_MOV(p
, dst
, tmp
);
412 func(c
, dst
, arg0
, arg1
, arg2
);
416 static void emit_sop( struct brw_vs_compile
*c
,
422 struct brw_compile
*p
= &c
->func
;
424 brw_MOV(p
, dst
, brw_imm_f(0.0f
));
425 brw_CMP(p
, brw_null_reg(), cond
, arg0
, arg1
);
426 brw_MOV(p
, dst
, brw_imm_f(1.0f
));
427 brw_set_predicate_control_flag_value(p
, 0xff);
430 static void emit_seq( struct brw_vs_compile
*c
,
433 struct brw_reg arg1
)
435 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_EQ
);
438 static void emit_sne( struct brw_vs_compile
*c
,
441 struct brw_reg arg1
)
443 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_NEQ
);
445 static void emit_slt( struct brw_vs_compile
*c
,
448 struct brw_reg arg1
)
450 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_L
);
453 static void emit_sle( struct brw_vs_compile
*c
,
456 struct brw_reg arg1
)
458 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_LE
);
461 static void emit_sgt( struct brw_vs_compile
*c
,
464 struct brw_reg arg1
)
466 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_G
);
469 static void emit_sge( struct brw_vs_compile
*c
,
472 struct brw_reg arg1
)
474 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_GE
);
477 static void emit_cmp( struct brw_compile
*p
,
481 struct brw_reg arg2
)
483 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, brw_imm_f(0));
484 brw_SEL(p
, dst
, arg1
, arg2
);
485 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
488 static void emit_max( struct brw_compile
*p
,
491 struct brw_reg arg1
)
493 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_GE
, arg0
, arg1
);
494 brw_SEL(p
, dst
, arg0
, arg1
);
495 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
498 static void emit_min( struct brw_compile
*p
,
501 struct brw_reg arg1
)
503 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
504 brw_SEL(p
, dst
, arg0
, arg1
);
505 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
509 static void emit_math1( struct brw_vs_compile
*c
,
515 /* There are various odd behaviours with SEND on the simulator. In
516 * addition there are documented issues with the fact that the GEN4
517 * processor doesn't do dependency control properly on SEND
518 * results. So, on balance, this kludge to get around failures
519 * with writemasked math results looks like it might be necessary
520 * whether that turns out to be a simulator bug or not:
522 struct brw_compile
*p
= &c
->func
;
523 struct intel_context
*intel
= &p
->brw
->intel
;
524 struct brw_reg tmp
= dst
;
525 GLboolean need_tmp
= (intel
->gen
< 6 &&
526 (dst
.dw1
.bits
.writemask
!= 0xf ||
527 dst
.file
!= BRW_GENERAL_REGISTER_FILE
));
535 BRW_MATH_SATURATE_NONE
,
538 BRW_MATH_DATA_SCALAR
,
542 brw_MOV(p
, dst
, tmp
);
548 static void emit_math2( struct brw_vs_compile
*c
,
555 struct brw_compile
*p
= &c
->func
;
556 struct intel_context
*intel
= &p
->brw
->intel
;
557 struct brw_reg tmp
= dst
;
558 GLboolean need_tmp
= (intel
->gen
< 6 &&
559 (dst
.dw1
.bits
.writemask
!= 0xf ||
560 dst
.file
!= BRW_GENERAL_REGISTER_FILE
));
565 brw_MOV(p
, brw_message_reg(3), arg1
);
570 BRW_MATH_SATURATE_NONE
,
573 BRW_MATH_DATA_SCALAR
,
577 brw_MOV(p
, dst
, tmp
);
583 static void emit_exp_noalias( struct brw_vs_compile
*c
,
585 struct brw_reg arg0
)
587 struct brw_compile
*p
= &c
->func
;
590 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
) {
591 struct brw_reg tmp
= get_tmp(c
);
592 struct brw_reg tmp_d
= retype(tmp
, BRW_REGISTER_TYPE_D
);
594 /* tmp_d = floor(arg0.x) */
595 brw_RNDD(p
, tmp_d
, brw_swizzle1(arg0
, 0));
597 /* result[0] = 2.0 ^ tmp */
599 /* Adjust exponent for floating point:
602 brw_ADD(p
, brw_writemask(tmp_d
, WRITEMASK_X
), tmp_d
, brw_imm_d(127));
604 /* Install exponent and sign.
605 * Excess drops off the edge:
607 brw_SHL(p
, brw_writemask(retype(dst
, BRW_REGISTER_TYPE_D
), WRITEMASK_X
),
608 tmp_d
, brw_imm_d(23));
613 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
) {
614 /* result[1] = arg0.x - floor(arg0.x) */
615 brw_FRC(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
, 0));
618 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
619 /* As with the LOG instruction, we might be better off just
620 * doing a taylor expansion here, seeing as we have to do all
623 * If mathbox partial precision is too low, consider also:
624 * result[3] = result[0] * EXP(result[1])
627 BRW_MATH_FUNCTION_EXP
,
628 brw_writemask(dst
, WRITEMASK_Z
),
629 brw_swizzle1(arg0
, 0),
630 BRW_MATH_PRECISION_FULL
);
633 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
634 /* result[3] = 1.0; */
635 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), brw_imm_f(1));
640 static void emit_log_noalias( struct brw_vs_compile
*c
,
642 struct brw_reg arg0
)
644 struct brw_compile
*p
= &c
->func
;
645 struct brw_reg tmp
= dst
;
646 struct brw_reg tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
647 struct brw_reg arg0_ud
= retype(arg0
, BRW_REGISTER_TYPE_UD
);
648 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
649 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
653 tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
656 /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt
659 * These almost look likey they could be joined up, but not really
662 * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127
663 * result[1].i = (x.i & ((1<<23)-1) + (127<<23)
665 if (dst
.dw1
.bits
.writemask
& WRITEMASK_XZ
) {
667 brw_writemask(tmp_ud
, WRITEMASK_X
),
668 brw_swizzle1(arg0_ud
, 0),
669 brw_imm_ud((1U<<31)-1));
672 brw_writemask(tmp_ud
, WRITEMASK_X
),
677 brw_writemask(tmp
, WRITEMASK_X
),
678 retype(tmp_ud
, BRW_REGISTER_TYPE_D
), /* does it matter? */
682 if (dst
.dw1
.bits
.writemask
& WRITEMASK_YZ
) {
684 brw_writemask(tmp_ud
, WRITEMASK_Y
),
685 brw_swizzle1(arg0_ud
, 0),
686 brw_imm_ud((1<<23)-1));
689 brw_writemask(tmp_ud
, WRITEMASK_Y
),
691 brw_imm_ud(127<<23));
694 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
695 /* result[2] = result[0] + LOG2(result[1]); */
697 /* Why bother? The above is just a hint how to do this with a
698 * taylor series. Maybe we *should* use a taylor series as by
699 * the time all the above has been done it's almost certainly
700 * quicker than calling the mathbox, even with low precision.
703 * - result[0] + mathbox.LOG2(result[1])
704 * - mathbox.LOG2(arg0.x)
705 * - result[0] + inline_taylor_approx(result[1])
708 BRW_MATH_FUNCTION_LOG
,
709 brw_writemask(tmp
, WRITEMASK_Z
),
710 brw_swizzle1(tmp
, 1),
711 BRW_MATH_PRECISION_FULL
);
714 brw_writemask(tmp
, WRITEMASK_Z
),
715 brw_swizzle1(tmp
, 2),
716 brw_swizzle1(tmp
, 0));
719 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
720 /* result[3] = 1.0; */
721 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_W
), brw_imm_f(1));
725 brw_MOV(p
, dst
, tmp
);
731 /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
733 static void emit_dst_noalias( struct brw_vs_compile
*c
,
738 struct brw_compile
*p
= &c
->func
;
740 /* There must be a better way to do this:
742 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
)
743 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_X
), brw_imm_f(1.0));
744 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
)
745 brw_MUL(p
, brw_writemask(dst
, WRITEMASK_Y
), arg0
, arg1
);
746 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
)
747 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Z
), arg0
);
748 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
)
749 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), arg1
);
753 static void emit_xpd( struct brw_compile
*p
,
758 brw_MUL(p
, brw_null_reg(), brw_swizzle(t
, 1,2,0,3), brw_swizzle(u
,2,0,1,3));
759 brw_MAC(p
, dst
, negate(brw_swizzle(t
, 2,0,1,3)), brw_swizzle(u
,1,2,0,3));
763 static void emit_lit_noalias( struct brw_vs_compile
*c
,
765 struct brw_reg arg0
)
767 struct brw_compile
*p
= &c
->func
;
768 struct brw_instruction
*if_insn
;
769 struct brw_reg tmp
= dst
;
770 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
775 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_YZ
), brw_imm_f(0));
776 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_XW
), brw_imm_f(1));
778 /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order
779 * to get all channels active inside the IF. In the clipping code
780 * we run with NoMask, so it's not an option and we can use
781 * BRW_EXECUTE_1 for all comparisions.
783 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,0), brw_imm_f(0));
784 if_insn
= brw_IF(p
, BRW_EXECUTE_8
);
786 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
,0));
788 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,1), brw_imm_f(0));
789 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_Z
), brw_swizzle1(arg0
,1));
790 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
793 BRW_MATH_FUNCTION_POW
,
794 brw_writemask(dst
, WRITEMASK_Z
),
795 brw_swizzle1(tmp
, 2),
796 brw_swizzle1(arg0
, 3),
797 BRW_MATH_PRECISION_PARTIAL
);
800 brw_ENDIF(p
, if_insn
);
805 static void emit_lrp_noalias(struct brw_vs_compile
*c
,
811 struct brw_compile
*p
= &c
->func
;
813 brw_ADD(p
, dst
, negate(arg0
), brw_imm_f(1.0));
814 brw_MUL(p
, brw_null_reg(), dst
, arg2
);
815 brw_MAC(p
, dst
, arg0
, arg1
);
818 /** 3 or 4-component vector normalization */
819 static void emit_nrm( struct brw_vs_compile
*c
,
824 struct brw_compile
*p
= &c
->func
;
825 struct brw_reg tmp
= get_tmp(c
);
827 /* tmp = dot(arg0, arg0) */
829 brw_DP3(p
, tmp
, arg0
, arg0
);
831 brw_DP4(p
, tmp
, arg0
, arg0
);
833 /* tmp = 1 / sqrt(tmp) */
834 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, tmp
, tmp
, BRW_MATH_PRECISION_FULL
);
836 /* dst = arg0 * tmp */
837 brw_MUL(p
, dst
, arg0
, tmp
);
843 static struct brw_reg
844 get_constant(struct brw_vs_compile
*c
,
845 const struct prog_instruction
*inst
,
848 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
849 struct brw_compile
*p
= &c
->func
;
850 struct brw_reg const_reg
= c
->current_const
[argIndex
].reg
;
852 assert(argIndex
< 3);
854 if (c
->current_const
[argIndex
].index
!= src
->Index
) {
855 struct brw_reg addrReg
= c
->regs
[PROGRAM_ADDRESS
][0];
857 /* Keep track of the last constant loaded in this slot, for reuse. */
858 c
->current_const
[argIndex
].index
= src
->Index
;
861 printf(" fetch const[%d] for arg %d into reg %d\n",
862 src
->Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
864 /* need to fetch the constant now */
866 const_reg
, /* writeback dest */
868 0, /* relative indexing? */
869 addrReg
, /* address register */
870 16 * src
->Index
, /* byte offset */
871 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
875 /* replicate lower four floats into upper half (to get XYZWXYZW) */
876 const_reg
= stride(const_reg
, 0, 4, 0);
882 static struct brw_reg
883 get_reladdr_constant(struct brw_vs_compile
*c
,
884 const struct prog_instruction
*inst
,
887 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
888 struct brw_compile
*p
= &c
->func
;
889 struct brw_reg const_reg
= c
->current_const
[argIndex
].reg
;
890 struct brw_reg const2_reg
;
891 struct brw_reg addrReg
= c
->regs
[PROGRAM_ADDRESS
][0];
893 assert(argIndex
< 3);
895 /* Can't reuse a reladdr constant load. */
896 c
->current_const
[argIndex
].index
= -1;
899 printf(" fetch const[a0.x+%d] for arg %d into reg %d\n",
900 src
->Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
903 /* fetch the first vec4 */
905 const_reg
, /* writeback dest */
907 1, /* relative indexing? */
908 addrReg
, /* address register */
909 16 * src
->Index
, /* byte offset */
910 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
913 const2_reg
= get_tmp(c
);
915 /* use upper half of address reg for second read */
916 addrReg
= stride(addrReg
, 0, 4, 0);
920 const2_reg
, /* writeback dest */
922 1, /* relative indexing? */
923 addrReg
, /* address register */
924 16 * src
->Index
, /* byte offset */
925 SURF_INDEX_VERT_CONST_BUFFER
928 /* merge the two Owords into the constant register */
929 /* const_reg[7..4] = const2_reg[7..4] */
931 suboffset(stride(const_reg
, 0, 4, 1), 4),
932 suboffset(stride(const2_reg
, 0, 4, 1), 4));
933 release_tmp(c
, const2_reg
);
940 /* TODO: relative addressing!
942 static struct brw_reg
get_reg( struct brw_vs_compile
*c
,
943 gl_register_file file
,
947 case PROGRAM_TEMPORARY
:
950 assert(c
->regs
[file
][index
].nr
!= 0);
951 return c
->regs
[file
][index
];
952 case PROGRAM_STATE_VAR
:
953 case PROGRAM_CONSTANT
:
954 case PROGRAM_UNIFORM
:
955 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
956 return c
->regs
[PROGRAM_STATE_VAR
][index
];
957 case PROGRAM_ADDRESS
:
959 return c
->regs
[file
][index
];
961 case PROGRAM_UNDEFINED
: /* undef values */
962 return brw_null_reg();
964 case PROGRAM_LOCAL_PARAM
:
965 case PROGRAM_ENV_PARAM
:
966 case PROGRAM_WRITE_ONLY
:
969 return brw_null_reg();
975 * Indirect addressing: get reg[[arg] + offset].
977 static struct brw_reg
deref( struct brw_vs_compile
*c
,
981 struct brw_compile
*p
= &c
->func
;
982 struct brw_reg tmp
= vec4(get_tmp(c
));
983 struct brw_reg addr_reg
= c
->regs
[PROGRAM_ADDRESS
][0];
984 struct brw_reg vp_address
= retype(vec1(addr_reg
), BRW_REGISTER_TYPE_UW
);
985 GLuint byte_offset
= arg
.nr
* 32 + arg
.subnr
+ offset
* 16;
986 struct brw_reg indirect
= brw_vec4_indirect(0,0);
989 brw_push_insn_state(p
);
990 brw_set_access_mode(p
, BRW_ALIGN_1
);
992 /* This is pretty clunky - load the address register twice and
993 * fetch each 4-dword value in turn. There must be a way to do
994 * this in a single pass, but I couldn't get it to work.
996 brw_ADD(p
, brw_address_reg(0), vp_address
, brw_imm_d(byte_offset
));
997 brw_MOV(p
, tmp
, indirect
);
999 brw_ADD(p
, brw_address_reg(0), suboffset(vp_address
, 8), brw_imm_d(byte_offset
));
1000 brw_MOV(p
, suboffset(tmp
, 4), indirect
);
1002 brw_pop_insn_state(p
);
1005 /* NOTE: tmp not released */
1011 * Get brw reg corresponding to the instruction's [argIndex] src reg.
1012 * TODO: relative addressing!
1014 static struct brw_reg
1015 get_src_reg( struct brw_vs_compile
*c
,
1016 const struct prog_instruction
*inst
,
1019 const GLuint file
= inst
->SrcReg
[argIndex
].File
;
1020 const GLint index
= inst
->SrcReg
[argIndex
].Index
;
1021 const GLboolean relAddr
= inst
->SrcReg
[argIndex
].RelAddr
;
1023 if (brw_vs_arg_can_be_immediate(inst
->Opcode
, argIndex
)) {
1024 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
1026 if (src
->Swizzle
== MAKE_SWIZZLE4(SWIZZLE_ZERO
,
1030 return brw_imm_f(0.0f
);
1031 } else if (src
->Swizzle
== MAKE_SWIZZLE4(SWIZZLE_ONE
,
1036 return brw_imm_f(-1.0F
);
1038 return brw_imm_f(1.0F
);
1039 } else if (src
->File
== PROGRAM_CONSTANT
) {
1040 const struct gl_program_parameter_list
*params
;
1044 switch (src
->Swizzle
) {
1059 if (component
>= 0) {
1060 params
= c
->vp
->program
.Base
.Parameters
;
1061 f
= params
->ParameterValues
[src
->Index
][component
];
1067 return brw_imm_f(f
);
1073 case PROGRAM_TEMPORARY
:
1075 case PROGRAM_OUTPUT
:
1077 return deref(c
, c
->regs
[file
][0], index
);
1080 assert(c
->regs
[file
][index
].nr
!= 0);
1081 return c
->regs
[file
][index
];
1084 case PROGRAM_STATE_VAR
:
1085 case PROGRAM_CONSTANT
:
1086 case PROGRAM_UNIFORM
:
1087 case PROGRAM_ENV_PARAM
:
1088 case PROGRAM_LOCAL_PARAM
:
1089 if (c
->vp
->use_const_buffer
) {
1090 if (!relAddr
&& c
->constant_map
[index
] != -1) {
1091 assert(c
->regs
[PROGRAM_STATE_VAR
][c
->constant_map
[index
]].nr
!= 0);
1092 return c
->regs
[PROGRAM_STATE_VAR
][c
->constant_map
[index
]];
1094 return get_reladdr_constant(c
, inst
, argIndex
);
1096 return get_constant(c
, inst
, argIndex
);
1099 return deref(c
, c
->regs
[PROGRAM_STATE_VAR
][0], index
);
1102 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
1103 return c
->regs
[PROGRAM_STATE_VAR
][index
];
1105 case PROGRAM_ADDRESS
:
1107 return c
->regs
[file
][index
];
1109 case PROGRAM_UNDEFINED
:
1110 /* this is a normal case since we loop over all three src args */
1111 return brw_null_reg();
1113 case PROGRAM_WRITE_ONLY
:
1116 return brw_null_reg();
1121 static void emit_arl( struct brw_vs_compile
*c
,
1123 struct brw_reg arg0
)
1125 struct brw_compile
*p
= &c
->func
;
1126 struct brw_reg tmp
= dst
;
1127 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
1132 brw_RNDD(p
, tmp
, arg0
); /* tmp = round(arg0) */
1133 brw_MUL(p
, dst
, tmp
, brw_imm_d(16)); /* dst = tmp * 16 */
1136 release_tmp(c
, tmp
);
1141 * Return the brw reg for the given instruction's src argument.
1142 * Will return mangled results for SWZ op. The emit_swz() function
1143 * ignores this result and recalculates taking extended swizzles into
1146 static struct brw_reg
get_arg( struct brw_vs_compile
*c
,
1147 const struct prog_instruction
*inst
,
1150 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
1153 if (src
->File
== PROGRAM_UNDEFINED
)
1154 return brw_null_reg();
1156 reg
= get_src_reg(c
, inst
, argIndex
);
1158 /* Convert 3-bit swizzle to 2-bit.
1160 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(GET_SWZ(src
->Swizzle
, 0),
1161 GET_SWZ(src
->Swizzle
, 1),
1162 GET_SWZ(src
->Swizzle
, 2),
1163 GET_SWZ(src
->Swizzle
, 3));
1165 /* Note this is ok for non-swizzle instructions:
1167 reg
.negate
= src
->Negate
? 1 : 0;
1174 * Get brw register for the given program dest register.
1176 static struct brw_reg
get_dst( struct brw_vs_compile
*c
,
1177 struct prog_dst_register dst
)
1182 case PROGRAM_TEMPORARY
:
1183 case PROGRAM_OUTPUT
:
1184 assert(c
->regs
[dst
.File
][dst
.Index
].nr
!= 0);
1185 reg
= c
->regs
[dst
.File
][dst
.Index
];
1187 case PROGRAM_ADDRESS
:
1188 assert(dst
.Index
== 0);
1189 reg
= c
->regs
[dst
.File
][dst
.Index
];
1191 case PROGRAM_UNDEFINED
:
1192 /* we may hit this for OPCODE_END, OPCODE_KIL, etc */
1193 reg
= brw_null_reg();
1197 reg
= brw_null_reg();
1200 reg
.dw1
.bits
.writemask
= dst
.WriteMask
;
1206 static void emit_swz( struct brw_vs_compile
*c
,
1208 const struct prog_instruction
*inst
)
1210 const GLuint argIndex
= 0;
1211 const struct prog_src_register src
= inst
->SrcReg
[argIndex
];
1212 struct brw_compile
*p
= &c
->func
;
1213 GLuint zeros_mask
= 0;
1214 GLuint ones_mask
= 0;
1215 GLuint src_mask
= 0;
1217 GLboolean need_tmp
= (src
.Negate
&&
1218 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
1219 struct brw_reg tmp
= dst
;
1225 for (i
= 0; i
< 4; i
++) {
1226 if (dst
.dw1
.bits
.writemask
& (1<<i
)) {
1227 GLubyte s
= GET_SWZ(src
.Swizzle
, i
);
1246 /* Do src first, in case dst aliases src:
1249 struct brw_reg arg0
;
1251 arg0
= get_src_reg(c
, inst
, argIndex
);
1253 arg0
= brw_swizzle(arg0
,
1254 src_swz
[0], src_swz
[1],
1255 src_swz
[2], src_swz
[3]);
1257 brw_MOV(p
, brw_writemask(tmp
, src_mask
), arg0
);
1261 brw_MOV(p
, brw_writemask(tmp
, zeros_mask
), brw_imm_f(0));
1264 brw_MOV(p
, brw_writemask(tmp
, ones_mask
), brw_imm_f(1));
1267 brw_MOV(p
, brw_writemask(tmp
, src
.Negate
), negate(tmp
));
1270 brw_MOV(p
, dst
, tmp
);
1271 release_tmp(c
, tmp
);
1277 * Post-vertex-program processing. Send the results to the URB.
1279 static void emit_vertex_write( struct brw_vs_compile
*c
)
1281 struct brw_compile
*p
= &c
->func
;
1282 struct brw_context
*brw
= p
->brw
;
1283 struct intel_context
*intel
= &brw
->intel
;
1284 struct brw_reg m0
= brw_message_reg(0);
1285 struct brw_reg pos
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_HPOS
];
1288 GLuint len_vertex_header
= 2;
1290 if (c
->key
.copy_edgeflag
) {
1292 get_reg(c
, PROGRAM_OUTPUT
, VERT_RESULT_EDGE
),
1293 get_reg(c
, PROGRAM_INPUT
, VERT_ATTRIB_EDGEFLAG
));
1296 if (intel
->gen
< 6) {
1297 /* Build ndc coords */
1299 /* ndc = 1.0 / pos.w */
1300 emit_math1(c
, BRW_MATH_FUNCTION_INV
, ndc
, brw_swizzle1(pos
, 3), BRW_MATH_PRECISION_FULL
);
1301 /* ndc.xyz = pos * ndc */
1302 brw_MUL(p
, brw_writemask(ndc
, WRITEMASK_XYZ
), pos
, ndc
);
1305 /* Update the header for point size, user clipping flags, and -ve rhw
1308 if ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
1309 c
->key
.nr_userclip
|| brw
->has_negative_rhw_bug
)
1311 struct brw_reg header1
= retype(get_tmp(c
), BRW_REGISTER_TYPE_UD
);
1314 brw_MOV(p
, header1
, brw_imm_ud(0));
1316 brw_set_access_mode(p
, BRW_ALIGN_16
);
1318 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1319 struct brw_reg psiz
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_PSIZ
];
1320 brw_MUL(p
, brw_writemask(header1
, WRITEMASK_W
), brw_swizzle1(psiz
, 0), brw_imm_f(1<<11));
1321 brw_AND(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(0x7ff<<8));
1324 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1325 brw_set_conditionalmod(p
, BRW_CONDITIONAL_L
);
1326 brw_DP4(p
, brw_null_reg(), pos
, c
->userplane
[i
]);
1327 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<i
));
1328 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1331 /* i965 clipping workaround:
1332 * 1) Test for -ve rhw
1334 * set ndc = (0,0,0,0)
1337 * Later, clipping will detect ucp[6] and ensure the primitive is
1338 * clipped against all fixed planes.
1340 if (brw
->has_negative_rhw_bug
) {
1342 vec8(brw_null_reg()),
1344 brw_swizzle1(ndc
, 3),
1347 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1348 brw_MOV(p
, ndc
, brw_imm_f(0));
1349 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1352 brw_set_access_mode(p
, BRW_ALIGN_1
); /* why? */
1353 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), header1
);
1354 brw_set_access_mode(p
, BRW_ALIGN_16
);
1356 release_tmp(c
, header1
);
1359 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
1362 /* Emit the (interleaved) headers for the two vertices - an 8-reg
1363 * of zeros followed by two sets of NDC coordinates:
1365 brw_set_access_mode(p
, BRW_ALIGN_1
);
1367 if (intel
->gen
>= 6) {
1368 /* There are 16 DWs (D0-D15) in VUE header on Sandybridge:
1369 * dword 0-3 (m1) of the header is indices, point width, clip flags.
1370 * dword 4-7 (m2) is the 4D space position
1371 * dword 8-15 (m3,m4) of the vertex header is the user clip distance.
1372 * m5 is the first vertex data we fill, which is the vertex position.
1374 brw_MOV(p
, offset(m0
, 2), pos
);
1375 brw_MOV(p
, offset(m0
, 5), pos
);
1376 len_vertex_header
= 4;
1377 } else if (intel
->gen
== 5) {
1378 /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
1379 * dword 0-3 (m1) of the header is indices, point width, clip flags.
1380 * dword 4-7 (m2) is the ndc position (set above)
1381 * dword 8-11 (m3) of the vertex header is the 4D space position
1382 * dword 12-19 (m4,m5) of the vertex header is the user clip distance.
1383 * m6 is a pad so that the vertex element data is aligned
1384 * m7 is the first vertex data we fill, which is the vertex position.
1386 brw_MOV(p
, offset(m0
, 2), ndc
);
1387 brw_MOV(p
, offset(m0
, 3), pos
);
1388 brw_MOV(p
, offset(m0
, 7), pos
);
1389 len_vertex_header
= 6;
1391 /* There are 8 dwords in VUE header pre-Ironlake:
1392 * dword 0-3 (m1) is indices, point width, clip flags.
1393 * dword 4-7 (m2) is ndc position (set above)
1395 * dword 8-11 (m3) is the first vertex data, which we always have be the
1398 brw_MOV(p
, offset(m0
, 2), ndc
);
1399 brw_MOV(p
, offset(m0
, 3), pos
);
1400 len_vertex_header
= 2;
1403 eot
= (c
->first_overflow_output
== 0);
1406 brw_null_reg(), /* dest */
1407 0, /* starting mrf reg nr */
1411 MIN2(c
->nr_outputs
+ 1 + len_vertex_header
, (BRW_MAX_MRF
-1)), /* msg len */
1412 0, /* response len */
1414 eot
, /* writes complete */
1415 0, /* urb destination offset */
1416 BRW_URB_SWIZZLE_INTERLEAVE
);
1418 if (c
->first_overflow_output
> 0) {
1419 /* Not all of the vertex outputs/results fit into the MRF.
1420 * Move the overflowed attributes from the GRF to the MRF and
1421 * issue another brw_urb_WRITE().
1423 /* XXX I'm not 100% sure about which MRF regs to use here. Starting
1427 for (i
= c
->first_overflow_output
; i
< VERT_RESULT_MAX
; i
++) {
1428 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(i
)) {
1429 /* move from GRF to MRF */
1430 brw_MOV(p
, brw_message_reg(4+mrf
), c
->regs
[PROGRAM_OUTPUT
][i
]);
1436 brw_null_reg(), /* dest */
1437 4, /* starting mrf reg nr */
1441 mrf
+1, /* msg len */
1442 0, /* response len */
1444 1, /* writes complete */
1445 BRW_MAX_MRF
-1, /* urb destination offset */
1446 BRW_URB_SWIZZLE_INTERLEAVE
);
1451 accumulator_contains(struct brw_vs_compile
*c
, struct brw_reg val
)
1453 struct brw_compile
*p
= &c
->func
;
1454 struct brw_instruction
*prev_insn
= &p
->store
[p
->nr_insn
- 1];
1456 if (p
->nr_insn
== 0)
1459 if (val
.address_mode
!= BRW_ADDRESS_DIRECT
)
1462 switch (prev_insn
->header
.opcode
) {
1463 case BRW_OPCODE_MOV
:
1464 case BRW_OPCODE_MAC
:
1465 case BRW_OPCODE_MUL
:
1466 if (prev_insn
->header
.access_mode
== BRW_ALIGN_16
&&
1467 prev_insn
->header
.execution_size
== val
.width
&&
1468 prev_insn
->bits1
.da1
.dest_reg_file
== val
.file
&&
1469 prev_insn
->bits1
.da1
.dest_reg_type
== val
.type
&&
1470 prev_insn
->bits1
.da1
.dest_address_mode
== val
.address_mode
&&
1471 prev_insn
->bits1
.da1
.dest_reg_nr
== val
.nr
&&
1472 prev_insn
->bits1
.da16
.dest_subreg_nr
== val
.subnr
/ 16 &&
1473 prev_insn
->bits1
.da16
.dest_writemask
== 0xf)
1483 get_predicate(const struct prog_instruction
*inst
)
1485 if (inst
->DstReg
.CondMask
== COND_TR
)
1486 return BRW_PREDICATE_NONE
;
1488 /* All of GLSL only produces predicates for COND_NE and one channel per
1489 * vector. Fail badly if someone starts doing something else, as it might
1490 * mean infinite looping or something.
1492 * We'd like to support all the condition codes, but our hardware doesn't
1493 * quite match the Mesa IR, which is modeled after the NV extensions. For
1494 * those, the instruction may update the condition codes or not, then any
1495 * later instruction may use one of those condition codes. For gen4, the
1496 * instruction may update the flags register based on one of the condition
1497 * codes output by the instruction, and then further instructions may
1498 * predicate on that. We can probably support this, but it won't
1499 * necessarily be easy.
1501 assert(inst
->DstReg
.CondMask
== COND_NE
);
1503 switch (inst
->DstReg
.CondSwizzle
) {
1505 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1507 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1509 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1511 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1513 _mesa_problem(NULL
, "Unexpected predicate: 0x%08x\n",
1514 inst
->DstReg
.CondMask
);
1515 return BRW_PREDICATE_NORMAL
;
1519 /* Emit the vertex program instructions here.
1521 void brw_vs_emit(struct brw_vs_compile
*c
)
1523 #define MAX_IF_DEPTH 32
1524 #define MAX_LOOP_DEPTH 32
1525 struct brw_compile
*p
= &c
->func
;
1526 struct brw_context
*brw
= p
->brw
;
1527 struct intel_context
*intel
= &brw
->intel
;
1528 const GLuint nr_insns
= c
->vp
->program
.Base
.NumInstructions
;
1529 GLuint insn
, if_depth
= 0, loop_depth
= 0;
1530 struct brw_instruction
*if_inst
[MAX_IF_DEPTH
], *loop_inst
[MAX_LOOP_DEPTH
] = { 0 };
1531 const struct brw_indirect stack_index
= brw_indirect(0, 0);
1535 if (INTEL_DEBUG
& DEBUG_VS
) {
1536 printf("vs-mesa:\n");
1537 _mesa_print_program(&c
->vp
->program
.Base
);
1541 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1542 brw_set_access_mode(p
, BRW_ALIGN_16
);
1544 for (insn
= 0; insn
< nr_insns
; insn
++) {
1546 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1548 /* Message registers can't be read, so copy the output into GRF
1549 * register if they are used in source registers
1551 for (i
= 0; i
< 3; i
++) {
1552 struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1553 GLuint index
= src
->Index
;
1554 GLuint file
= src
->File
;
1555 if (file
== PROGRAM_OUTPUT
&& index
!= VERT_RESULT_HPOS
)
1556 c
->output_regs
[index
].used_in_src
= GL_TRUE
;
1559 switch (inst
->Opcode
) {
1562 c
->needs_stack
= GL_TRUE
;
1569 /* Static register allocation
1571 brw_vs_alloc_regs(c
);
1574 brw_MOV(p
, get_addr_reg(stack_index
), brw_address(c
->stack
));
1576 for (insn
= 0; insn
< nr_insns
; insn
++) {
1578 const struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1579 struct brw_reg args
[3], dst
;
1583 printf("%d: ", insn
);
1584 _mesa_print_instruction(inst
);
1587 /* Get argument regs. SWZ is special and does this itself.
1589 if (inst
->Opcode
!= OPCODE_SWZ
)
1590 for (i
= 0; i
< 3; i
++) {
1591 const struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1594 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1595 args
[i
] = c
->output_regs
[index
].reg
;
1597 args
[i
] = get_arg(c
, inst
, i
);
1600 /* Get dest regs. Note that it is possible for a reg to be both
1601 * dst and arg, given the static allocation of registers. So
1602 * care needs to be taken emitting multi-operation instructions.
1604 index
= inst
->DstReg
.Index
;
1605 file
= inst
->DstReg
.File
;
1606 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1607 dst
= c
->output_regs
[index
].reg
;
1609 dst
= get_dst(c
, inst
->DstReg
);
1611 if (inst
->SaturateMode
!= SATURATE_OFF
) {
1612 _mesa_problem(NULL
, "Unsupported saturate %d in vertex shader",
1613 inst
->SaturateMode
);
1616 switch (inst
->Opcode
) {
1618 brw_MOV(p
, dst
, brw_abs(args
[0]));
1621 brw_ADD(p
, dst
, args
[0], args
[1]);
1624 emit_math1(c
, BRW_MATH_FUNCTION_COS
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1627 brw_DP3(p
, dst
, args
[0], args
[1]);
1630 brw_DP4(p
, dst
, args
[0], args
[1]);
1633 brw_DPH(p
, dst
, args
[0], args
[1]);
1636 emit_nrm(c
, dst
, args
[0], 3);
1639 emit_nrm(c
, dst
, args
[0], 4);
1642 unalias2(c
, dst
, args
[0], args
[1], emit_dst_noalias
);
1645 unalias1(c
, dst
, args
[0], emit_exp_noalias
);
1648 emit_math1(c
, BRW_MATH_FUNCTION_EXP
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1651 emit_arl(c
, dst
, args
[0]);
1654 brw_RNDD(p
, dst
, args
[0]);
1657 brw_FRC(p
, dst
, args
[0]);
1660 unalias1(c
, dst
, args
[0], emit_log_noalias
);
1663 emit_math1(c
, BRW_MATH_FUNCTION_LOG
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1666 unalias1(c
, dst
, args
[0], emit_lit_noalias
);
1669 unalias3(c
, dst
, args
[0], args
[1], args
[2], emit_lrp_noalias
);
1672 if (!accumulator_contains(c
, args
[2]))
1673 brw_MOV(p
, brw_acc_reg(), args
[2]);
1674 brw_MAC(p
, dst
, args
[0], args
[1]);
1677 emit_cmp(p
, dst
, args
[0], args
[1], args
[2]);
1680 emit_max(p
, dst
, args
[0], args
[1]);
1683 emit_min(p
, dst
, args
[0], args
[1]);
1686 brw_MOV(p
, dst
, args
[0]);
1689 brw_MUL(p
, dst
, args
[0], args
[1]);
1692 emit_math2(c
, BRW_MATH_FUNCTION_POW
, dst
, args
[0], args
[1], BRW_MATH_PRECISION_FULL
);
1695 emit_math1(c
, BRW_MATH_FUNCTION_INV
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1698 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1702 unalias2(c
, dst
, args
[0], args
[1], emit_seq
);
1705 emit_math1(c
, BRW_MATH_FUNCTION_SIN
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1708 unalias2(c
, dst
, args
[0], args
[1], emit_sne
);
1711 unalias2(c
, dst
, args
[0], args
[1], emit_sge
);
1714 unalias2(c
, dst
, args
[0], args
[1], emit_sgt
);
1717 unalias2(c
, dst
, args
[0], args
[1], emit_slt
);
1720 unalias2(c
, dst
, args
[0], args
[1], emit_sle
);
1723 brw_ADD(p
, dst
, args
[0], negate(args
[1]));
1726 /* The args[0] value can't be used here as it won't have
1727 * correctly encoded the full swizzle:
1729 emit_swz(c
, dst
, inst
);
1732 /* round toward zero */
1733 brw_RNDZ(p
, dst
, args
[0]);
1736 emit_xpd(p
, dst
, args
[0], args
[1]);
1739 assert(if_depth
< MAX_IF_DEPTH
);
1740 if_inst
[if_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1741 /* Note that brw_IF smashes the predicate_control field. */
1742 if_inst
[if_depth
]->header
.predicate_control
= get_predicate(inst
);
1746 assert(if_depth
> 0);
1747 if_inst
[if_depth
-1] = brw_ELSE(p
, if_inst
[if_depth
-1]);
1750 assert(if_depth
> 0);
1751 brw_ENDIF(p
, if_inst
[--if_depth
]);
1753 case OPCODE_BGNLOOP
:
1754 loop_inst
[loop_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
1757 brw_set_predicate_control(p
, get_predicate(inst
));
1759 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1762 brw_set_predicate_control(p
, get_predicate(inst
));
1764 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1766 case OPCODE_ENDLOOP
:
1768 struct brw_instruction
*inst0
, *inst1
;
1773 if (intel
->gen
== 5)
1776 inst0
= inst1
= brw_WHILE(p
, loop_inst
[loop_depth
]);
1777 /* patch all the BREAK/CONT instructions from last BEGINLOOP */
1778 while (inst0
> loop_inst
[loop_depth
]) {
1780 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
1781 inst0
->bits3
.if_else
.jump_count
== 0) {
1782 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
1783 inst0
->bits3
.if_else
.pop_count
= 0;
1785 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
1786 inst0
->bits3
.if_else
.jump_count
== 0) {
1787 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
1788 inst0
->bits3
.if_else
.pop_count
= 0;
1794 brw_set_predicate_control(p
, get_predicate(inst
));
1795 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1796 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1799 brw_set_access_mode(p
, BRW_ALIGN_1
);
1800 brw_ADD(p
, deref_1d(stack_index
, 0), brw_ip_reg(), brw_imm_d(3*16));
1801 brw_set_access_mode(p
, BRW_ALIGN_16
);
1802 brw_ADD(p
, get_addr_reg(stack_index
),
1803 get_addr_reg(stack_index
), brw_imm_d(4));
1804 brw_save_call(p
, inst
->Comment
, p
->nr_insn
);
1805 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1808 brw_ADD(p
, get_addr_reg(stack_index
),
1809 get_addr_reg(stack_index
), brw_imm_d(-4));
1810 brw_set_access_mode(p
, BRW_ALIGN_1
);
1811 brw_MOV(p
, brw_ip_reg(), deref_1d(stack_index
, 0));
1812 brw_set_access_mode(p
, BRW_ALIGN_16
);
1815 emit_vertex_write(c
);
1821 brw_save_label(p
, inst
->Comment
, p
->nr_insn
);
1827 _mesa_problem(NULL
, "Unsupported opcode %i (%s) in vertex shader",
1828 inst
->Opcode
, inst
->Opcode
< MAX_OPCODE
?
1829 _mesa_opcode_string(inst
->Opcode
) :
1833 /* Set the predication update on the last instruction of the native
1834 * instruction sequence.
1836 * This would be problematic if it was set on a math instruction,
1837 * but that shouldn't be the case with the current GLSL compiler.
1839 if (inst
->CondUpdate
) {
1840 struct brw_instruction
*hw_insn
= &p
->store
[p
->nr_insn
- 1];
1842 assert(hw_insn
->header
.destreg__conditionalmod
== 0);
1843 hw_insn
->header
.destreg__conditionalmod
= BRW_CONDITIONAL_NZ
;
1846 if ((inst
->DstReg
.File
== PROGRAM_OUTPUT
)
1847 && (inst
->DstReg
.Index
!= VERT_RESULT_HPOS
)
1848 && c
->output_regs
[inst
->DstReg
.Index
].used_in_src
) {
1849 brw_MOV(p
, get_dst(c
, inst
->DstReg
), dst
);
1852 /* Result color clamping.
1854 * When destination register is an output register and
1855 * it's primary/secondary front/back color, we have to clamp
1856 * the result to [0,1]. This is done by enabling the
1857 * saturation bit for the last instruction.
1859 * We don't use brw_set_saturate() as it modifies
1860 * p->current->header.saturate, which affects all the subsequent
1861 * instructions. Instead, we directly modify the header
1862 * of the last (already stored) instruction.
1864 if (inst
->DstReg
.File
== PROGRAM_OUTPUT
) {
1865 if ((inst
->DstReg
.Index
== VERT_RESULT_COL0
)
1866 || (inst
->DstReg
.Index
== VERT_RESULT_COL1
)
1867 || (inst
->DstReg
.Index
== VERT_RESULT_BFC0
)
1868 || (inst
->DstReg
.Index
== VERT_RESULT_BFC1
)) {
1869 p
->store
[p
->nr_insn
-1].header
.saturate
= 1;
1876 brw_resolve_cals(p
);
1880 if (INTEL_DEBUG
& DEBUG_VS
) {
1883 printf("vs-native:\n");
1884 for (i
= 0; i
< p
->nr_insn
; i
++)
1885 brw_disasm(stderr
, &p
->store
[i
], intel
->gen
);