2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/macros.h"
34 #include "shader/program.h"
35 #include "shader/prog_parameter.h"
36 #include "shader/prog_print.h"
37 #include "brw_context.h"
42 /* Do things as simply as possible. Allocate and populate all regs
45 static void brw_vs_alloc_regs( struct brw_vs_compile
*c
)
47 GLuint i
, reg
= 0, mrf
;
50 /* r0 -- reserved as usual
52 c
->r0
= brw_vec8_grf(reg
, 0); reg
++;
54 /* User clip planes from curbe:
56 if (c
->key
.nr_userclip
) {
57 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
58 c
->userplane
[i
] = stride( brw_vec4_grf(reg
+3+i
/2, (i
%2) * 4), 0, 4, 1);
61 /* Deal with curbe alignment:
63 reg
+= ((6+c
->key
.nr_userclip
+3)/4)*2;
66 /* Vertex program parameters from curbe:
68 nr_params
= c
->vp
->program
.Base
.Parameters
->NumParameters
;
69 for (i
= 0; i
< nr_params
; i
++) {
70 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2, (i
%2) * 4), 0, 4, 1);
72 reg
+= (nr_params
+1)/2;
74 c
->prog_data
.curb_read_length
= reg
- 1;
76 /* Allocate input regs:
79 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
80 if (c
->prog_data
.inputs_read
& (1<<i
)) {
82 c
->regs
[PROGRAM_INPUT
][i
] = brw_vec8_grf(reg
, 0);
87 /* Allocate outputs: TODO: could organize the non-position outputs
88 * to go straight into message regs.
91 c
->first_output
= reg
;
93 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
94 if (c
->prog_data
.outputs_written
& (1<<i
)) {
96 if (i
== VERT_RESULT_HPOS
) {
97 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
100 else if (i
== VERT_RESULT_PSIZ
) {
101 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
103 mrf
++; /* just a placeholder? XXX fix later stages & remove this */
106 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_message_reg(mrf
);
112 /* Allocate program temporaries:
114 for (i
= 0; i
< c
->vp
->program
.Base
.NumTemporaries
; i
++) {
115 c
->regs
[PROGRAM_TEMPORARY
][i
] = brw_vec8_grf(reg
, 0);
119 /* Address reg(s). Don't try to use the internal address reg until
122 for (i
= 0; i
< c
->vp
->program
.Base
.NumAddressRegs
; i
++) {
123 c
->regs
[PROGRAM_ADDRESS
][i
] = brw_reg(BRW_GENERAL_REGISTER_FILE
,
127 BRW_VERTICAL_STRIDE_8
,
129 BRW_HORIZONTAL_STRIDE_1
,
135 for (i
= 0; i
< 128; i
++) {
136 if (c
->output_regs
[i
].used_in_src
) {
137 c
->output_regs
[i
].reg
= brw_vec8_grf(reg
, 0);
142 c
->stack
= brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, reg
, 0);
146 /* Some opcodes need an internal temporary:
149 c
->last_tmp
= reg
; /* for allocation purposes */
151 /* Each input reg holds data from two vertices. The
152 * urb_read_length is the number of registers read from *each*
153 * vertex urb, so is half the amount:
155 c
->prog_data
.urb_read_length
= (c
->nr_inputs
+1)/2;
157 c
->prog_data
.urb_entry_size
= (c
->nr_outputs
+2+3)/4;
158 c
->prog_data
.total_grf
= reg
;
162 static struct brw_reg
get_tmp( struct brw_vs_compile
*c
)
164 struct brw_reg tmp
= brw_vec8_grf(c
->last_tmp
, 0);
166 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
167 c
->prog_data
.total_grf
= c
->last_tmp
;
172 static void release_tmp( struct brw_vs_compile
*c
, struct brw_reg tmp
)
174 if (tmp
.nr
== c
->last_tmp
-1)
178 static void release_tmps( struct brw_vs_compile
*c
)
180 c
->last_tmp
= c
->first_tmp
;
184 static void unalias1( struct brw_vs_compile
*c
,
187 void (*func
)( struct brw_vs_compile
*,
191 if (dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) {
192 struct brw_compile
*p
= &c
->func
;
193 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
195 brw_MOV(p
, dst
, tmp
);
203 static void unalias2( struct brw_vs_compile
*c
,
207 void (*func
)( struct brw_vs_compile
*,
212 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
213 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
)) {
214 struct brw_compile
*p
= &c
->func
;
215 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
216 func(c
, tmp
, arg0
, arg1
);
217 brw_MOV(p
, dst
, tmp
);
221 func(c
, dst
, arg0
, arg1
);
225 static void unalias3( struct brw_vs_compile
*c
,
230 void (*func
)( struct brw_vs_compile
*,
236 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
237 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
) ||
238 (dst
.file
== arg2
.file
&& dst
.nr
== arg2
.nr
)) {
239 struct brw_compile
*p
= &c
->func
;
240 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
241 func(c
, tmp
, arg0
, arg1
, arg2
);
242 brw_MOV(p
, dst
, tmp
);
246 func(c
, dst
, arg0
, arg1
, arg2
);
250 static void emit_sop( struct brw_compile
*p
,
256 brw_MOV(p
, dst
, brw_imm_f(0.0f
));
257 brw_CMP(p
, brw_null_reg(), cond
, arg0
, arg1
);
258 brw_MOV(p
, dst
, brw_imm_f(1.0f
));
259 brw_set_predicate_control_flag_value(p
, 0xff);
262 static void emit_seq( struct brw_compile
*p
,
265 struct brw_reg arg1
)
267 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_EQ
);
270 static void emit_sne( struct brw_compile
*p
,
273 struct brw_reg arg1
)
275 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_NEQ
);
277 static void emit_slt( struct brw_compile
*p
,
280 struct brw_reg arg1
)
282 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_L
);
285 static void emit_sle( struct brw_compile
*p
,
288 struct brw_reg arg1
)
290 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_LE
);
293 static void emit_sgt( struct brw_compile
*p
,
296 struct brw_reg arg1
)
298 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_G
);
301 static void emit_sge( struct brw_compile
*p
,
304 struct brw_reg arg1
)
306 emit_sop(p
, dst
, arg0
, arg1
, BRW_CONDITIONAL_GE
);
309 static void emit_max( struct brw_compile
*p
,
312 struct brw_reg arg1
)
314 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
315 brw_SEL(p
, dst
, arg1
, arg0
);
316 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
319 static void emit_min( struct brw_compile
*p
,
322 struct brw_reg arg1
)
324 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
325 brw_SEL(p
, dst
, arg0
, arg1
);
326 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
330 static void emit_math1( struct brw_vs_compile
*c
,
336 /* There are various odd behaviours with SEND on the simulator. In
337 * addition there are documented issues with the fact that the GEN4
338 * processor doesn't do dependency control properly on SEND
339 * results. So, on balance, this kludge to get around failures
340 * with writemasked math results looks like it might be necessary
341 * whether that turns out to be a simulator bug or not:
343 struct brw_compile
*p
= &c
->func
;
344 struct brw_reg tmp
= dst
;
345 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
346 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
354 BRW_MATH_SATURATE_NONE
,
357 BRW_MATH_DATA_SCALAR
,
361 brw_MOV(p
, dst
, tmp
);
367 static void emit_math2( struct brw_vs_compile
*c
,
374 struct brw_compile
*p
= &c
->func
;
375 struct brw_reg tmp
= dst
;
376 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
377 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
382 brw_MOV(p
, brw_message_reg(3), arg1
);
387 BRW_MATH_SATURATE_NONE
,
390 BRW_MATH_DATA_SCALAR
,
394 brw_MOV(p
, dst
, tmp
);
400 static void emit_exp_noalias( struct brw_vs_compile
*c
,
402 struct brw_reg arg0
)
404 struct brw_compile
*p
= &c
->func
;
407 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
) {
408 struct brw_reg tmp
= get_tmp(c
);
409 struct brw_reg tmp_d
= retype(tmp
, BRW_REGISTER_TYPE_D
);
411 /* tmp_d = floor(arg0.x) */
412 brw_RNDD(p
, tmp_d
, brw_swizzle1(arg0
, 0));
414 /* result[0] = 2.0 ^ tmp */
416 /* Adjust exponent for floating point:
419 brw_ADD(p
, brw_writemask(tmp_d
, WRITEMASK_X
), tmp_d
, brw_imm_d(127));
421 /* Install exponent and sign.
422 * Excess drops off the edge:
424 brw_SHL(p
, brw_writemask(retype(dst
, BRW_REGISTER_TYPE_D
), WRITEMASK_X
),
425 tmp_d
, brw_imm_d(23));
430 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
) {
431 /* result[1] = arg0.x - floor(arg0.x) */
432 brw_FRC(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
, 0));
435 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
436 /* As with the LOG instruction, we might be better off just
437 * doing a taylor expansion here, seeing as we have to do all
440 * If mathbox partial precision is too low, consider also:
441 * result[3] = result[0] * EXP(result[1])
444 BRW_MATH_FUNCTION_EXP
,
445 brw_writemask(dst
, WRITEMASK_Z
),
446 brw_swizzle1(arg0
, 0),
447 BRW_MATH_PRECISION_FULL
);
450 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
451 /* result[3] = 1.0; */
452 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), brw_imm_f(1));
457 static void emit_log_noalias( struct brw_vs_compile
*c
,
459 struct brw_reg arg0
)
461 struct brw_compile
*p
= &c
->func
;
462 struct brw_reg tmp
= dst
;
463 struct brw_reg tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
464 struct brw_reg arg0_ud
= retype(arg0
, BRW_REGISTER_TYPE_UD
);
465 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
466 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
470 tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
473 /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt
476 * These almost look likey they could be joined up, but not really
479 * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127
480 * result[1].i = (x.i & ((1<<23)-1) + (127<<23)
482 if (dst
.dw1
.bits
.writemask
& WRITEMASK_XZ
) {
484 brw_writemask(tmp_ud
, WRITEMASK_X
),
485 brw_swizzle1(arg0_ud
, 0),
486 brw_imm_ud((1U<<31)-1));
489 brw_writemask(tmp_ud
, WRITEMASK_X
),
494 brw_writemask(tmp
, WRITEMASK_X
),
495 retype(tmp_ud
, BRW_REGISTER_TYPE_D
), /* does it matter? */
499 if (dst
.dw1
.bits
.writemask
& WRITEMASK_YZ
) {
501 brw_writemask(tmp_ud
, WRITEMASK_Y
),
502 brw_swizzle1(arg0_ud
, 0),
503 brw_imm_ud((1<<23)-1));
506 brw_writemask(tmp_ud
, WRITEMASK_Y
),
508 brw_imm_ud(127<<23));
511 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
512 /* result[2] = result[0] + LOG2(result[1]); */
514 /* Why bother? The above is just a hint how to do this with a
515 * taylor series. Maybe we *should* use a taylor series as by
516 * the time all the above has been done it's almost certainly
517 * quicker than calling the mathbox, even with low precision.
520 * - result[0] + mathbox.LOG2(result[1])
521 * - mathbox.LOG2(arg0.x)
522 * - result[0] + inline_taylor_approx(result[1])
525 BRW_MATH_FUNCTION_LOG
,
526 brw_writemask(tmp
, WRITEMASK_Z
),
527 brw_swizzle1(tmp
, 1),
528 BRW_MATH_PRECISION_FULL
);
531 brw_writemask(tmp
, WRITEMASK_Z
),
532 brw_swizzle1(tmp
, 2),
533 brw_swizzle1(tmp
, 0));
536 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
537 /* result[3] = 1.0; */
538 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_W
), brw_imm_f(1));
542 brw_MOV(p
, dst
, tmp
);
548 /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
550 static void emit_dst_noalias( struct brw_vs_compile
*c
,
555 struct brw_compile
*p
= &c
->func
;
557 /* There must be a better way to do this:
559 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
)
560 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_X
), brw_imm_f(1.0));
561 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
)
562 brw_MUL(p
, brw_writemask(dst
, WRITEMASK_Y
), arg0
, arg1
);
563 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
)
564 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Z
), arg0
);
565 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
)
566 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), arg1
);
570 static void emit_xpd( struct brw_compile
*p
,
575 brw_MUL(p
, brw_null_reg(), brw_swizzle(t
, 1,2,0,3), brw_swizzle(u
,2,0,1,3));
576 brw_MAC(p
, dst
, negate(brw_swizzle(t
, 2,0,1,3)), brw_swizzle(u
,1,2,0,3));
580 static void emit_lit_noalias( struct brw_vs_compile
*c
,
582 struct brw_reg arg0
)
584 struct brw_compile
*p
= &c
->func
;
585 struct brw_instruction
*if_insn
;
586 struct brw_reg tmp
= dst
;
587 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
592 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_YZ
), brw_imm_f(0));
593 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_XW
), brw_imm_f(1));
595 /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order
596 * to get all channels active inside the IF. In the clipping code
597 * we run with NoMask, so it's not an option and we can use
598 * BRW_EXECUTE_1 for all comparisions.
600 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,0), brw_imm_f(0));
601 if_insn
= brw_IF(p
, BRW_EXECUTE_8
);
603 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
,0));
605 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,1), brw_imm_f(0));
606 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_Z
), brw_swizzle1(arg0
,1));
607 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
610 BRW_MATH_FUNCTION_POW
,
611 brw_writemask(dst
, WRITEMASK_Z
),
612 brw_swizzle1(tmp
, 2),
613 brw_swizzle1(arg0
, 3),
614 BRW_MATH_PRECISION_PARTIAL
);
617 brw_ENDIF(p
, if_insn
);
620 static void emit_lrp_noalias(struct brw_vs_compile
*c
,
626 struct brw_compile
*p
= &c
->func
;
628 brw_ADD(p
, dst
, negate(arg0
), brw_imm_f(1.0));
629 brw_MUL(p
, brw_null_reg(), dst
, arg2
);
630 brw_MAC(p
, dst
, arg0
, arg1
);
633 /** 3 or 4-component vector normalization */
634 static void emit_nrm( struct brw_vs_compile
*c
,
639 struct brw_compile
*p
= &c
->func
;
640 struct brw_reg tmp
= get_tmp(c
);
642 /* tmp = dot(arg0, arg0) */
644 brw_DP3(p
, tmp
, arg0
, arg0
);
646 brw_DP4(p
, tmp
, arg0
, arg0
);
648 /* tmp = 1 / sqrt(tmp) */
649 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, tmp
, tmp
, BRW_MATH_PRECISION_FULL
);
651 /* dst = arg0 * tmp */
652 brw_MUL(p
, dst
, arg0
, tmp
);
658 /* TODO: relative addressing!
660 static struct brw_reg
get_reg( struct brw_vs_compile
*c
,
666 case PROGRAM_TEMPORARY
:
669 assert(c
->regs
[file
][index
].nr
!= 0);
670 return c
->regs
[file
][index
];
671 case PROGRAM_STATE_VAR
:
672 case PROGRAM_CONSTANT
:
673 case PROGRAM_UNIFORM
:
674 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
675 return c
->regs
[PROGRAM_STATE_VAR
][index
];
676 case PROGRAM_ADDRESS
:
678 return c
->regs
[file
][index
];
680 case PROGRAM_UNDEFINED
: /* undef values */
681 return brw_null_reg();
683 case PROGRAM_LOCAL_PARAM
:
684 case PROGRAM_ENV_PARAM
:
685 case PROGRAM_WRITE_ONLY
:
688 return brw_null_reg();
693 static struct brw_reg
deref( struct brw_vs_compile
*c
,
697 struct brw_compile
*p
= &c
->func
;
698 struct brw_reg tmp
= vec4(get_tmp(c
));
699 struct brw_reg vp_address
= retype(vec1(get_reg(c
, PROGRAM_ADDRESS
, 0)), BRW_REGISTER_TYPE_UW
);
700 GLuint byte_offset
= arg
.nr
* 32 + arg
.subnr
+ offset
* 16;
701 struct brw_reg indirect
= brw_vec4_indirect(0,0);
704 brw_push_insn_state(p
);
705 brw_set_access_mode(p
, BRW_ALIGN_1
);
707 /* This is pretty clunky - load the address register twice and
708 * fetch each 4-dword value in turn. There must be a way to do
709 * this in a single pass, but I couldn't get it to work.
711 brw_ADD(p
, brw_address_reg(0), vp_address
, brw_imm_d(byte_offset
));
712 brw_MOV(p
, tmp
, indirect
);
714 brw_ADD(p
, brw_address_reg(0), suboffset(vp_address
, 8), brw_imm_d(byte_offset
));
715 brw_MOV(p
, suboffset(tmp
, 4), indirect
);
717 brw_pop_insn_state(p
);
724 static void emit_arl( struct brw_vs_compile
*c
,
726 struct brw_reg arg0
)
728 struct brw_compile
*p
= &c
->func
;
729 struct brw_reg tmp
= dst
;
730 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
735 brw_RNDD(p
, tmp
, arg0
);
736 brw_MUL(p
, dst
, tmp
, brw_imm_d(16));
743 /* Will return mangled results for SWZ op. The emit_swz() function
744 * ignores this result and recalculates taking extended swizzles into
747 static struct brw_reg
get_arg( struct brw_vs_compile
*c
,
748 struct prog_src_register
*src
)
752 if (src
->File
== PROGRAM_UNDEFINED
)
753 return brw_null_reg();
756 reg
= deref(c
, c
->regs
[PROGRAM_STATE_VAR
][0], src
->Index
);
758 reg
= get_reg(c
, src
->File
, src
->Index
);
760 /* Convert 3-bit swizzle to 2-bit.
762 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(GET_SWZ(src
->Swizzle
, 0),
763 GET_SWZ(src
->Swizzle
, 1),
764 GET_SWZ(src
->Swizzle
, 2),
765 GET_SWZ(src
->Swizzle
, 3));
767 /* Note this is ok for non-swizzle instructions:
769 reg
.negate
= src
->NegateBase
? 1 : 0;
775 static struct brw_reg
get_dst( struct brw_vs_compile
*c
,
776 struct prog_dst_register dst
)
778 struct brw_reg reg
= get_reg(c
, dst
.File
, dst
.Index
);
780 reg
.dw1
.bits
.writemask
= dst
.WriteMask
;
786 static void emit_swz( struct brw_vs_compile
*c
,
788 struct prog_src_register src
)
790 struct brw_compile
*p
= &c
->func
;
791 GLuint zeros_mask
= 0;
792 GLuint ones_mask
= 0;
795 GLboolean need_tmp
= (src
.NegateBase
&&
796 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
797 struct brw_reg tmp
= dst
;
803 for (i
= 0; i
< 4; i
++) {
804 if (dst
.dw1
.bits
.writemask
& (1<<i
)) {
805 GLubyte s
= GET_SWZ(src
.Swizzle
, i
);
824 /* Do src first, in case dst aliases src:
830 arg0
= deref(c
, c
->regs
[PROGRAM_STATE_VAR
][0], src
.Index
);
832 arg0
= get_reg(c
, src
.File
, src
.Index
);
834 arg0
= brw_swizzle(arg0
,
835 src_swz
[0], src_swz
[1],
836 src_swz
[2], src_swz
[3]);
838 brw_MOV(p
, brw_writemask(tmp
, src_mask
), arg0
);
842 brw_MOV(p
, brw_writemask(tmp
, zeros_mask
), brw_imm_f(0));
845 brw_MOV(p
, brw_writemask(tmp
, ones_mask
), brw_imm_f(1));
848 brw_MOV(p
, brw_writemask(tmp
, src
.NegateBase
), negate(tmp
));
851 brw_MOV(p
, dst
, tmp
);
858 * Post-vertex-program processing. Send the results to the URB.
860 static void emit_vertex_write( struct brw_vs_compile
*c
)
862 struct brw_compile
*p
= &c
->func
;
863 struct brw_reg m0
= brw_message_reg(0);
864 struct brw_reg pos
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_HPOS
];
867 if (c
->key
.copy_edgeflag
) {
869 get_reg(c
, PROGRAM_OUTPUT
, VERT_RESULT_EDGE
),
870 get_reg(c
, PROGRAM_INPUT
, VERT_ATTRIB_EDGEFLAG
));
873 /* Build ndc coords */
875 emit_math1(c
, BRW_MATH_FUNCTION_INV
, ndc
, brw_swizzle1(pos
, 3), BRW_MATH_PRECISION_FULL
);
876 brw_MUL(p
, brw_writemask(ndc
, WRITEMASK_XYZ
), pos
, ndc
);
878 /* Update the header for point size, user clipping flags, and -ve rhw
881 if ((c
->prog_data
.outputs_written
& (1<<VERT_RESULT_PSIZ
)) ||
882 c
->key
.nr_userclip
|| !BRW_IS_G4X(p
->brw
))
884 struct brw_reg header1
= retype(get_tmp(c
), BRW_REGISTER_TYPE_UD
);
887 brw_MOV(p
, header1
, brw_imm_ud(0));
889 brw_set_access_mode(p
, BRW_ALIGN_16
);
891 if (c
->prog_data
.outputs_written
& (1<<VERT_RESULT_PSIZ
)) {
892 struct brw_reg psiz
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_PSIZ
];
893 brw_MUL(p
, brw_writemask(header1
, WRITEMASK_W
), brw_swizzle1(psiz
, 0), brw_imm_f(1<<11));
894 brw_AND(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(0x7ff<<8));
897 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
898 brw_set_conditionalmod(p
, BRW_CONDITIONAL_L
);
899 brw_DP4(p
, brw_null_reg(), pos
, c
->userplane
[i
]);
900 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<i
));
901 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
904 /* i965 clipping workaround:
905 * 1) Test for -ve rhw
907 * set ndc = (0,0,0,0)
910 * Later, clipping will detect ucp[6] and ensure the primitive is
911 * clipped against all fixed planes.
913 if (!BRW_IS_G4X(p
->brw
)) {
915 vec8(brw_null_reg()),
917 brw_swizzle1(ndc
, 3),
920 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
921 brw_MOV(p
, ndc
, brw_imm_f(0));
922 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
925 brw_set_access_mode(p
, BRW_ALIGN_1
); /* why? */
926 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), header1
);
927 brw_set_access_mode(p
, BRW_ALIGN_16
);
929 release_tmp(c
, header1
);
932 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
935 /* Emit the (interleaved) headers for the two vertices - an 8-reg
936 * of zeros followed by two sets of NDC coordinates:
938 brw_set_access_mode(p
, BRW_ALIGN_1
);
939 brw_MOV(p
, offset(m0
, 2), ndc
);
940 brw_MOV(p
, offset(m0
, 3), pos
);
943 brw_null_reg(), /* dest */
944 0, /* starting mrf reg nr */
948 c
->nr_outputs
+ 3, /* msg len */
949 0, /* response len */
951 1, /* writes complete */
952 0, /* urb destination offset */
953 BRW_URB_SWIZZLE_INTERLEAVE
);
958 post_vs_emit( struct brw_vs_compile
*c
, struct brw_instruction
*end_inst
)
960 GLuint nr_insns
= c
->vp
->program
.Base
.NumInstructions
;
961 GLuint insn
, target_insn
;
962 struct prog_instruction
*inst1
, *inst2
;
963 struct brw_instruction
*brw_inst1
, *brw_inst2
;
965 for (insn
= 0; insn
< nr_insns
; insn
++) {
966 inst1
= &c
->vp
->program
.Base
.Instructions
[insn
];
967 brw_inst1
= inst1
->Data
;
968 switch (inst1
->Opcode
) {
971 target_insn
= inst1
->BranchTarget
;
972 inst2
= &c
->vp
->program
.Base
.Instructions
[target_insn
];
973 brw_inst2
= inst2
->Data
;
974 offset
= brw_inst2
- brw_inst1
;
975 brw_set_src1(brw_inst1
, brw_imm_d(offset
*16));
978 offset
= end_inst
- brw_inst1
;
979 brw_set_src1(brw_inst1
, brw_imm_d(offset
*16));
987 /* Emit the fragment program instructions here.
989 void brw_vs_emit(struct brw_vs_compile
*c
)
992 struct brw_compile
*p
= &c
->func
;
993 GLuint nr_insns
= c
->vp
->program
.Base
.NumInstructions
;
994 GLuint insn
, if_insn
= 0;
995 struct brw_instruction
*end_inst
;
996 struct brw_instruction
*if_inst
[MAX_IFSN
];
997 struct brw_indirect stack_index
= brw_indirect(0, 0);
1002 if (INTEL_DEBUG
& DEBUG_VS
) {
1003 _mesa_printf("vs-emit:\n");
1004 _mesa_print_program(&c
->vp
->program
.Base
);
1008 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1009 brw_set_access_mode(p
, BRW_ALIGN_16
);
1011 /* Message registers can't be read, so copy the output into GRF register
1012 if they are used in source registers */
1013 for (insn
= 0; insn
< nr_insns
; insn
++) {
1015 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1016 for (i
= 0; i
< 3; i
++) {
1017 struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1018 GLuint index
= src
->Index
;
1019 GLuint file
= src
->File
;
1020 if (file
== PROGRAM_OUTPUT
&& index
!= VERT_RESULT_HPOS
)
1021 c
->output_regs
[index
].used_in_src
= GL_TRUE
;
1025 /* Static register allocation
1027 brw_vs_alloc_regs(c
);
1028 brw_MOV(p
, get_addr_reg(stack_index
), brw_address(c
->stack
));
1030 for (insn
= 0; insn
< nr_insns
; insn
++) {
1032 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1033 struct brw_reg args
[3], dst
;
1036 /* Get argument regs. SWZ is special and does this itself.
1038 inst
->Data
= &p
->store
[p
->nr_insn
];
1039 if (inst
->Opcode
!= OPCODE_SWZ
)
1040 for (i
= 0; i
< 3; i
++) {
1041 struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1044 if (file
== PROGRAM_OUTPUT
&&c
->output_regs
[index
].used_in_src
)
1045 args
[i
] = c
->output_regs
[index
].reg
;
1047 args
[i
] = get_arg(c
, src
);
1050 /* Get dest regs. Note that it is possible for a reg to be both
1051 * dst and arg, given the static allocation of registers. So
1052 * care needs to be taken emitting multi-operation instructions.
1054 index
= inst
->DstReg
.Index
;
1055 file
= inst
->DstReg
.File
;
1056 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1057 dst
= c
->output_regs
[index
].reg
;
1059 dst
= get_dst(c
, inst
->DstReg
);
1061 if (inst
->SaturateMode
!= SATURATE_OFF
) {
1062 _mesa_problem(NULL
, "Unsupported saturate %d in vertex shader",
1063 inst
->SaturateMode
);
1066 switch (inst
->Opcode
) {
1068 brw_MOV(p
, dst
, brw_abs(args
[0]));
1071 brw_ADD(p
, dst
, args
[0], args
[1]);
1074 emit_math1(c
, BRW_MATH_FUNCTION_COS
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1077 brw_DP3(p
, dst
, args
[0], args
[1]);
1080 brw_DP4(p
, dst
, args
[0], args
[1]);
1083 brw_DPH(p
, dst
, args
[0], args
[1]);
1086 emit_nrm(c
, dst
, args
[0], 3);
1089 emit_nrm(c
, dst
, args
[0], 4);
1092 unalias2(c
, dst
, args
[0], args
[1], emit_dst_noalias
);
1095 unalias1(c
, dst
, args
[0], emit_exp_noalias
);
1098 emit_math1(c
, BRW_MATH_FUNCTION_EXP
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1101 emit_arl(c
, dst
, args
[0]);
1104 brw_RNDD(p
, dst
, args
[0]);
1107 brw_FRC(p
, dst
, args
[0]);
1110 unalias1(c
, dst
, args
[0], emit_log_noalias
);
1113 emit_math1(c
, BRW_MATH_FUNCTION_LOG
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1116 unalias1(c
, dst
, args
[0], emit_lit_noalias
);
1119 unalias3(c
, dst
, args
[0], args
[1], args
[2], emit_lrp_noalias
);
1122 brw_MOV(p
, brw_acc_reg(), args
[2]);
1123 brw_MAC(p
, dst
, args
[0], args
[1]);
1126 emit_max(p
, dst
, args
[0], args
[1]);
1129 emit_min(p
, dst
, args
[0], args
[1]);
1132 brw_MOV(p
, dst
, args
[0]);
1135 brw_MUL(p
, dst
, args
[0], args
[1]);
1138 emit_math2(c
, BRW_MATH_FUNCTION_POW
, dst
, args
[0], args
[1], BRW_MATH_PRECISION_FULL
);
1141 emit_math1(c
, BRW_MATH_FUNCTION_INV
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1144 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1148 emit_seq(p
, dst
, args
[0], args
[1]);
1151 emit_math1(c
, BRW_MATH_FUNCTION_SIN
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1154 emit_sne(p
, dst
, args
[0], args
[1]);
1157 emit_sge(p
, dst
, args
[0], args
[1]);
1160 emit_sgt(p
, dst
, args
[0], args
[1]);
1163 emit_slt(p
, dst
, args
[0], args
[1]);
1166 emit_sle(p
, dst
, args
[0], args
[1]);
1169 brw_ADD(p
, dst
, args
[0], negate(args
[1]));
1172 /* The args[0] value can't be used here as it won't have
1173 * correctly encoded the full swizzle:
1175 emit_swz(c
, dst
, inst
->SrcReg
[0] );
1178 /* round toward zero */
1179 brw_RNDZ(p
, dst
, args
[0]);
1182 emit_xpd(p
, dst
, args
[0], args
[1]);
1185 assert(if_insn
< MAX_IFSN
);
1186 if_inst
[if_insn
++] = brw_IF(p
, BRW_EXECUTE_8
);
1189 if_inst
[if_insn
-1] = brw_ELSE(p
, if_inst
[if_insn
-1]);
1192 assert(if_insn
> 0);
1193 brw_ENDIF(p
, if_inst
[--if_insn
]);
1196 brw_set_predicate_control(p
, BRW_PREDICATE_NORMAL
);
1197 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1198 brw_set_predicate_control_flag_value(p
, 0xff);
1201 brw_set_access_mode(p
, BRW_ALIGN_1
);
1202 brw_ADD(p
, deref_1d(stack_index
, 0), brw_ip_reg(), brw_imm_d(3*16));
1203 brw_set_access_mode(p
, BRW_ALIGN_16
);
1204 brw_ADD(p
, get_addr_reg(stack_index
),
1205 get_addr_reg(stack_index
), brw_imm_d(4));
1206 inst
->Data
= &p
->store
[p
->nr_insn
];
1207 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1210 brw_ADD(p
, get_addr_reg(stack_index
),
1211 get_addr_reg(stack_index
), brw_imm_d(-4));
1212 brw_set_access_mode(p
, BRW_ALIGN_1
);
1213 brw_MOV(p
, brw_ip_reg(), deref_1d(stack_index
, 0));
1214 brw_set_access_mode(p
, BRW_ALIGN_16
);
1217 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1222 /* no-op instructions */
1225 _mesa_problem(NULL
, "Unsupported opcode %i (%s) in vertex shader",
1226 inst
->Opcode
, inst
->Opcode
< MAX_OPCODE
?
1227 _mesa_opcode_string(inst
->Opcode
) :
1231 if ((inst
->DstReg
.File
== PROGRAM_OUTPUT
)
1232 && (inst
->DstReg
.Index
!= VERT_RESULT_HPOS
)
1233 && c
->output_regs
[inst
->DstReg
.Index
].used_in_src
) {
1234 brw_MOV(p
, get_dst(c
, inst
->DstReg
), dst
);
1237 /* Result color clamping.
1239 * When destination register is an output register and
1240 * it's primary/secondary front/back color, we have to clamp
1241 * the result to [0,1]. This is done by enabling the
1242 * saturation bit for the last instruction.
1244 * We don't use brw_set_saturate() as it modifies
1245 * p->current->header.saturate, which affects all the subsequent
1246 * instructions. Instead, we directly modify the header
1247 * of the last (already stored) instruction.
1249 if (inst
->DstReg
.File
== PROGRAM_OUTPUT
) {
1250 if ((inst
->DstReg
.Index
== VERT_RESULT_COL0
)
1251 || (inst
->DstReg
.Index
== VERT_RESULT_COL1
)
1252 || (inst
->DstReg
.Index
== VERT_RESULT_BFC0
)
1253 || (inst
->DstReg
.Index
== VERT_RESULT_BFC1
)) {
1254 p
->store
[p
->nr_insn
-1].header
.saturate
= 1;
1261 end_inst
= &p
->store
[p
->nr_insn
];
1262 emit_vertex_write(c
);
1263 post_vs_emit(c
, end_inst
);
1264 for (insn
= 0; insn
< nr_insns
; insn
++)
1265 c
->vp
->program
.Base
.Instructions
[insn
].Data
= NULL
;