2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/macros.h"
34 #include "shader/program.h"
35 #include "shader/prog_parameter.h"
36 #include "shader/prog_print.h"
37 #include "brw_context.h"
41 static struct brw_reg
get_tmp( struct brw_vs_compile
*c
)
43 struct brw_reg tmp
= brw_vec8_grf(c
->last_tmp
, 0);
45 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
46 c
->prog_data
.total_grf
= c
->last_tmp
;
51 static void release_tmp( struct brw_vs_compile
*c
, struct brw_reg tmp
)
53 if (tmp
.nr
== c
->last_tmp
-1)
57 static void release_tmps( struct brw_vs_compile
*c
)
59 c
->last_tmp
= c
->first_tmp
;
64 * Preallocate GRF register before code emit.
65 * Do things as simply as possible. Allocate and populate all regs
68 static void brw_vs_alloc_regs( struct brw_vs_compile
*c
)
70 struct intel_context
*intel
= &c
->func
.brw
->intel
;
71 GLuint i
, reg
= 0, mrf
;
72 int attributes_in_vue
;
74 /* Determine whether to use a real constant buffer or use a block
75 * of GRF registers for constants. The later is faster but only
76 * works if everything fits in the GRF.
77 * XXX this heuristic/check may need some fine tuning...
79 if (c
->vp
->program
.Base
.Parameters
->NumParameters
+
80 c
->vp
->program
.Base
.NumTemporaries
+ 20 > BRW_MAX_GRF
)
81 c
->vp
->use_const_buffer
= GL_TRUE
;
83 c
->vp
->use_const_buffer
= GL_FALSE
;
85 /*printf("use_const_buffer = %d\n", c->vp->use_const_buffer);*/
87 /* r0 -- reserved as usual
89 c
->r0
= brw_vec8_grf(reg
, 0);
92 /* User clip planes from curbe:
94 if (c
->key
.nr_userclip
) {
95 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
96 c
->userplane
[i
] = stride( brw_vec4_grf(reg
+3+i
/2, (i
%2) * 4), 0, 4, 1);
99 /* Deal with curbe alignment:
101 reg
+= ((6 + c
->key
.nr_userclip
+ 3) / 4) * 2;
104 /* Vertex program parameters from curbe:
106 if (c
->vp
->use_const_buffer
) {
107 int max_constant
= BRW_MAX_GRF
- 20 - c
->vp
->program
.Base
.NumTemporaries
;
110 /* We've got more constants than we can load with the push
111 * mechanism. This is often correlated with reladdr loads where
112 * we should probably be using a pull mechanism anyway to avoid
113 * excessive reading. However, the pull mechanism is slow in
114 * general. So, we try to allocate as many non-reladdr-loaded
115 * constants through the push buffer as we can before giving up.
117 memset(c
->constant_map
, -1, c
->vp
->program
.Base
.Parameters
->NumParameters
);
119 i
< c
->vp
->program
.Base
.NumInstructions
&& constant
< max_constant
;
121 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[i
];
124 for (arg
= 0; arg
< 3 && constant
< max_constant
; arg
++) {
125 if ((inst
->SrcReg
[arg
].File
!= PROGRAM_STATE_VAR
&&
126 inst
->SrcReg
[arg
].File
!= PROGRAM_CONSTANT
&&
127 inst
->SrcReg
[arg
].File
!= PROGRAM_UNIFORM
&&
128 inst
->SrcReg
[arg
].File
!= PROGRAM_ENV_PARAM
&&
129 inst
->SrcReg
[arg
].File
!= PROGRAM_LOCAL_PARAM
) ||
130 inst
->SrcReg
[arg
].RelAddr
)
133 if (c
->constant_map
[inst
->SrcReg
[arg
].Index
] == -1) {
134 c
->constant_map
[inst
->SrcReg
[arg
].Index
] = constant
++;
139 for (i
= 0; i
< constant
; i
++) {
140 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2,
144 reg
+= (constant
+ 1) / 2;
145 c
->prog_data
.curb_read_length
= reg
- 1;
146 /* XXX 0 causes a bug elsewhere... */
147 c
->prog_data
.nr_params
= MAX2(constant
* 4, 4);
150 /* use a section of the GRF for constants */
151 GLuint nr_params
= c
->vp
->program
.Base
.Parameters
->NumParameters
;
152 for (i
= 0; i
< nr_params
; i
++) {
153 c
->regs
[PROGRAM_STATE_VAR
][i
] = stride( brw_vec4_grf(reg
+i
/2, (i
%2) * 4), 0, 4, 1);
155 reg
+= (nr_params
+ 1) / 2;
156 c
->prog_data
.curb_read_length
= reg
- 1;
158 c
->prog_data
.nr_params
= nr_params
* 4;
161 /* Allocate input regs:
164 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
165 if (c
->prog_data
.inputs_read
& (1 << i
)) {
167 c
->regs
[PROGRAM_INPUT
][i
] = brw_vec8_grf(reg
, 0);
171 /* If there are no inputs, we'll still be reading one attribute's worth
172 * because it's required -- see urb_read_length setting.
174 if (c
->nr_inputs
== 0)
177 /* Allocate outputs. The non-position outputs go straight into message regs.
180 c
->first_output
= reg
;
181 c
->first_overflow_output
= 0;
185 else if (intel
->is_ironlake
)
190 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
191 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(i
)) {
193 assert(i
< Elements(c
->regs
[PROGRAM_OUTPUT
]));
194 if (i
== VERT_RESULT_HPOS
) {
195 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
198 else if (i
== VERT_RESULT_PSIZ
) {
199 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
201 mrf
++; /* just a placeholder? XXX fix later stages & remove this */
205 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_message_reg(mrf
);
209 /* too many vertex results to fit in MRF, use GRF for overflow */
210 if (!c
->first_overflow_output
)
211 c
->first_overflow_output
= i
;
212 c
->regs
[PROGRAM_OUTPUT
][i
] = brw_vec8_grf(reg
, 0);
219 /* Allocate program temporaries:
221 for (i
= 0; i
< c
->vp
->program
.Base
.NumTemporaries
; i
++) {
222 c
->regs
[PROGRAM_TEMPORARY
][i
] = brw_vec8_grf(reg
, 0);
226 /* Address reg(s). Don't try to use the internal address reg until
229 for (i
= 0; i
< c
->vp
->program
.Base
.NumAddressRegs
; i
++) {
230 c
->regs
[PROGRAM_ADDRESS
][i
] = brw_reg(BRW_GENERAL_REGISTER_FILE
,
234 BRW_VERTICAL_STRIDE_8
,
236 BRW_HORIZONTAL_STRIDE_1
,
242 if (c
->vp
->use_const_buffer
) {
243 for (i
= 0; i
< 3; i
++) {
244 c
->current_const
[i
].index
= -1;
245 c
->current_const
[i
].reg
= brw_vec8_grf(reg
, 0);
250 for (i
= 0; i
< 128; i
++) {
251 if (c
->output_regs
[i
].used_in_src
) {
252 c
->output_regs
[i
].reg
= brw_vec8_grf(reg
, 0);
257 if (c
->needs_stack
) {
258 c
->stack
= brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, reg
, 0);
262 /* Some opcodes need an internal temporary:
265 c
->last_tmp
= reg
; /* for allocation purposes */
267 /* Each input reg holds data from two vertices. The
268 * urb_read_length is the number of registers read from *each*
269 * vertex urb, so is half the amount:
271 c
->prog_data
.urb_read_length
= (c
->nr_inputs
+ 1) / 2;
272 /* Setting this field to 0 leads to undefined behavior according to the
273 * the VS_STATE docs. Our VUEs will always have at least one attribute
274 * sitting in them, even if it's padding.
276 if (c
->prog_data
.urb_read_length
== 0)
277 c
->prog_data
.urb_read_length
= 1;
279 /* The VS VUEs are shared by VF (outputting our inputs) and VS, so size
280 * them to fit the biggest thing they need to.
282 attributes_in_vue
= MAX2(c
->nr_outputs
, c
->nr_inputs
);
285 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 4 + 7) / 8;
286 else if (intel
->is_ironlake
)
287 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 6 + 3) / 4;
289 c
->prog_data
.urb_entry_size
= (attributes_in_vue
+ 2 + 3) / 4;
291 c
->prog_data
.total_grf
= reg
;
293 if (INTEL_DEBUG
& DEBUG_VS
) {
294 printf("%s NumAddrRegs %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumAddressRegs
);
295 printf("%s NumTemps %d\n", __FUNCTION__
, c
->vp
->program
.Base
.NumTemporaries
);
296 printf("%s reg = %d\n", __FUNCTION__
, reg
);
302 * If an instruction uses a temp reg both as a src and the dest, we
303 * sometimes need to allocate an intermediate temporary.
305 static void unalias1( struct brw_vs_compile
*c
,
308 void (*func
)( struct brw_vs_compile
*,
312 if (dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) {
313 struct brw_compile
*p
= &c
->func
;
314 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
316 brw_MOV(p
, dst
, tmp
);
326 * Checkes if 2-operand instruction needs an intermediate temporary.
328 static void unalias2( struct brw_vs_compile
*c
,
332 void (*func
)( struct brw_vs_compile
*,
337 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
338 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
)) {
339 struct brw_compile
*p
= &c
->func
;
340 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
341 func(c
, tmp
, arg0
, arg1
);
342 brw_MOV(p
, dst
, tmp
);
346 func(c
, dst
, arg0
, arg1
);
352 * Checkes if 3-operand instruction needs an intermediate temporary.
354 static void unalias3( struct brw_vs_compile
*c
,
359 void (*func
)( struct brw_vs_compile
*,
365 if ((dst
.file
== arg0
.file
&& dst
.nr
== arg0
.nr
) ||
366 (dst
.file
== arg1
.file
&& dst
.nr
== arg1
.nr
) ||
367 (dst
.file
== arg2
.file
&& dst
.nr
== arg2
.nr
)) {
368 struct brw_compile
*p
= &c
->func
;
369 struct brw_reg tmp
= brw_writemask(get_tmp(c
), dst
.dw1
.bits
.writemask
);
370 func(c
, tmp
, arg0
, arg1
, arg2
);
371 brw_MOV(p
, dst
, tmp
);
375 func(c
, dst
, arg0
, arg1
, arg2
);
379 static void emit_sop( struct brw_vs_compile
*c
,
385 struct brw_compile
*p
= &c
->func
;
387 brw_MOV(p
, dst
, brw_imm_f(0.0f
));
388 brw_CMP(p
, brw_null_reg(), cond
, arg0
, arg1
);
389 brw_MOV(p
, dst
, brw_imm_f(1.0f
));
390 brw_set_predicate_control_flag_value(p
, 0xff);
393 static void emit_seq( struct brw_vs_compile
*c
,
396 struct brw_reg arg1
)
398 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_EQ
);
401 static void emit_sne( struct brw_vs_compile
*c
,
404 struct brw_reg arg1
)
406 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_NEQ
);
408 static void emit_slt( struct brw_vs_compile
*c
,
411 struct brw_reg arg1
)
413 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_L
);
416 static void emit_sle( struct brw_vs_compile
*c
,
419 struct brw_reg arg1
)
421 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_LE
);
424 static void emit_sgt( struct brw_vs_compile
*c
,
427 struct brw_reg arg1
)
429 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_G
);
432 static void emit_sge( struct brw_vs_compile
*c
,
435 struct brw_reg arg1
)
437 emit_sop(c
, dst
, arg0
, arg1
, BRW_CONDITIONAL_GE
);
440 static void emit_cmp( struct brw_compile
*p
,
444 struct brw_reg arg2
)
446 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, brw_imm_f(0));
447 brw_SEL(p
, dst
, arg1
, arg2
);
448 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
451 static void emit_max( struct brw_compile
*p
,
454 struct brw_reg arg1
)
456 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
457 brw_SEL(p
, dst
, arg1
, arg0
);
458 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
461 static void emit_min( struct brw_compile
*p
,
464 struct brw_reg arg1
)
466 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_L
, arg0
, arg1
);
467 brw_SEL(p
, dst
, arg0
, arg1
);
468 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
472 static void emit_math1( struct brw_vs_compile
*c
,
478 /* There are various odd behaviours with SEND on the simulator. In
479 * addition there are documented issues with the fact that the GEN4
480 * processor doesn't do dependency control properly on SEND
481 * results. So, on balance, this kludge to get around failures
482 * with writemasked math results looks like it might be necessary
483 * whether that turns out to be a simulator bug or not:
485 struct brw_compile
*p
= &c
->func
;
486 struct intel_context
*intel
= &p
->brw
->intel
;
487 struct brw_reg tmp
= dst
;
488 GLboolean need_tmp
= (intel
->gen
< 6 &&
489 (dst
.dw1
.bits
.writemask
!= 0xf ||
490 dst
.file
!= BRW_GENERAL_REGISTER_FILE
));
498 BRW_MATH_SATURATE_NONE
,
501 BRW_MATH_DATA_SCALAR
,
505 brw_MOV(p
, dst
, tmp
);
511 static void emit_math2( struct brw_vs_compile
*c
,
518 struct brw_compile
*p
= &c
->func
;
519 struct intel_context
*intel
= &p
->brw
->intel
;
520 struct brw_reg tmp
= dst
;
521 GLboolean need_tmp
= (intel
->gen
< 6 &&
522 (dst
.dw1
.bits
.writemask
!= 0xf ||
523 dst
.file
!= BRW_GENERAL_REGISTER_FILE
));
528 brw_MOV(p
, brw_message_reg(3), arg1
);
533 BRW_MATH_SATURATE_NONE
,
536 BRW_MATH_DATA_SCALAR
,
540 brw_MOV(p
, dst
, tmp
);
546 static void emit_exp_noalias( struct brw_vs_compile
*c
,
548 struct brw_reg arg0
)
550 struct brw_compile
*p
= &c
->func
;
553 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
) {
554 struct brw_reg tmp
= get_tmp(c
);
555 struct brw_reg tmp_d
= retype(tmp
, BRW_REGISTER_TYPE_D
);
557 /* tmp_d = floor(arg0.x) */
558 brw_RNDD(p
, tmp_d
, brw_swizzle1(arg0
, 0));
560 /* result[0] = 2.0 ^ tmp */
562 /* Adjust exponent for floating point:
565 brw_ADD(p
, brw_writemask(tmp_d
, WRITEMASK_X
), tmp_d
, brw_imm_d(127));
567 /* Install exponent and sign.
568 * Excess drops off the edge:
570 brw_SHL(p
, brw_writemask(retype(dst
, BRW_REGISTER_TYPE_D
), WRITEMASK_X
),
571 tmp_d
, brw_imm_d(23));
576 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
) {
577 /* result[1] = arg0.x - floor(arg0.x) */
578 brw_FRC(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
, 0));
581 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
582 /* As with the LOG instruction, we might be better off just
583 * doing a taylor expansion here, seeing as we have to do all
586 * If mathbox partial precision is too low, consider also:
587 * result[3] = result[0] * EXP(result[1])
590 BRW_MATH_FUNCTION_EXP
,
591 brw_writemask(dst
, WRITEMASK_Z
),
592 brw_swizzle1(arg0
, 0),
593 BRW_MATH_PRECISION_FULL
);
596 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
597 /* result[3] = 1.0; */
598 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), brw_imm_f(1));
603 static void emit_log_noalias( struct brw_vs_compile
*c
,
605 struct brw_reg arg0
)
607 struct brw_compile
*p
= &c
->func
;
608 struct brw_reg tmp
= dst
;
609 struct brw_reg tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
610 struct brw_reg arg0_ud
= retype(arg0
, BRW_REGISTER_TYPE_UD
);
611 GLboolean need_tmp
= (dst
.dw1
.bits
.writemask
!= 0xf ||
612 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
616 tmp_ud
= retype(tmp
, BRW_REGISTER_TYPE_UD
);
619 /* Perform mant = frexpf(fabsf(x), &exp), adjust exp and mnt
622 * These almost look likey they could be joined up, but not really
625 * result[0].f = (x.i & ((1<<31)-1) >> 23) - 127
626 * result[1].i = (x.i & ((1<<23)-1) + (127<<23)
628 if (dst
.dw1
.bits
.writemask
& WRITEMASK_XZ
) {
630 brw_writemask(tmp_ud
, WRITEMASK_X
),
631 brw_swizzle1(arg0_ud
, 0),
632 brw_imm_ud((1U<<31)-1));
635 brw_writemask(tmp_ud
, WRITEMASK_X
),
640 brw_writemask(tmp
, WRITEMASK_X
),
641 retype(tmp_ud
, BRW_REGISTER_TYPE_D
), /* does it matter? */
645 if (dst
.dw1
.bits
.writemask
& WRITEMASK_YZ
) {
647 brw_writemask(tmp_ud
, WRITEMASK_Y
),
648 brw_swizzle1(arg0_ud
, 0),
649 brw_imm_ud((1<<23)-1));
652 brw_writemask(tmp_ud
, WRITEMASK_Y
),
654 brw_imm_ud(127<<23));
657 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
) {
658 /* result[2] = result[0] + LOG2(result[1]); */
660 /* Why bother? The above is just a hint how to do this with a
661 * taylor series. Maybe we *should* use a taylor series as by
662 * the time all the above has been done it's almost certainly
663 * quicker than calling the mathbox, even with low precision.
666 * - result[0] + mathbox.LOG2(result[1])
667 * - mathbox.LOG2(arg0.x)
668 * - result[0] + inline_taylor_approx(result[1])
671 BRW_MATH_FUNCTION_LOG
,
672 brw_writemask(tmp
, WRITEMASK_Z
),
673 brw_swizzle1(tmp
, 1),
674 BRW_MATH_PRECISION_FULL
);
677 brw_writemask(tmp
, WRITEMASK_Z
),
678 brw_swizzle1(tmp
, 2),
679 brw_swizzle1(tmp
, 0));
682 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
) {
683 /* result[3] = 1.0; */
684 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_W
), brw_imm_f(1));
688 brw_MOV(p
, dst
, tmp
);
694 /* Need to unalias - consider swizzles: r0 = DST r0.xxxx r1
696 static void emit_dst_noalias( struct brw_vs_compile
*c
,
701 struct brw_compile
*p
= &c
->func
;
703 /* There must be a better way to do this:
705 if (dst
.dw1
.bits
.writemask
& WRITEMASK_X
)
706 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_X
), brw_imm_f(1.0));
707 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Y
)
708 brw_MUL(p
, brw_writemask(dst
, WRITEMASK_Y
), arg0
, arg1
);
709 if (dst
.dw1
.bits
.writemask
& WRITEMASK_Z
)
710 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Z
), arg0
);
711 if (dst
.dw1
.bits
.writemask
& WRITEMASK_W
)
712 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_W
), arg1
);
716 static void emit_xpd( struct brw_compile
*p
,
721 brw_MUL(p
, brw_null_reg(), brw_swizzle(t
, 1,2,0,3), brw_swizzle(u
,2,0,1,3));
722 brw_MAC(p
, dst
, negate(brw_swizzle(t
, 2,0,1,3)), brw_swizzle(u
,1,2,0,3));
726 static void emit_lit_noalias( struct brw_vs_compile
*c
,
728 struct brw_reg arg0
)
730 struct brw_compile
*p
= &c
->func
;
731 struct brw_instruction
*if_insn
;
732 struct brw_reg tmp
= dst
;
733 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
738 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_YZ
), brw_imm_f(0));
739 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_XW
), brw_imm_f(1));
741 /* Need to use BRW_EXECUTE_8 and also do an 8-wide compare in order
742 * to get all channels active inside the IF. In the clipping code
743 * we run with NoMask, so it's not an option and we can use
744 * BRW_EXECUTE_1 for all comparisions.
746 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,0), brw_imm_f(0));
747 if_insn
= brw_IF(p
, BRW_EXECUTE_8
);
749 brw_MOV(p
, brw_writemask(dst
, WRITEMASK_Y
), brw_swizzle1(arg0
,0));
751 brw_CMP(p
, brw_null_reg(), BRW_CONDITIONAL_G
, brw_swizzle1(arg0
,1), brw_imm_f(0));
752 brw_MOV(p
, brw_writemask(tmp
, WRITEMASK_Z
), brw_swizzle1(arg0
,1));
753 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
756 BRW_MATH_FUNCTION_POW
,
757 brw_writemask(dst
, WRITEMASK_Z
),
758 brw_swizzle1(tmp
, 2),
759 brw_swizzle1(arg0
, 3),
760 BRW_MATH_PRECISION_PARTIAL
);
763 brw_ENDIF(p
, if_insn
);
768 static void emit_lrp_noalias(struct brw_vs_compile
*c
,
774 struct brw_compile
*p
= &c
->func
;
776 brw_ADD(p
, dst
, negate(arg0
), brw_imm_f(1.0));
777 brw_MUL(p
, brw_null_reg(), dst
, arg2
);
778 brw_MAC(p
, dst
, arg0
, arg1
);
781 /** 3 or 4-component vector normalization */
782 static void emit_nrm( struct brw_vs_compile
*c
,
787 struct brw_compile
*p
= &c
->func
;
788 struct brw_reg tmp
= get_tmp(c
);
790 /* tmp = dot(arg0, arg0) */
792 brw_DP3(p
, tmp
, arg0
, arg0
);
794 brw_DP4(p
, tmp
, arg0
, arg0
);
796 /* tmp = 1 / sqrt(tmp) */
797 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, tmp
, tmp
, BRW_MATH_PRECISION_FULL
);
799 /* dst = arg0 * tmp */
800 brw_MUL(p
, dst
, arg0
, tmp
);
806 static struct brw_reg
807 get_constant(struct brw_vs_compile
*c
,
808 const struct prog_instruction
*inst
,
811 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
812 struct brw_compile
*p
= &c
->func
;
813 struct brw_reg const_reg
= c
->current_const
[argIndex
].reg
;
815 assert(argIndex
< 3);
817 if (c
->current_const
[argIndex
].index
!= src
->Index
) {
818 struct brw_reg addrReg
= c
->regs
[PROGRAM_ADDRESS
][0];
820 /* Keep track of the last constant loaded in this slot, for reuse. */
821 c
->current_const
[argIndex
].index
= src
->Index
;
824 printf(" fetch const[%d] for arg %d into reg %d\n",
825 src
->Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
827 /* need to fetch the constant now */
829 const_reg
, /* writeback dest */
831 0, /* relative indexing? */
832 addrReg
, /* address register */
833 16 * src
->Index
, /* byte offset */
834 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
838 /* replicate lower four floats into upper half (to get XYZWXYZW) */
839 const_reg
= stride(const_reg
, 0, 4, 0);
845 static struct brw_reg
846 get_reladdr_constant(struct brw_vs_compile
*c
,
847 const struct prog_instruction
*inst
,
850 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
851 struct brw_compile
*p
= &c
->func
;
852 struct brw_reg const_reg
= c
->current_const
[argIndex
].reg
;
853 struct brw_reg const2_reg
;
854 struct brw_reg addrReg
= c
->regs
[PROGRAM_ADDRESS
][0];
856 assert(argIndex
< 3);
858 /* Can't reuse a reladdr constant load. */
859 c
->current_const
[argIndex
].index
= -1;
862 printf(" fetch const[a0.x+%d] for arg %d into reg %d\n",
863 src
->Index
, argIndex
, c
->current_const
[argIndex
].reg
.nr
);
866 /* fetch the first vec4 */
868 const_reg
, /* writeback dest */
870 1, /* relative indexing? */
871 addrReg
, /* address register */
872 16 * src
->Index
, /* byte offset */
873 SURF_INDEX_VERT_CONST_BUFFER
/* binding table index */
876 const2_reg
= get_tmp(c
);
878 /* use upper half of address reg for second read */
879 addrReg
= stride(addrReg
, 0, 4, 0);
883 const2_reg
, /* writeback dest */
885 1, /* relative indexing? */
886 addrReg
, /* address register */
887 16 * src
->Index
, /* byte offset */
888 SURF_INDEX_VERT_CONST_BUFFER
891 /* merge the two Owords into the constant register */
892 /* const_reg[7..4] = const2_reg[7..4] */
894 suboffset(stride(const_reg
, 0, 4, 1), 4),
895 suboffset(stride(const2_reg
, 0, 4, 1), 4));
896 release_tmp(c
, const2_reg
);
903 /* TODO: relative addressing!
905 static struct brw_reg
get_reg( struct brw_vs_compile
*c
,
906 gl_register_file file
,
910 case PROGRAM_TEMPORARY
:
913 assert(c
->regs
[file
][index
].nr
!= 0);
914 return c
->regs
[file
][index
];
915 case PROGRAM_STATE_VAR
:
916 case PROGRAM_CONSTANT
:
917 case PROGRAM_UNIFORM
:
918 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
919 return c
->regs
[PROGRAM_STATE_VAR
][index
];
920 case PROGRAM_ADDRESS
:
922 return c
->regs
[file
][index
];
924 case PROGRAM_UNDEFINED
: /* undef values */
925 return brw_null_reg();
927 case PROGRAM_LOCAL_PARAM
:
928 case PROGRAM_ENV_PARAM
:
929 case PROGRAM_WRITE_ONLY
:
932 return brw_null_reg();
938 * Indirect addressing: get reg[[arg] + offset].
940 static struct brw_reg
deref( struct brw_vs_compile
*c
,
944 struct brw_compile
*p
= &c
->func
;
945 struct brw_reg tmp
= vec4(get_tmp(c
));
946 struct brw_reg addr_reg
= c
->regs
[PROGRAM_ADDRESS
][0];
947 struct brw_reg vp_address
= retype(vec1(addr_reg
), BRW_REGISTER_TYPE_UW
);
948 GLuint byte_offset
= arg
.nr
* 32 + arg
.subnr
+ offset
* 16;
949 struct brw_reg indirect
= brw_vec4_indirect(0,0);
952 brw_push_insn_state(p
);
953 brw_set_access_mode(p
, BRW_ALIGN_1
);
955 /* This is pretty clunky - load the address register twice and
956 * fetch each 4-dword value in turn. There must be a way to do
957 * this in a single pass, but I couldn't get it to work.
959 brw_ADD(p
, brw_address_reg(0), vp_address
, brw_imm_d(byte_offset
));
960 brw_MOV(p
, tmp
, indirect
);
962 brw_ADD(p
, brw_address_reg(0), suboffset(vp_address
, 8), brw_imm_d(byte_offset
));
963 brw_MOV(p
, suboffset(tmp
, 4), indirect
);
965 brw_pop_insn_state(p
);
968 /* NOTE: tmp not released */
974 * Get brw reg corresponding to the instruction's [argIndex] src reg.
975 * TODO: relative addressing!
977 static struct brw_reg
978 get_src_reg( struct brw_vs_compile
*c
,
979 const struct prog_instruction
*inst
,
982 const GLuint file
= inst
->SrcReg
[argIndex
].File
;
983 const GLint index
= inst
->SrcReg
[argIndex
].Index
;
984 const GLboolean relAddr
= inst
->SrcReg
[argIndex
].RelAddr
;
987 case PROGRAM_TEMPORARY
:
991 return deref(c
, c
->regs
[file
][0], index
);
994 assert(c
->regs
[file
][index
].nr
!= 0);
995 return c
->regs
[file
][index
];
998 case PROGRAM_STATE_VAR
:
999 case PROGRAM_CONSTANT
:
1000 case PROGRAM_UNIFORM
:
1001 case PROGRAM_ENV_PARAM
:
1002 case PROGRAM_LOCAL_PARAM
:
1003 if (c
->vp
->use_const_buffer
) {
1004 if (!relAddr
&& c
->constant_map
[index
] != -1) {
1005 assert(c
->regs
[PROGRAM_STATE_VAR
][c
->constant_map
[index
]].nr
!= 0);
1006 return c
->regs
[PROGRAM_STATE_VAR
][c
->constant_map
[index
]];
1008 return get_reladdr_constant(c
, inst
, argIndex
);
1010 return get_constant(c
, inst
, argIndex
);
1013 return deref(c
, c
->regs
[PROGRAM_STATE_VAR
][0], index
);
1016 assert(c
->regs
[PROGRAM_STATE_VAR
][index
].nr
!= 0);
1017 return c
->regs
[PROGRAM_STATE_VAR
][index
];
1019 case PROGRAM_ADDRESS
:
1021 return c
->regs
[file
][index
];
1023 case PROGRAM_UNDEFINED
:
1024 /* this is a normal case since we loop over all three src args */
1025 return brw_null_reg();
1027 case PROGRAM_WRITE_ONLY
:
1030 return brw_null_reg();
1035 static void emit_arl( struct brw_vs_compile
*c
,
1037 struct brw_reg arg0
)
1039 struct brw_compile
*p
= &c
->func
;
1040 struct brw_reg tmp
= dst
;
1041 GLboolean need_tmp
= (dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
1046 brw_RNDD(p
, tmp
, arg0
); /* tmp = round(arg0) */
1047 brw_MUL(p
, dst
, tmp
, brw_imm_d(16)); /* dst = tmp * 16 */
1050 release_tmp(c
, tmp
);
1055 * Return the brw reg for the given instruction's src argument.
1056 * Will return mangled results for SWZ op. The emit_swz() function
1057 * ignores this result and recalculates taking extended swizzles into
1060 static struct brw_reg
get_arg( struct brw_vs_compile
*c
,
1061 const struct prog_instruction
*inst
,
1064 const struct prog_src_register
*src
= &inst
->SrcReg
[argIndex
];
1067 if (src
->File
== PROGRAM_UNDEFINED
)
1068 return brw_null_reg();
1070 reg
= get_src_reg(c
, inst
, argIndex
);
1072 /* Convert 3-bit swizzle to 2-bit.
1074 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(GET_SWZ(src
->Swizzle
, 0),
1075 GET_SWZ(src
->Swizzle
, 1),
1076 GET_SWZ(src
->Swizzle
, 2),
1077 GET_SWZ(src
->Swizzle
, 3));
1079 /* Note this is ok for non-swizzle instructions:
1081 reg
.negate
= src
->Negate
? 1 : 0;
1088 * Get brw register for the given program dest register.
1090 static struct brw_reg
get_dst( struct brw_vs_compile
*c
,
1091 struct prog_dst_register dst
)
1096 case PROGRAM_TEMPORARY
:
1097 case PROGRAM_OUTPUT
:
1098 assert(c
->regs
[dst
.File
][dst
.Index
].nr
!= 0);
1099 reg
= c
->regs
[dst
.File
][dst
.Index
];
1101 case PROGRAM_ADDRESS
:
1102 assert(dst
.Index
== 0);
1103 reg
= c
->regs
[dst
.File
][dst
.Index
];
1105 case PROGRAM_UNDEFINED
:
1106 /* we may hit this for OPCODE_END, OPCODE_KIL, etc */
1107 reg
= brw_null_reg();
1111 reg
= brw_null_reg();
1114 reg
.dw1
.bits
.writemask
= dst
.WriteMask
;
1120 static void emit_swz( struct brw_vs_compile
*c
,
1122 const struct prog_instruction
*inst
)
1124 const GLuint argIndex
= 0;
1125 const struct prog_src_register src
= inst
->SrcReg
[argIndex
];
1126 struct brw_compile
*p
= &c
->func
;
1127 GLuint zeros_mask
= 0;
1128 GLuint ones_mask
= 0;
1129 GLuint src_mask
= 0;
1131 GLboolean need_tmp
= (src
.Negate
&&
1132 dst
.file
!= BRW_GENERAL_REGISTER_FILE
);
1133 struct brw_reg tmp
= dst
;
1139 for (i
= 0; i
< 4; i
++) {
1140 if (dst
.dw1
.bits
.writemask
& (1<<i
)) {
1141 GLubyte s
= GET_SWZ(src
.Swizzle
, i
);
1160 /* Do src first, in case dst aliases src:
1163 struct brw_reg arg0
;
1165 arg0
= get_src_reg(c
, inst
, argIndex
);
1167 arg0
= brw_swizzle(arg0
,
1168 src_swz
[0], src_swz
[1],
1169 src_swz
[2], src_swz
[3]);
1171 brw_MOV(p
, brw_writemask(tmp
, src_mask
), arg0
);
1175 brw_MOV(p
, brw_writemask(tmp
, zeros_mask
), brw_imm_f(0));
1178 brw_MOV(p
, brw_writemask(tmp
, ones_mask
), brw_imm_f(1));
1181 brw_MOV(p
, brw_writemask(tmp
, src
.Negate
), negate(tmp
));
1184 brw_MOV(p
, dst
, tmp
);
1185 release_tmp(c
, tmp
);
1191 * Post-vertex-program processing. Send the results to the URB.
1193 static void emit_vertex_write( struct brw_vs_compile
*c
)
1195 struct brw_compile
*p
= &c
->func
;
1196 struct brw_context
*brw
= p
->brw
;
1197 struct intel_context
*intel
= &brw
->intel
;
1198 struct brw_reg m0
= brw_message_reg(0);
1199 struct brw_reg pos
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_HPOS
];
1202 GLuint len_vertex_header
= 2;
1204 if (c
->key
.copy_edgeflag
) {
1206 get_reg(c
, PROGRAM_OUTPUT
, VERT_RESULT_EDGE
),
1207 get_reg(c
, PROGRAM_INPUT
, VERT_ATTRIB_EDGEFLAG
));
1210 if (intel
->gen
< 6) {
1211 /* Build ndc coords */
1213 /* ndc = 1.0 / pos.w */
1214 emit_math1(c
, BRW_MATH_FUNCTION_INV
, ndc
, brw_swizzle1(pos
, 3), BRW_MATH_PRECISION_FULL
);
1215 /* ndc.xyz = pos * ndc */
1216 brw_MUL(p
, brw_writemask(ndc
, WRITEMASK_XYZ
), pos
, ndc
);
1219 /* Update the header for point size, user clipping flags, and -ve rhw
1222 if ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
1223 c
->key
.nr_userclip
|| brw
->has_negative_rhw_bug
)
1225 struct brw_reg header1
= retype(get_tmp(c
), BRW_REGISTER_TYPE_UD
);
1228 brw_MOV(p
, header1
, brw_imm_ud(0));
1230 brw_set_access_mode(p
, BRW_ALIGN_16
);
1232 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1233 struct brw_reg psiz
= c
->regs
[PROGRAM_OUTPUT
][VERT_RESULT_PSIZ
];
1234 brw_MUL(p
, brw_writemask(header1
, WRITEMASK_W
), brw_swizzle1(psiz
, 0), brw_imm_f(1<<11));
1235 brw_AND(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(0x7ff<<8));
1238 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1239 brw_set_conditionalmod(p
, BRW_CONDITIONAL_L
);
1240 brw_DP4(p
, brw_null_reg(), pos
, c
->userplane
[i
]);
1241 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<i
));
1242 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1245 /* i965 clipping workaround:
1246 * 1) Test for -ve rhw
1248 * set ndc = (0,0,0,0)
1251 * Later, clipping will detect ucp[6] and ensure the primitive is
1252 * clipped against all fixed planes.
1254 if (brw
->has_negative_rhw_bug
) {
1256 vec8(brw_null_reg()),
1258 brw_swizzle1(ndc
, 3),
1261 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1262 brw_MOV(p
, ndc
, brw_imm_f(0));
1263 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1266 brw_set_access_mode(p
, BRW_ALIGN_1
); /* why? */
1267 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), header1
);
1268 brw_set_access_mode(p
, BRW_ALIGN_16
);
1270 release_tmp(c
, header1
);
1273 brw_MOV(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
1276 /* Emit the (interleaved) headers for the two vertices - an 8-reg
1277 * of zeros followed by two sets of NDC coordinates:
1279 brw_set_access_mode(p
, BRW_ALIGN_1
);
1281 if (intel
->gen
>= 6) {
1282 /* There are 16 DWs (D0-D15) in VUE header on Sandybridge:
1283 * dword 0-3 (m1) of the header is indices, point width, clip flags.
1284 * dword 4-7 (m2) is the 4D space position
1285 * dword 8-15 (m3,m4) of the vertex header is the user clip distance.
1286 * m5 is the first vertex data we fill, which is the vertex position.
1288 brw_MOV(p
, offset(m0
, 2), pos
);
1289 brw_MOV(p
, offset(m0
, 5), pos
);
1290 len_vertex_header
= 4;
1291 } else if (intel
->is_ironlake
) {
1292 /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
1293 * dword 0-3 (m1) of the header is indices, point width, clip flags.
1294 * dword 4-7 (m2) is the ndc position (set above)
1295 * dword 8-11 (m3) of the vertex header is the 4D space position
1296 * dword 12-19 (m4,m5) of the vertex header is the user clip distance.
1297 * m6 is a pad so that the vertex element data is aligned
1298 * m7 is the first vertex data we fill, which is the vertex position.
1300 brw_MOV(p
, offset(m0
, 2), ndc
);
1301 brw_MOV(p
, offset(m0
, 3), pos
);
1302 brw_MOV(p
, offset(m0
, 7), pos
);
1303 len_vertex_header
= 6;
1305 /* There are 8 dwords in VUE header pre-Ironlake:
1306 * dword 0-3 (m1) is indices, point width, clip flags.
1307 * dword 4-7 (m2) is ndc position (set above)
1309 * dword 8-11 (m3) is the first vertex data, which we always have be the
1312 brw_MOV(p
, offset(m0
, 2), ndc
);
1313 brw_MOV(p
, offset(m0
, 3), pos
);
1314 len_vertex_header
= 2;
1317 eot
= (c
->first_overflow_output
== 0);
1320 brw_null_reg(), /* dest */
1321 0, /* starting mrf reg nr */
1325 MIN2(c
->nr_outputs
+ 1 + len_vertex_header
, (BRW_MAX_MRF
-1)), /* msg len */
1326 0, /* response len */
1328 eot
, /* writes complete */
1329 0, /* urb destination offset */
1330 BRW_URB_SWIZZLE_INTERLEAVE
);
1332 if (c
->first_overflow_output
> 0) {
1333 /* Not all of the vertex outputs/results fit into the MRF.
1334 * Move the overflowed attributes from the GRF to the MRF and
1335 * issue another brw_urb_WRITE().
1337 /* XXX I'm not 100% sure about which MRF regs to use here. Starting
1341 for (i
= c
->first_overflow_output
; i
< VERT_RESULT_MAX
; i
++) {
1342 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(i
)) {
1343 /* move from GRF to MRF */
1344 brw_MOV(p
, brw_message_reg(4+mrf
), c
->regs
[PROGRAM_OUTPUT
][i
]);
1350 brw_null_reg(), /* dest */
1351 4, /* starting mrf reg nr */
1355 mrf
+1, /* msg len */
1356 0, /* response len */
1358 1, /* writes complete */
1359 BRW_MAX_MRF
-1, /* urb destination offset */
1360 BRW_URB_SWIZZLE_INTERLEAVE
);
1365 accumulator_contains(struct brw_vs_compile
*c
, struct brw_reg val
)
1367 struct brw_compile
*p
= &c
->func
;
1368 struct brw_instruction
*prev_insn
= &p
->store
[p
->nr_insn
- 1];
1370 if (p
->nr_insn
== 0)
1373 if (val
.address_mode
!= BRW_ADDRESS_DIRECT
)
1376 switch (prev_insn
->header
.opcode
) {
1377 case BRW_OPCODE_MOV
:
1378 case BRW_OPCODE_MAC
:
1379 case BRW_OPCODE_MUL
:
1380 if (prev_insn
->header
.access_mode
== BRW_ALIGN_16
&&
1381 prev_insn
->header
.execution_size
== val
.width
&&
1382 prev_insn
->bits1
.da1
.dest_reg_file
== val
.file
&&
1383 prev_insn
->bits1
.da1
.dest_reg_type
== val
.type
&&
1384 prev_insn
->bits1
.da1
.dest_address_mode
== val
.address_mode
&&
1385 prev_insn
->bits1
.da1
.dest_reg_nr
== val
.nr
&&
1386 prev_insn
->bits1
.da16
.dest_subreg_nr
== val
.subnr
/ 16 &&
1387 prev_insn
->bits1
.da16
.dest_writemask
== 0xf)
1397 get_predicate(const struct prog_instruction
*inst
)
1399 if (inst
->DstReg
.CondMask
== COND_TR
)
1400 return BRW_PREDICATE_NONE
;
1402 /* All of GLSL only produces predicates for COND_NE and one channel per
1403 * vector. Fail badly if someone starts doing something else, as it might
1404 * mean infinite looping or something.
1406 * We'd like to support all the condition codes, but our hardware doesn't
1407 * quite match the Mesa IR, which is modeled after the NV extensions. For
1408 * those, the instruction may update the condition codes or not, then any
1409 * later instruction may use one of those condition codes. For gen4, the
1410 * instruction may update the flags register based on one of the condition
1411 * codes output by the instruction, and then further instructions may
1412 * predicate on that. We can probably support this, but it won't
1413 * necessarily be easy.
1415 assert(inst
->DstReg
.CondMask
== COND_NE
);
1417 switch (inst
->DstReg
.CondSwizzle
) {
1419 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1421 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1423 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1425 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1427 _mesa_problem(NULL
, "Unexpected predicate: 0x%08x\n",
1428 inst
->DstReg
.CondMask
);
1429 return BRW_PREDICATE_NORMAL
;
1433 /* Emit the vertex program instructions here.
1435 void brw_vs_emit(struct brw_vs_compile
*c
)
1437 #define MAX_IF_DEPTH 32
1438 #define MAX_LOOP_DEPTH 32
1439 struct brw_compile
*p
= &c
->func
;
1440 struct brw_context
*brw
= p
->brw
;
1441 struct intel_context
*intel
= &brw
->intel
;
1442 const GLuint nr_insns
= c
->vp
->program
.Base
.NumInstructions
;
1443 GLuint insn
, if_depth
= 0, loop_depth
= 0;
1444 struct brw_instruction
*if_inst
[MAX_IF_DEPTH
], *loop_inst
[MAX_LOOP_DEPTH
] = { 0 };
1445 const struct brw_indirect stack_index
= brw_indirect(0, 0);
1449 if (INTEL_DEBUG
& DEBUG_VS
) {
1450 printf("vs-mesa:\n");
1451 _mesa_print_program(&c
->vp
->program
.Base
);
1455 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1456 brw_set_access_mode(p
, BRW_ALIGN_16
);
1458 for (insn
= 0; insn
< nr_insns
; insn
++) {
1460 struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1462 /* Message registers can't be read, so copy the output into GRF
1463 * register if they are used in source registers
1465 for (i
= 0; i
< 3; i
++) {
1466 struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1467 GLuint index
= src
->Index
;
1468 GLuint file
= src
->File
;
1469 if (file
== PROGRAM_OUTPUT
&& index
!= VERT_RESULT_HPOS
)
1470 c
->output_regs
[index
].used_in_src
= GL_TRUE
;
1473 switch (inst
->Opcode
) {
1476 c
->needs_stack
= GL_TRUE
;
1483 /* Static register allocation
1485 brw_vs_alloc_regs(c
);
1488 brw_MOV(p
, get_addr_reg(stack_index
), brw_address(c
->stack
));
1490 for (insn
= 0; insn
< nr_insns
; insn
++) {
1492 const struct prog_instruction
*inst
= &c
->vp
->program
.Base
.Instructions
[insn
];
1493 struct brw_reg args
[3], dst
;
1497 printf("%d: ", insn
);
1498 _mesa_print_instruction(inst
);
1501 /* Get argument regs. SWZ is special and does this itself.
1503 if (inst
->Opcode
!= OPCODE_SWZ
)
1504 for (i
= 0; i
< 3; i
++) {
1505 const struct prog_src_register
*src
= &inst
->SrcReg
[i
];
1508 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1509 args
[i
] = c
->output_regs
[index
].reg
;
1511 args
[i
] = get_arg(c
, inst
, i
);
1514 /* Get dest regs. Note that it is possible for a reg to be both
1515 * dst and arg, given the static allocation of registers. So
1516 * care needs to be taken emitting multi-operation instructions.
1518 index
= inst
->DstReg
.Index
;
1519 file
= inst
->DstReg
.File
;
1520 if (file
== PROGRAM_OUTPUT
&& c
->output_regs
[index
].used_in_src
)
1521 dst
= c
->output_regs
[index
].reg
;
1523 dst
= get_dst(c
, inst
->DstReg
);
1525 if (inst
->SaturateMode
!= SATURATE_OFF
) {
1526 _mesa_problem(NULL
, "Unsupported saturate %d in vertex shader",
1527 inst
->SaturateMode
);
1530 switch (inst
->Opcode
) {
1532 brw_MOV(p
, dst
, brw_abs(args
[0]));
1535 brw_ADD(p
, dst
, args
[0], args
[1]);
1538 emit_math1(c
, BRW_MATH_FUNCTION_COS
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1541 brw_DP3(p
, dst
, args
[0], args
[1]);
1544 brw_DP4(p
, dst
, args
[0], args
[1]);
1547 brw_DPH(p
, dst
, args
[0], args
[1]);
1550 emit_nrm(c
, dst
, args
[0], 3);
1553 emit_nrm(c
, dst
, args
[0], 4);
1556 unalias2(c
, dst
, args
[0], args
[1], emit_dst_noalias
);
1559 unalias1(c
, dst
, args
[0], emit_exp_noalias
);
1562 emit_math1(c
, BRW_MATH_FUNCTION_EXP
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1565 emit_arl(c
, dst
, args
[0]);
1568 brw_RNDD(p
, dst
, args
[0]);
1571 brw_FRC(p
, dst
, args
[0]);
1574 unalias1(c
, dst
, args
[0], emit_log_noalias
);
1577 emit_math1(c
, BRW_MATH_FUNCTION_LOG
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1580 unalias1(c
, dst
, args
[0], emit_lit_noalias
);
1583 unalias3(c
, dst
, args
[0], args
[1], args
[2], emit_lrp_noalias
);
1586 if (!accumulator_contains(c
, args
[2]))
1587 brw_MOV(p
, brw_acc_reg(), args
[2]);
1588 brw_MAC(p
, dst
, args
[0], args
[1]);
1591 emit_cmp(p
, dst
, args
[0], args
[1], args
[2]);
1594 emit_max(p
, dst
, args
[0], args
[1]);
1597 emit_min(p
, dst
, args
[0], args
[1]);
1600 brw_MOV(p
, dst
, args
[0]);
1603 brw_MUL(p
, dst
, args
[0], args
[1]);
1606 emit_math2(c
, BRW_MATH_FUNCTION_POW
, dst
, args
[0], args
[1], BRW_MATH_PRECISION_FULL
);
1609 emit_math1(c
, BRW_MATH_FUNCTION_INV
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1612 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1616 unalias2(c
, dst
, args
[0], args
[1], emit_seq
);
1619 emit_math1(c
, BRW_MATH_FUNCTION_SIN
, dst
, args
[0], BRW_MATH_PRECISION_FULL
);
1622 unalias2(c
, dst
, args
[0], args
[1], emit_sne
);
1625 unalias2(c
, dst
, args
[0], args
[1], emit_sge
);
1628 unalias2(c
, dst
, args
[0], args
[1], emit_sgt
);
1631 unalias2(c
, dst
, args
[0], args
[1], emit_slt
);
1634 unalias2(c
, dst
, args
[0], args
[1], emit_sle
);
1637 brw_ADD(p
, dst
, args
[0], negate(args
[1]));
1640 /* The args[0] value can't be used here as it won't have
1641 * correctly encoded the full swizzle:
1643 emit_swz(c
, dst
, inst
);
1646 /* round toward zero */
1647 brw_RNDZ(p
, dst
, args
[0]);
1650 emit_xpd(p
, dst
, args
[0], args
[1]);
1653 assert(if_depth
< MAX_IF_DEPTH
);
1654 if_inst
[if_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1655 /* Note that brw_IF smashes the predicate_control field. */
1656 if_inst
[if_depth
]->header
.predicate_control
= get_predicate(inst
);
1660 if_inst
[if_depth
-1] = brw_ELSE(p
, if_inst
[if_depth
-1]);
1663 assert(if_depth
> 0);
1664 brw_ENDIF(p
, if_inst
[--if_depth
]);
1666 case OPCODE_BGNLOOP
:
1667 loop_inst
[loop_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
1670 brw_set_predicate_control(p
, get_predicate(inst
));
1672 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1675 brw_set_predicate_control(p
, get_predicate(inst
));
1677 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1679 case OPCODE_ENDLOOP
:
1681 struct brw_instruction
*inst0
, *inst1
;
1686 if (intel
->is_ironlake
)
1689 inst0
= inst1
= brw_WHILE(p
, loop_inst
[loop_depth
]);
1690 /* patch all the BREAK/CONT instructions from last BEGINLOOP */
1691 while (inst0
> loop_inst
[loop_depth
]) {
1693 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
1694 inst0
->bits3
.if_else
.jump_count
== 0) {
1695 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
1696 inst0
->bits3
.if_else
.pop_count
= 0;
1698 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
1699 inst0
->bits3
.if_else
.jump_count
== 0) {
1700 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
1701 inst0
->bits3
.if_else
.pop_count
= 0;
1707 brw_set_predicate_control(p
, get_predicate(inst
));
1708 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1709 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1712 brw_set_access_mode(p
, BRW_ALIGN_1
);
1713 brw_ADD(p
, deref_1d(stack_index
, 0), brw_ip_reg(), brw_imm_d(3*16));
1714 brw_set_access_mode(p
, BRW_ALIGN_16
);
1715 brw_ADD(p
, get_addr_reg(stack_index
),
1716 get_addr_reg(stack_index
), brw_imm_d(4));
1717 brw_save_call(p
, inst
->Comment
, p
->nr_insn
);
1718 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1721 brw_ADD(p
, get_addr_reg(stack_index
),
1722 get_addr_reg(stack_index
), brw_imm_d(-4));
1723 brw_set_access_mode(p
, BRW_ALIGN_1
);
1724 brw_MOV(p
, brw_ip_reg(), deref_1d(stack_index
, 0));
1725 brw_set_access_mode(p
, BRW_ALIGN_16
);
1728 emit_vertex_write(c
);
1734 brw_save_label(p
, inst
->Comment
, p
->nr_insn
);
1740 _mesa_problem(NULL
, "Unsupported opcode %i (%s) in vertex shader",
1741 inst
->Opcode
, inst
->Opcode
< MAX_OPCODE
?
1742 _mesa_opcode_string(inst
->Opcode
) :
1746 /* Set the predication update on the last instruction of the native
1747 * instruction sequence.
1749 * This would be problematic if it was set on a math instruction,
1750 * but that shouldn't be the case with the current GLSL compiler.
1752 if (inst
->CondUpdate
) {
1753 struct brw_instruction
*hw_insn
= &p
->store
[p
->nr_insn
- 1];
1755 assert(hw_insn
->header
.destreg__conditionalmod
== 0);
1756 hw_insn
->header
.destreg__conditionalmod
= BRW_CONDITIONAL_NZ
;
1759 if ((inst
->DstReg
.File
== PROGRAM_OUTPUT
)
1760 && (inst
->DstReg
.Index
!= VERT_RESULT_HPOS
)
1761 && c
->output_regs
[inst
->DstReg
.Index
].used_in_src
) {
1762 brw_MOV(p
, get_dst(c
, inst
->DstReg
), dst
);
1765 /* Result color clamping.
1767 * When destination register is an output register and
1768 * it's primary/secondary front/back color, we have to clamp
1769 * the result to [0,1]. This is done by enabling the
1770 * saturation bit for the last instruction.
1772 * We don't use brw_set_saturate() as it modifies
1773 * p->current->header.saturate, which affects all the subsequent
1774 * instructions. Instead, we directly modify the header
1775 * of the last (already stored) instruction.
1777 if (inst
->DstReg
.File
== PROGRAM_OUTPUT
) {
1778 if ((inst
->DstReg
.Index
== VERT_RESULT_COL0
)
1779 || (inst
->DstReg
.Index
== VERT_RESULT_COL1
)
1780 || (inst
->DstReg
.Index
== VERT_RESULT_BFC0
)
1781 || (inst
->DstReg
.Index
== VERT_RESULT_BFC1
)) {
1782 p
->store
[p
->nr_insn
-1].header
.saturate
= 1;
1789 brw_resolve_cals(p
);
1793 if (INTEL_DEBUG
& DEBUG_VS
) {
1796 printf("vs-native:\n");
1797 for (i
= 0; i
< p
->nr_insn
; i
++)
1798 brw_disasm(stderr
, &p
->store
[i
]);