radeon: add support for new ttm
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vs_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
37 #include "main/macros.h"
38
39 struct brw_vs_unit_key {
40 unsigned int total_grf;
41 unsigned int urb_entry_read_length;
42 unsigned int curb_entry_read_length;
43
44 unsigned int curbe_offset;
45
46 unsigned int nr_urb_entries, urb_size;
47 };
48
49 static void
50 vs_unit_populate_key(struct brw_context *brw, struct brw_vs_unit_key *key)
51 {
52 GLcontext *ctx = &brw->intel.ctx;
53
54 memset(key, 0, sizeof(*key));
55
56 /* CACHE_NEW_VS_PROG */
57 key->total_grf = brw->vs.prog_data->total_grf;
58 key->urb_entry_read_length = brw->vs.prog_data->urb_read_length;
59 key->curb_entry_read_length = brw->vs.prog_data->curb_read_length;
60
61 /* BRW_NEW_URB_FENCE */
62 key->nr_urb_entries = brw->urb.nr_vs_entries;
63 key->urb_size = brw->urb.vsize;
64
65 /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM */
66 if (ctx->Transform.ClipPlanesEnabled) {
67 /* Note that we read in the userclip planes as well, hence
68 * clip_start:
69 */
70 key->curbe_offset = brw->curbe.clip_start;
71 }
72 else {
73 key->curbe_offset = brw->curbe.vs_start;
74 }
75 }
76
77 static dri_bo *
78 vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
79 {
80 struct brw_vs_unit_state vs;
81 dri_bo *bo;
82 int chipset_max_threads;
83
84 memset(&vs, 0, sizeof(vs));
85
86 vs.thread0.kernel_start_pointer = brw->vs.prog_bo->offset >> 6; /* reloc */
87 vs.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
88 vs.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
89 /* Choosing multiple program flow means that we may get 2-vertex threads,
90 * which will have the channel mask for dwords 4-7 enabled in the thread,
91 * and those dwords will be written to the second URB handle when we
92 * brw_urb_WRITE() results.
93 */
94 vs.thread1.single_program_flow = 0;
95 vs.thread3.urb_entry_read_length = key->urb_entry_read_length;
96 vs.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
97 vs.thread3.dispatch_grf_start_reg = 1;
98 vs.thread3.urb_entry_read_offset = 0;
99 vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
100
101 vs.thread4.nr_urb_entries = key->nr_urb_entries;
102 vs.thread4.urb_entry_allocation_size = key->urb_size - 1;
103
104 if (BRW_IS_G4X(brw))
105 chipset_max_threads = 32;
106 else
107 chipset_max_threads = 16;
108 vs.thread4.max_threads = CLAMP(key->nr_urb_entries / 2,
109 1, chipset_max_threads) - 1;
110
111 if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
112 vs.thread4.max_threads = 0;
113
114 /* No samplers for ARB_vp programs:
115 */
116 vs.vs5.sampler_count = 0;
117
118 if (INTEL_DEBUG & DEBUG_STATS)
119 vs.thread4.stats_enable = 1;
120
121 /* Vertex program always enabled:
122 */
123 vs.vs6.vs_enable = 1;
124
125 bo = brw_upload_cache(&brw->cache, BRW_VS_UNIT,
126 key, sizeof(*key),
127 &brw->vs.prog_bo, 1,
128 &vs, sizeof(vs),
129 NULL, NULL);
130
131 /* Emit VS program relocation */
132 dri_bo_emit_reloc(bo,
133 I915_GEM_DOMAIN_INSTRUCTION, 0,
134 vs.thread0.grf_reg_count << 1,
135 offsetof(struct brw_vs_unit_state, thread0),
136 brw->vs.prog_bo);
137
138 return bo;
139 }
140
141 static void prepare_vs_unit(struct brw_context *brw)
142 {
143 struct brw_vs_unit_key key;
144
145 vs_unit_populate_key(brw, &key);
146
147 dri_bo_unreference(brw->vs.state_bo);
148 brw->vs.state_bo = brw_search_cache(&brw->cache, BRW_VS_UNIT,
149 &key, sizeof(key),
150 &brw->vs.prog_bo, 1,
151 NULL);
152 if (brw->vs.state_bo == NULL) {
153 brw->vs.state_bo = vs_unit_create_from_key(brw, &key);
154 }
155 }
156
157 const struct brw_tracked_state brw_vs_unit = {
158 .dirty = {
159 .mesa = _NEW_TRANSFORM,
160 .brw = (BRW_NEW_CURBE_OFFSETS |
161 BRW_NEW_URB_FENCE),
162 .cache = CACHE_NEW_VS_PROG
163 },
164 .prepare = prepare_vs_unit,
165 };