src/mesa/drivers/dri/i965/brw_vs_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "main/macros.h"
  38
  39 struct brw_vs_unit_key {
  40    unsigned int total_grf;
  41    unsigned int urb_entry_read_length;
  42    unsigned int curb_entry_read_length;
  43
  44    unsigned int curbe_offset;
  45
  46    unsigned int nr_urb_entries, urb_size;
  47
  48    unsigned int nr_surfaces;
  49 };
  50
  51 static void
  52 brw_prepare_vs_unit(struct brw_context *brw)
  53 {
  54    struct intel_context *intel = &brw->intel;
  55    struct gl_context *ctx = &intel->ctx;
  56    struct brw_vs_unit_state *vs;
  57
  58    vs = brw_state_batch(brw, sizeof(*vs), 32, &brw->vs.state_offset);
  59    memset(vs, 0, sizeof(*vs));
  60
  61    /* CACHE_NEW_VS_PROG */
  62    vs->thread0.kernel_start_pointer = brw->vs.prog_bo->offset >> 6; /* reloc */
  63    vs->thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1;
  64    vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  65    /* Choosing multiple program flow means that we may get 2-vertex threads,
  66     * which will have the channel mask for dwords 4-7 enabled in the thread,
  67     * and those dwords will be written to the second URB handle when we
  68     * brw_urb_WRITE() results.
  69     */
  70    /* Disable single program flow on Ironlake.  We cannot reliably get
  71     * all applications working without it.  See:
  72     * https://bugs.freedesktop.org/show_bug.cgi?id=29172
  73     *
  74     * The most notable and reliably failing application is the Humus
  75     * demo "CelShading"
  76    */
  77    vs->thread1.single_program_flow = (intel->gen == 5);
  78
  79    /* BRW_NEW_NR_VS_SURFACES */
  80    if (intel->gen == 5)
  81       vs->thread1.binding_table_entry_count = 0; /* hardware requirement */
  82    else
  83       vs->thread1.binding_table_entry_count = brw->vs.nr_surfaces;
  84
  85    vs->thread3.urb_entry_read_length = brw->vs.prog_data->urb_read_length;
  86    vs->thread3.const_urb_entry_read_length = brw->vs.prog_data->curb_read_length;
  87    vs->thread3.dispatch_grf_start_reg = 1;
  88    vs->thread3.urb_entry_read_offset = 0;
  89
  90    /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM */
  91    if (ctx->Transform.ClipPlanesEnabled) {
  92       /* Note that we read in the userclip planes as well, hence
  93        * clip_start:
  94        */
  95       vs->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
  96    }
  97    else {
  98       vs->thread3.const_urb_entry_read_offset = brw->curbe.vs_start * 2;
  99    }
 100
 101
 102    /* BRW_NEW_URB_FENCE */
 103    if (intel->gen == 5) {
 104       switch (brw->urb.nr_vs_entries) {
 105       case 8:
 106       case 12:
 107       case 16:
 108       case 32:
 109       case 64:
 110       case 96:
 111       case 128:
 112       case 168:
 113       case 192:
 114       case 224:
 115       case 256:
 116          vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries >> 2;
 117          break;
 118       default:
 119          assert(0);
 120       }
 121    } else {
 122       switch (brw->urb.nr_vs_entries) {
 123       case 8:
 124       case 12:
 125       case 16:
 126       case 32:
 127          break;
 128       case 64:
 129          assert(intel->is_g4x);
 130          break;
 131       default:
 132          assert(0);
 133       }
 134       vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries;
 135    }
 136
 137    vs->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
 138
 139    vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
 140                                    1, brw->vs_max_threads) - 1;
 141
 142    /* No samplers for ARB_vp programs:
 143     */
 144    /* It has to be set to 0 for Ironlake
 145     */
 146    vs->vs5.sampler_count = 0;
 147
 148    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 149       vs->thread4.stats_enable = 1;
 150
 151    /* Vertex program always enabled:
 152     */
 153    vs->vs6.vs_enable = 1;
 154
 155    /* Emit VS program relocation */
 156    drm_intel_bo_emit_reloc(intel->batch.bo, (brw->vs.state_offset +
 157                                              offsetof(struct brw_vs_unit_state,
 158                                                       thread0)),
 159                            brw->vs.prog_bo, vs->thread0.grf_reg_count << 1,
 160                            I915_GEM_DOMAIN_INSTRUCTION, 0);
 161
 162    brw->state.dirty.cache |= CACHE_NEW_VS_UNIT;
 163 }
 164
 165 const struct brw_tracked_state brw_vs_unit = {
 166    .dirty = {
 167       .mesa  = _NEW_TRANSFORM,
 168       .brw   = (BRW_NEW_BATCH |
 169                 BRW_NEW_CURBE_OFFSETS |
 170                 BRW_NEW_NR_VS_SURFACES |
 171                 BRW_NEW_URB_FENCE),
 172       .cache = CACHE_NEW_VS_PROG
 173    },
 174    .prepare = brw_prepare_vs_unit,
 175 };