i965: defined BRW_MAX_MRF
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vs_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
37 #include "main/macros.h"
38
39 struct brw_vs_unit_key {
40 unsigned int total_grf;
41 unsigned int urb_entry_read_length;
42 unsigned int curb_entry_read_length;
43
44 unsigned int curbe_offset;
45
46 unsigned int nr_urb_entries, urb_size;
47
48 unsigned int nr_surfaces;
49 };
50
51 static void
52 vs_unit_populate_key(struct brw_context *brw, struct brw_vs_unit_key *key)
53 {
54 GLcontext *ctx = &brw->intel.ctx;
55
56 memset(key, 0, sizeof(*key));
57
58 /* CACHE_NEW_VS_PROG */
59 key->total_grf = brw->vs.prog_data->total_grf;
60 key->urb_entry_read_length = brw->vs.prog_data->urb_read_length;
61 key->curb_entry_read_length = brw->vs.prog_data->curb_read_length;
62
63 /* BRW_NEW_URB_FENCE */
64 key->nr_urb_entries = brw->urb.nr_vs_entries;
65 key->urb_size = brw->urb.vsize;
66
67 /* BRW_NEW_NR_VS_SURFACES */
68 key->nr_surfaces = brw->vs.nr_surfaces;
69
70 /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM */
71 if (ctx->Transform.ClipPlanesEnabled) {
72 /* Note that we read in the userclip planes as well, hence
73 * clip_start:
74 */
75 key->curbe_offset = brw->curbe.clip_start;
76 }
77 else {
78 key->curbe_offset = brw->curbe.vs_start;
79 }
80 }
81
82 static dri_bo *
83 vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
84 {
85 struct brw_vs_unit_state vs;
86 dri_bo *bo;
87 int chipset_max_threads;
88
89 memset(&vs, 0, sizeof(vs));
90
91 vs.thread0.kernel_start_pointer = brw->vs.prog_bo->offset >> 6; /* reloc */
92 vs.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
93 vs.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
94 /* Choosing multiple program flow means that we may get 2-vertex threads,
95 * which will have the channel mask for dwords 4-7 enabled in the thread,
96 * and those dwords will be written to the second URB handle when we
97 * brw_urb_WRITE() results.
98 */
99 vs.thread1.single_program_flow = 0;
100 vs.thread1.binding_table_entry_count = key->nr_surfaces;
101
102 vs.thread3.urb_entry_read_length = key->urb_entry_read_length;
103 vs.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
104 vs.thread3.dispatch_grf_start_reg = 1;
105 vs.thread3.urb_entry_read_offset = 0;
106 vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
107
108 vs.thread4.nr_urb_entries = key->nr_urb_entries;
109 vs.thread4.urb_entry_allocation_size = key->urb_size - 1;
110
111 if (BRW_IS_G4X(brw))
112 chipset_max_threads = 32;
113 else
114 chipset_max_threads = 16;
115 vs.thread4.max_threads = CLAMP(key->nr_urb_entries / 2,
116 1, chipset_max_threads) - 1;
117
118 if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
119 vs.thread4.max_threads = 0;
120
121 /* No samplers for ARB_vp programs:
122 */
123 vs.vs5.sampler_count = 0;
124
125 if (INTEL_DEBUG & DEBUG_STATS)
126 vs.thread4.stats_enable = 1;
127
128 /* Vertex program always enabled:
129 */
130 vs.vs6.vs_enable = 1;
131
132 bo = brw_upload_cache(&brw->cache, BRW_VS_UNIT,
133 key, sizeof(*key),
134 &brw->vs.prog_bo, 1,
135 &vs, sizeof(vs),
136 NULL, NULL);
137
138 /* Emit VS program relocation */
139 dri_bo_emit_reloc(bo,
140 I915_GEM_DOMAIN_INSTRUCTION, 0,
141 vs.thread0.grf_reg_count << 1,
142 offsetof(struct brw_vs_unit_state, thread0),
143 brw->vs.prog_bo);
144
145 return bo;
146 }
147
148 static void prepare_vs_unit(struct brw_context *brw)
149 {
150 struct brw_vs_unit_key key;
151
152 vs_unit_populate_key(brw, &key);
153
154 dri_bo_unreference(brw->vs.state_bo);
155 brw->vs.state_bo = brw_search_cache(&brw->cache, BRW_VS_UNIT,
156 &key, sizeof(key),
157 &brw->vs.prog_bo, 1,
158 NULL);
159 if (brw->vs.state_bo == NULL) {
160 brw->vs.state_bo = vs_unit_create_from_key(brw, &key);
161 }
162 }
163
164 const struct brw_tracked_state brw_vs_unit = {
165 .dirty = {
166 .mesa = _NEW_TRANSFORM,
167 .brw = (BRW_NEW_CURBE_OFFSETS |
168 BRW_NEW_NR_VS_SURFACES |
169 BRW_NEW_URB_FENCE),
170 .cache = CACHE_NEW_VS_PROG
171 },
172 .prepare = prepare_vs_unit,
173 };