src/mesa/drivers/dri/i965/brw_vs_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "main/macros.h"
  38
  39 static void
  40 brw_prepare_vs_unit(struct brw_context *brw)
  41 {
  42    struct intel_context *intel = &brw->intel;
  43    struct gl_context *ctx = &intel->ctx;
  44    struct brw_vs_unit_state *vs;
  45
  46    vs = brw_state_batch(brw, AUB_TRACE_VS_STATE,
  47                         sizeof(*vs), 32, &brw->vs.state_offset);
  48    memset(vs, 0, sizeof(*vs));
  49
  50    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_VS_PROG */
  51    vs->thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1;
  52    vs->thread0.kernel_start_pointer =
  53       brw_program_reloc(brw,
  54                         brw->vs.state_offset +
  55                         offsetof(struct brw_vs_unit_state, thread0),
  56                         brw->vs.prog_offset +
  57                         (vs->thread0.grf_reg_count << 1)) >> 6;
  58
  59    vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  60    /* Choosing multiple program flow means that we may get 2-vertex threads,
  61     * which will have the channel mask for dwords 4-7 enabled in the thread,
  62     * and those dwords will be written to the second URB handle when we
  63     * brw_urb_WRITE() results.
  64     */
  65    /* Disable single program flow on Ironlake.  We cannot reliably get
  66     * all applications working without it.  See:
  67     * https://bugs.freedesktop.org/show_bug.cgi?id=29172
  68     *
  69     * The most notable and reliably failing application is the Humus
  70     * demo "CelShading"
  71    */
  72    vs->thread1.single_program_flow = (intel->gen == 5);
  73
  74    /* BRW_NEW_NR_VS_SURFACES */
  75    if (intel->gen == 5)
  76       vs->thread1.binding_table_entry_count = 0; /* hardware requirement */
  77    else
  78       vs->thread1.binding_table_entry_count = brw->vs.nr_surfaces;
  79
  80    if (brw->vs.prog_data->total_scratch != 0) {
  81       vs->thread2.scratch_space_base_pointer =
  82          brw->vs.scratch_bo->offset >> 10; /* reloc */
  83       vs->thread2.per_thread_scratch_space =
  84          ffs(brw->vs.prog_data->total_scratch) - 11;
  85    } else {
  86       vs->thread2.scratch_space_base_pointer = 0;
  87       vs->thread2.per_thread_scratch_space = 0;
  88    }
  89
  90    vs->thread3.urb_entry_read_length = brw->vs.prog_data->urb_read_length;
  91    vs->thread3.const_urb_entry_read_length = brw->vs.prog_data->curb_read_length;
  92    vs->thread3.dispatch_grf_start_reg = 1;
  93    vs->thread3.urb_entry_read_offset = 0;
  94
  95    /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM */
  96    if (ctx->Transform.ClipPlanesEnabled) {
  97       /* Note that we read in the userclip planes as well, hence
  98        * clip_start:
  99        */
 100       vs->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
 101    }
 102    else {
 103       vs->thread3.const_urb_entry_read_offset = brw->curbe.vs_start * 2;
 104    }
 105
 106
 107    /* BRW_NEW_URB_FENCE */
 108    if (intel->gen == 5) {
 109       switch (brw->urb.nr_vs_entries) {
 110       case 8:
 111       case 12:
 112       case 16:
 113       case 32:
 114       case 64:
 115       case 96:
 116       case 128:
 117       case 168:
 118       case 192:
 119       case 224:
 120       case 256:
 121          vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries >> 2;
 122          break;
 123       default:
 124          assert(0);
 125       }
 126    } else {
 127       switch (brw->urb.nr_vs_entries) {
 128       case 8:
 129       case 12:
 130       case 16:
 131       case 32:
 132          break;
 133       case 64:
 134          assert(intel->is_g4x);
 135          break;
 136       default:
 137          assert(0);
 138       }
 139       vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries;
 140    }
 141
 142    vs->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
 143
 144    vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
 145                                    1, brw->vs_max_threads) - 1;
 146
 147    /* No samplers for ARB_vp programs:
 148     */
 149    /* It has to be set to 0 for Ironlake
 150     */
 151    vs->vs5.sampler_count = 0;
 152
 153    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 154       vs->thread4.stats_enable = 1;
 155
 156    /* Vertex program always enabled:
 157     */
 158    vs->vs6.vs_enable = 1;
 159
 160    /* Emit scratch space relocation */
 161    if (brw->vs.prog_data->total_scratch != 0) {
 162       drm_intel_bo_emit_reloc(intel->batch.bo,
 163                               brw->vs.state_offset +
 164                               offsetof(struct brw_vs_unit_state, thread2),
 165                               brw->vs.scratch_bo,
 166                               vs->thread2.per_thread_scratch_space,
 167                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 168    }
 169
 170    brw->state.dirty.cache |= CACHE_NEW_VS_UNIT;
 171 }
 172
 173 const struct brw_tracked_state brw_vs_unit = {
 174    .dirty = {
 175       .mesa  = _NEW_TRANSFORM,
 176       .brw   = (BRW_NEW_BATCH |
 177                 BRW_NEW_PROGRAM_CACHE |
 178                 BRW_NEW_CURBE_OFFSETS |
 179                 BRW_NEW_NR_VS_SURFACES |
 180                 BRW_NEW_URB_FENCE),
 181       .cache = CACHE_NEW_VS_PROG
 182    },
 183    .prepare = brw_prepare_vs_unit,
 184 };