src/mesa/drivers/dri/i965/brw_vs_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "main/macros.h"
  38
  39 static void
  40 brw_upload_vs_unit(struct brw_context *brw)
  41 {
  42    struct brw_stage_state *stage_state = &brw->vs.base;
  43
  44    struct brw_vs_unit_state *vs;
  45
  46    vs = brw_state_batch(brw, AUB_TRACE_VS_STATE,
  47                         sizeof(*vs), 32, &stage_state->state_offset);
  48    memset(vs, 0, sizeof(*vs));
  49
  50    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_VS_PROG_DATA */
  51    vs->thread0.grf_reg_count =
  52       ALIGN(brw->vs.prog_data->base.total_grf, 16) / 16 - 1;
  53    vs->thread0.kernel_start_pointer =
  54       brw_program_reloc(brw,
  55                         stage_state->state_offset +
  56                         offsetof(struct brw_vs_unit_state, thread0),
  57                         stage_state->prog_offset +
  58                         (vs->thread0.grf_reg_count << 1)) >> 6;
  59
  60    if (brw->vs.prog_data->base.base.use_alt_mode)
  61       vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  62    else
  63       vs->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
  64
  65    /* Choosing multiple program flow means that we may get 2-vertex threads,
  66     * which will have the channel mask for dwords 4-7 enabled in the thread,
  67     * and those dwords will be written to the second URB handle when we
  68     * brw_urb_WRITE() results.
  69     */
  70    /* Force single program flow on Ironlake.  We cannot reliably get
  71     * all applications working without it.  See:
  72     * https://bugs.freedesktop.org/show_bug.cgi?id=29172
  73     *
  74     * The most notable and reliably failing application is the Humus
  75     * demo "CelShading"
  76    */
  77    vs->thread1.single_program_flow = (brw->gen == 5);
  78
  79    vs->thread1.binding_table_entry_count =
  80       brw->vs.prog_data->base.base.binding_table.size_bytes / 4;
  81
  82    if (brw->vs.prog_data->base.base.total_scratch != 0) {
  83       vs->thread2.scratch_space_base_pointer =
  84          stage_state->scratch_bo->offset64 >> 10; /* reloc */
  85       vs->thread2.per_thread_scratch_space =
  86          ffs(brw->vs.prog_data->base.base.total_scratch) - 11;
  87    } else {
  88       vs->thread2.scratch_space_base_pointer = 0;
  89       vs->thread2.per_thread_scratch_space = 0;
  90    }
  91
  92    vs->thread3.urb_entry_read_length = brw->vs.prog_data->base.urb_read_length;
  93    vs->thread3.const_urb_entry_read_length
  94       = brw->vs.prog_data->base.base.curb_read_length;
  95    vs->thread3.dispatch_grf_start_reg =
  96       brw->vs.prog_data->base.base.dispatch_grf_start_reg;
  97    vs->thread3.urb_entry_read_offset = 0;
  98
  99    /* BRW_NEW_CURBE_OFFSETS */
 100    vs->thread3.const_urb_entry_read_offset = brw->curbe.vs_start * 2;
 101
 102    /* BRW_NEW_URB_FENCE */
 103    if (brw->gen == 5) {
 104       switch (brw->urb.nr_vs_entries) {
 105       case 8:
 106       case 12:
 107       case 16:
 108       case 32:
 109       case 64:
 110       case 96:
 111       case 128:
 112       case 168:
 113       case 192:
 114       case 224:
 115       case 256:
 116          vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries >> 2;
 117          break;
 118       default:
 119          unreachable("not reached");
 120       }
 121    } else {
 122       switch (brw->urb.nr_vs_entries) {
 123       case 8:
 124       case 12:
 125       case 16:
 126       case 32:
 127          break;
 128       case 64:
 129          assert(brw->is_g4x);
 130          break;
 131       default:
 132          unreachable("not reached");
 133       }
 134       vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries;
 135    }
 136
 137    vs->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
 138
 139    vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
 140                                    1, brw->max_vs_threads) - 1;
 141
 142    if (brw->gen == 5)
 143       vs->vs5.sampler_count = 0; /* hardware requirement */
 144    else {
 145       vs->vs5.sampler_count = (stage_state->sampler_count + 3) / 4;
 146    }
 147
 148
 149    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 150       vs->thread4.stats_enable = 1;
 151
 152    /* Vertex program always enabled:
 153     */
 154    vs->vs6.vs_enable = 1;
 155
 156    /* Set the sampler state pointer, and its reloc
 157     */
 158    if (stage_state->sampler_count) {
 159       /* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
 160       vs->vs5.sampler_state_pointer =
 161          (brw->batch.bo->offset64 + stage_state->sampler_offset) >> 5;
 162       drm_intel_bo_emit_reloc(brw->batch.bo,
 163                               stage_state->state_offset +
 164                               offsetof(struct brw_vs_unit_state, vs5),
 165                               brw->batch.bo,
 166                               (stage_state->sampler_offset |
 167                                vs->vs5.sampler_count),
 168                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 169    }
 170
 171    /* Emit scratch space relocation */
 172    if (brw->vs.prog_data->base.base.total_scratch != 0) {
 173       drm_intel_bo_emit_reloc(brw->batch.bo,
 174                               stage_state->state_offset +
 175                               offsetof(struct brw_vs_unit_state, thread2),
 176                               stage_state->scratch_bo,
 177                               vs->thread2.per_thread_scratch_space,
 178                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 179    }
 180
 181    brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 182 }
 183
 184 const struct brw_tracked_state brw_vs_unit = {
 185    .dirty = {
 186       .mesa  = 0,
 187       .brw   = BRW_NEW_BATCH |
 188                BRW_NEW_CURBE_OFFSETS |
 189                BRW_NEW_PROGRAM_CACHE |
 190                BRW_NEW_SAMPLER_STATE_TABLE |
 191                BRW_NEW_URB_FENCE |
 192                BRW_NEW_VS_PROG_DATA,
 193    },
 194    .emit = brw_upload_vs_unit,
 195 };