src/mesa/drivers/dri/i965/brw_vs_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "main/macros.h"
  38
  39 static void
  40 brw_upload_vs_unit(struct brw_context *brw)
  41 {
  42    struct intel_context *intel = &brw->intel;
  43    struct brw_vs_unit_state *vs;
  44
  45    vs = brw_state_batch(brw, AUB_TRACE_VS_STATE,
  46                         sizeof(*vs), 32, &brw->vs.state_offset);
  47    memset(vs, 0, sizeof(*vs));
  48
  49    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_VS_PROG */
  50    vs->thread0.grf_reg_count =
  51       ALIGN(brw->vs.prog_data->base.total_grf, 16) / 16 - 1;
  52    vs->thread0.kernel_start_pointer =
  53       brw_program_reloc(brw,
  54                         brw->vs.state_offset +
  55                         offsetof(struct brw_vs_unit_state, thread0),
  56                         brw->vs.prog_offset +
  57                         (vs->thread0.grf_reg_count << 1)) >> 6;
  58
  59    vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  60    /* Choosing multiple program flow means that we may get 2-vertex threads,
  61     * which will have the channel mask for dwords 4-7 enabled in the thread,
  62     * and those dwords will be written to the second URB handle when we
  63     * brw_urb_WRITE() results.
  64     */
  65    /* Force single program flow on Ironlake.  We cannot reliably get
  66     * all applications working without it.  See:
  67     * https://bugs.freedesktop.org/show_bug.cgi?id=29172
  68     *
  69     * The most notable and reliably failing application is the Humus
  70     * demo "CelShading"
  71    */
  72    vs->thread1.single_program_flow = (intel->gen == 5);
  73
  74    vs->thread1.binding_table_entry_count = 0;
  75
  76    if (brw->vs.prog_data->base.total_scratch != 0) {
  77       vs->thread2.scratch_space_base_pointer =
  78          brw->vs.scratch_bo->offset >> 10; /* reloc */
  79       vs->thread2.per_thread_scratch_space =
  80          ffs(brw->vs.prog_data->base.total_scratch) - 11;
  81    } else {
  82       vs->thread2.scratch_space_base_pointer = 0;
  83       vs->thread2.per_thread_scratch_space = 0;
  84    }
  85
  86    vs->thread3.urb_entry_read_length = brw->vs.prog_data->base.urb_read_length;
  87    vs->thread3.const_urb_entry_read_length
  88       = brw->vs.prog_data->base.curb_read_length;
  89    vs->thread3.dispatch_grf_start_reg = 1;
  90    vs->thread3.urb_entry_read_offset = 0;
  91
  92    /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM, BRW_NEW_VERTEX_PROGRAM */
  93    vs->thread3.const_urb_entry_read_offset = brw->curbe.vs_start * 2;
  94
  95    /* BRW_NEW_URB_FENCE */
  96    if (intel->gen == 5) {
  97       switch (brw->urb.nr_vs_entries) {
  98       case 8:
  99       case 12:
 100       case 16:
 101       case 32:
 102       case 64:
 103       case 96:
 104       case 128:
 105       case 168:
 106       case 192:
 107       case 224:
 108       case 256:
 109          vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries >> 2;
 110          break;
 111       default:
 112          assert(0);
 113       }
 114    } else {
 115       switch (brw->urb.nr_vs_entries) {
 116       case 8:
 117       case 12:
 118       case 16:
 119       case 32:
 120          break;
 121       case 64:
 122          assert(intel->is_g4x);
 123          break;
 124       default:
 125          assert(0);
 126       }
 127       vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries;
 128    }
 129
 130    vs->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
 131
 132    vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
 133                                    1, brw->max_vs_threads) - 1;
 134
 135    /* No samplers for ARB_vp programs:
 136     */
 137    /* It has to be set to 0 for Ironlake
 138     */
 139    vs->vs5.sampler_count = 0;
 140
 141    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 142       vs->thread4.stats_enable = 1;
 143
 144    /* Vertex program always enabled:
 145     */
 146    vs->vs6.vs_enable = 1;
 147
 148    /* Emit scratch space relocation */
 149    if (brw->vs.prog_data->base.total_scratch != 0) {
 150       drm_intel_bo_emit_reloc(intel->batch.bo,
 151                               brw->vs.state_offset +
 152                               offsetof(struct brw_vs_unit_state, thread2),
 153                               brw->vs.scratch_bo,
 154                               vs->thread2.per_thread_scratch_space,
 155                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 156    }
 157
 158    brw->state.dirty.cache |= CACHE_NEW_VS_UNIT;
 159 }
 160
 161 const struct brw_tracked_state brw_vs_unit = {
 162    .dirty = {
 163       .mesa  = _NEW_TRANSFORM,
 164       .brw   = (BRW_NEW_BATCH |
 165                 BRW_NEW_PROGRAM_CACHE |
 166                 BRW_NEW_CURBE_OFFSETS |
 167                 BRW_NEW_URB_FENCE |
 168                 BRW_NEW_VERTEX_PROGRAM),
 169       .cache = CACHE_NEW_VS_PROG
 170    },
 171    .emit = brw_upload_vs_unit,
 172 };