src/mesa/drivers/dri/i965/brw_vs_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "main/macros.h"
  38
  39 static void
  40 brw_upload_vs_unit(struct brw_context *brw)
  41 {
  42    struct brw_stage_state *stage_state = &brw->vs.base;
  43
  44    struct brw_vs_unit_state *vs;
  45
  46    vs = brw_state_batch(brw, AUB_TRACE_VS_STATE,
  47                         sizeof(*vs), 32, &stage_state->state_offset);
  48    memset(vs, 0, sizeof(*vs));
  49
  50    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_VS_PROG */
  51    vs->thread0.grf_reg_count =
  52       ALIGN(brw->vs.prog_data->base.total_grf, 16) / 16 - 1;
  53    vs->thread0.kernel_start_pointer =
  54       brw_program_reloc(brw,
  55                         stage_state->state_offset +
  56                         offsetof(struct brw_vs_unit_state, thread0),
  57                         stage_state->prog_offset +
  58                         (vs->thread0.grf_reg_count << 1)) >> 6;
  59
  60    /* Use ALT floating point mode for ARB vertex programs, because they
  61     * require 0^0 == 1.
  62     */
  63    if (brw->ctx.Shader.CurrentVertexProgram == NULL)
  64       vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  65    else
  66       vs->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
  67
  68    /* Choosing multiple program flow means that we may get 2-vertex threads,
  69     * which will have the channel mask for dwords 4-7 enabled in the thread,
  70     * and those dwords will be written to the second URB handle when we
  71     * brw_urb_WRITE() results.
  72     */
  73    /* Force single program flow on Ironlake.  We cannot reliably get
  74     * all applications working without it.  See:
  75     * https://bugs.freedesktop.org/show_bug.cgi?id=29172
  76     *
  77     * The most notable and reliably failing application is the Humus
  78     * demo "CelShading"
  79    */
  80    vs->thread1.single_program_flow = (brw->gen == 5);
  81
  82    vs->thread1.binding_table_entry_count = 0;
  83
  84    if (brw->vs.prog_data->base.total_scratch != 0) {
  85       vs->thread2.scratch_space_base_pointer =
  86          stage_state->scratch_bo->offset >> 10; /* reloc */
  87       vs->thread2.per_thread_scratch_space =
  88          ffs(brw->vs.prog_data->base.total_scratch) - 11;
  89    } else {
  90       vs->thread2.scratch_space_base_pointer = 0;
  91       vs->thread2.per_thread_scratch_space = 0;
  92    }
  93
  94    vs->thread3.urb_entry_read_length = brw->vs.prog_data->base.urb_read_length;
  95    vs->thread3.const_urb_entry_read_length
  96       = brw->vs.prog_data->base.curb_read_length;
  97    vs->thread3.dispatch_grf_start_reg =
  98       brw->vs.prog_data->base.dispatch_grf_start_reg;
  99    vs->thread3.urb_entry_read_offset = 0;
 100
 101    /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM, BRW_NEW_VERTEX_PROGRAM */
 102    vs->thread3.const_urb_entry_read_offset = brw->curbe.vs_start * 2;
 103
 104    /* BRW_NEW_URB_FENCE */
 105    if (brw->gen == 5) {
 106       switch (brw->urb.nr_vs_entries) {
 107       case 8:
 108       case 12:
 109       case 16:
 110       case 32:
 111       case 64:
 112       case 96:
 113       case 128:
 114       case 168:
 115       case 192:
 116       case 224:
 117       case 256:
 118          vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries >> 2;
 119          break;
 120       default:
 121          assert(0);
 122       }
 123    } else {
 124       switch (brw->urb.nr_vs_entries) {
 125       case 8:
 126       case 12:
 127       case 16:
 128       case 32:
 129          break;
 130       case 64:
 131          assert(brw->is_g4x);
 132          break;
 133       default:
 134          assert(0);
 135       }
 136       vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries;
 137    }
 138
 139    vs->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
 140
 141    vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
 142                                    1, brw->max_vs_threads) - 1;
 143
 144    if (brw->gen == 5)
 145       vs->vs5.sampler_count = 0; /* hardware requirement */
 146    else {
 147       /* CACHE_NEW_SAMPLER */
 148       vs->vs5.sampler_count = (stage_state->sampler_count + 3) / 4;
 149    }
 150
 151
 152    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 153       vs->thread4.stats_enable = 1;
 154
 155    /* Vertex program always enabled:
 156     */
 157    vs->vs6.vs_enable = 1;
 158
 159    /* Set the sampler state pointer, and its reloc
 160     */
 161    if (stage_state->sampler_count) {
 162       vs->vs5.sampler_state_pointer =
 163          (brw->batch.bo->offset + stage_state->sampler_offset) >> 5;
 164       drm_intel_bo_emit_reloc(brw->batch.bo,
 165                               stage_state->state_offset +
 166                               offsetof(struct brw_vs_unit_state, vs5),
 167                               brw->batch.bo,
 168                               (stage_state->sampler_offset |
 169                                vs->vs5.sampler_count),
 170                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 171    }
 172
 173    /* Emit scratch space relocation */
 174    if (brw->vs.prog_data->base.total_scratch != 0) {
 175       drm_intel_bo_emit_reloc(brw->batch.bo,
 176                               stage_state->state_offset +
 177                               offsetof(struct brw_vs_unit_state, thread2),
 178                               stage_state->scratch_bo,
 179                               vs->thread2.per_thread_scratch_space,
 180                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 181    }
 182
 183    brw->state.dirty.cache |= CACHE_NEW_VS_UNIT;
 184 }
 185
 186 const struct brw_tracked_state brw_vs_unit = {
 187    .dirty = {
 188       .mesa  = _NEW_TRANSFORM,
 189       .brw   = (BRW_NEW_BATCH |
 190                 BRW_NEW_PROGRAM_CACHE |
 191                 BRW_NEW_CURBE_OFFSETS |
 192                 BRW_NEW_URB_FENCE |
 193                 BRW_NEW_VERTEX_PROGRAM),
 194       .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
 195    },
 196    .emit = brw_upload_vs_unit,
 197 };