src/mesa/drivers/dri/i965/brw_vs_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "main/macros.h"
  38
  39 static void
  40 brw_prepare_vs_unit(struct brw_context *brw)
  41 {
  42    struct intel_context *intel = &brw->intel;
  43    struct gl_context *ctx = &intel->ctx;
  44    struct brw_vs_unit_state *vs;
  45
  46    vs = brw_state_batch(brw, sizeof(*vs), 32, &brw->vs.state_offset);
  47    memset(vs, 0, sizeof(*vs));
  48
  49    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_VS_PROG */
  50    vs->thread0.kernel_start_pointer =
  51       brw_program_reloc(brw,
  52                         brw->vs.state_offset +
  53                         offsetof(struct brw_vs_unit_state, thread0),
  54                         brw->vs.prog_offset +
  55                         (vs->thread0.grf_reg_count << 1)) >> 6;
  56
  57    vs->thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1;
  58    vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  59    /* Choosing multiple program flow means that we may get 2-vertex threads,
  60     * which will have the channel mask for dwords 4-7 enabled in the thread,
  61     * and those dwords will be written to the second URB handle when we
  62     * brw_urb_WRITE() results.
  63     */
  64    /* Disable single program flow on Ironlake.  We cannot reliably get
  65     * all applications working without it.  See:
  66     * https://bugs.freedesktop.org/show_bug.cgi?id=29172
  67     *
  68     * The most notable and reliably failing application is the Humus
  69     * demo "CelShading"
  70    */
  71    vs->thread1.single_program_flow = (intel->gen == 5);
  72
  73    /* BRW_NEW_NR_VS_SURFACES */
  74    if (intel->gen == 5)
  75       vs->thread1.binding_table_entry_count = 0; /* hardware requirement */
  76    else
  77       vs->thread1.binding_table_entry_count = brw->vs.nr_surfaces;
  78
  79    vs->thread3.urb_entry_read_length = brw->vs.prog_data->urb_read_length;
  80    vs->thread3.const_urb_entry_read_length = brw->vs.prog_data->curb_read_length;
  81    vs->thread3.dispatch_grf_start_reg = 1;
  82    vs->thread3.urb_entry_read_offset = 0;
  83
  84    /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM */
  85    if (ctx->Transform.ClipPlanesEnabled) {
  86       /* Note that we read in the userclip planes as well, hence
  87        * clip_start:
  88        */
  89       vs->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
  90    }
  91    else {
  92       vs->thread3.const_urb_entry_read_offset = brw->curbe.vs_start * 2;
  93    }
  94
  95
  96    /* BRW_NEW_URB_FENCE */
  97    if (intel->gen == 5) {
  98       switch (brw->urb.nr_vs_entries) {
  99       case 8:
 100       case 12:
 101       case 16:
 102       case 32:
 103       case 64:
 104       case 96:
 105       case 128:
 106       case 168:
 107       case 192:
 108       case 224:
 109       case 256:
 110          vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries >> 2;
 111          break;
 112       default:
 113          assert(0);
 114       }
 115    } else {
 116       switch (brw->urb.nr_vs_entries) {
 117       case 8:
 118       case 12:
 119       case 16:
 120       case 32:
 121          break;
 122       case 64:
 123          assert(intel->is_g4x);
 124          break;
 125       default:
 126          assert(0);
 127       }
 128       vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries;
 129    }
 130
 131    vs->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
 132
 133    vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
 134                                    1, brw->vs_max_threads) - 1;
 135
 136    /* No samplers for ARB_vp programs:
 137     */
 138    /* It has to be set to 0 for Ironlake
 139     */
 140    vs->vs5.sampler_count = 0;
 141
 142    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 143       vs->thread4.stats_enable = 1;
 144
 145    /* Vertex program always enabled:
 146     */
 147    vs->vs6.vs_enable = 1;
 148
 149    brw->state.dirty.cache |= CACHE_NEW_VS_UNIT;
 150 }
 151
 152 const struct brw_tracked_state brw_vs_unit = {
 153    .dirty = {
 154       .mesa  = _NEW_TRANSFORM,
 155       .brw   = (BRW_NEW_BATCH |
 156                 BRW_NEW_PROGRAM_CACHE |
 157                 BRW_NEW_CURBE_OFFSETS |
 158                 BRW_NEW_NR_VS_SURFACES |
 159                 BRW_NEW_URB_FENCE),
 160       .cache = CACHE_NEW_VS_PROG
 161    },
 162    .prepare = brw_prepare_vs_unit,
 163 };