src/mesa/drivers/dri/i965/brw_vs_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "main/macros.h"
  38
  39 struct brw_vs_unit_key {
  40    unsigned int total_grf;
  41    unsigned int urb_entry_read_length;
  42    unsigned int curb_entry_read_length;
  43
  44    unsigned int curbe_offset;
  45
  46    unsigned int nr_urb_entries, urb_size;
  47
  48    unsigned int nr_surfaces;
  49 };
  50
  51 static void
  52 vs_unit_populate_key(struct brw_context *brw, struct brw_vs_unit_key *key)
  53 {
  54    GLcontext *ctx = &brw->intel.ctx;
  55
  56    memset(key, 0, sizeof(*key));
  57
  58    /* CACHE_NEW_VS_PROG */
  59    key->total_grf = brw->vs.prog_data->total_grf;
  60    key->urb_entry_read_length = brw->vs.prog_data->urb_read_length;
  61    key->curb_entry_read_length = brw->vs.prog_data->curb_read_length;
  62
  63    /* BRW_NEW_URB_FENCE */
  64    key->nr_urb_entries = brw->urb.nr_vs_entries;
  65    key->urb_size = brw->urb.vsize;
  66
  67    /* BRW_NEW_NR_VS_SURFACES */
  68    key->nr_surfaces = brw->vs.nr_surfaces;
  69
  70    /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM */
  71    if (ctx->Transform.ClipPlanesEnabled) {
  72       /* Note that we read in the userclip planes as well, hence
  73        * clip_start:
  74        */
  75       key->curbe_offset = brw->curbe.clip_start;
  76    }
  77    else {
  78       key->curbe_offset = brw->curbe.vs_start;
  79    }
  80 }
  81
  82 static dri_bo *
  83 vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
  84 {
  85    struct intel_context *intel = &brw->intel;
  86    struct brw_vs_unit_state vs;
  87    dri_bo *bo;
  88    int chipset_max_threads;
  89
  90    memset(&vs, 0, sizeof(vs));
  91
  92    vs.thread0.kernel_start_pointer = brw->vs.prog_bo->offset >> 6; /* reloc */
  93    vs.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
  94    vs.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  95    /* Choosing multiple program flow means that we may get 2-vertex threads,
  96     * which will have the channel mask for dwords 4-7 enabled in the thread,
  97     * and those dwords will be written to the second URB handle when we
  98     * brw_urb_WRITE() results.
  99     */
 100    vs.thread1.single_program_flow = 0;
 101
 102    if (intel->is_ironlake)
 103       vs.thread1.binding_table_entry_count = 0; /* hardware requirement */
 104    else
 105       vs.thread1.binding_table_entry_count = key->nr_surfaces;
 106
 107    vs.thread3.urb_entry_read_length = key->urb_entry_read_length;
 108    vs.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
 109    vs.thread3.dispatch_grf_start_reg = 1;
 110    vs.thread3.urb_entry_read_offset = 0;
 111    vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
 112
 113    if (intel->is_ironlake) {
 114       switch (key->nr_urb_entries) {
 115       case 8:
 116       case 12:
 117       case 16:
 118       case 32:
 119       case 64:
 120       case 96:
 121       case 128:
 122       case 168:
 123       case 192:
 124       case 224:
 125       case 256:
 126          vs.thread4.nr_urb_entries = key->nr_urb_entries >> 2;
 127          break;
 128       default:
 129          assert(0);
 130       }
 131    } else {
 132       switch (key->nr_urb_entries) {
 133       case 8:
 134       case 12:
 135       case 16:
 136       case 32:
 137          break;
 138       case 64:
 139          assert(BRW_IS_G4X(brw));
 140          break;
 141       default:
 142          assert(0);
 143       }
 144       vs.thread4.nr_urb_entries = key->nr_urb_entries;
 145    }
 146
 147    vs.thread4.urb_entry_allocation_size = key->urb_size - 1;
 148
 149    if (intel->is_ironlake)
 150       chipset_max_threads = 72;
 151    else if (BRW_IS_G4X(brw))
 152       chipset_max_threads = 32;
 153    else
 154       chipset_max_threads = 16;
 155    vs.thread4.max_threads = CLAMP(key->nr_urb_entries / 2,
 156                                   1, chipset_max_threads) - 1;
 157
 158    if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
 159       vs.thread4.max_threads = 0;
 160
 161    /* No samplers for ARB_vp programs:
 162     */
 163    /* It has to be set to 0 for IGDNG
 164     */
 165    vs.vs5.sampler_count = 0;
 166
 167    if (INTEL_DEBUG & DEBUG_STATS)
 168       vs.thread4.stats_enable = 1;
 169
 170    /* Vertex program always enabled:
 171     */
 172    vs.vs6.vs_enable = 1;
 173
 174    bo = brw_upload_cache(&brw->cache, BRW_VS_UNIT,
 175                          key, sizeof(*key),
 176                          &brw->vs.prog_bo, 1,
 177                          &vs, sizeof(vs),
 178                          NULL, NULL);
 179
 180    /* Emit VS program relocation */
 181    dri_bo_emit_reloc(bo,
 182                      I915_GEM_DOMAIN_INSTRUCTION, 0,
 183                      vs.thread0.grf_reg_count << 1,
 184                      offsetof(struct brw_vs_unit_state, thread0),
 185                      brw->vs.prog_bo);
 186
 187    return bo;
 188 }
 189
 190 static void prepare_vs_unit(struct brw_context *brw)
 191 {
 192    struct brw_vs_unit_key key;
 193
 194    vs_unit_populate_key(brw, &key);
 195
 196    dri_bo_unreference(brw->vs.state_bo);
 197    brw->vs.state_bo = brw_search_cache(&brw->cache, BRW_VS_UNIT,
 198                                        &key, sizeof(key),
 199                                        &brw->vs.prog_bo, 1,
 200                                        NULL);
 201    if (brw->vs.state_bo == NULL) {
 202       brw->vs.state_bo = vs_unit_create_from_key(brw, &key);
 203    }
 204 }
 205
 206 const struct brw_tracked_state brw_vs_unit = {
 207    .dirty = {
 208       .mesa  = _NEW_TRANSFORM,
 209       .brw   = (BRW_NEW_CURBE_OFFSETS |
 210                 BRW_NEW_NR_VS_SURFACES |
 211                 BRW_NEW_URB_FENCE),
 212       .cache = CACHE_NEW_VS_PROG
 213    },
 214    .prepare = prepare_vs_unit,
 215 };