i965: Use state streaming on programs, and state base address on gen5+.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vtbl.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27
28 /*
29 * Authors:
30 * Keith Whitwell <keith@tungstengraphics.com>
31 */
32
33 #include "main/glheader.h"
34 #include "main/mtypes.h"
35 #include "main/imports.h"
36 #include "main/macros.h"
37 #include "main/colormac.h"
38
39 #include "intel_batchbuffer.h"
40 #include "intel_regions.h"
41
42 #include "brw_context.h"
43 #include "brw_defines.h"
44 #include "brw_state.h"
45 #include "brw_draw.h"
46 #include "brw_vs.h"
47 #include "brw_wm.h"
48
49 #include "../glsl/ralloc.h"
50
51 static void
52 dri_bo_release(drm_intel_bo **bo)
53 {
54 drm_intel_bo_unreference(*bo);
55 *bo = NULL;
56 }
57
58
59 /**
60 * called from intelDestroyContext()
61 */
62 static void brw_destroy_context( struct intel_context *intel )
63 {
64 struct brw_context *brw = brw_context(&intel->ctx);
65
66 brw_destroy_state(brw);
67 brw_draw_destroy( brw );
68 brw_clear_validated_bos(brw);
69 ralloc_free(brw->wm.compile_data);
70
71 dri_bo_release(&brw->curbe.curbe_bo);
72 dri_bo_release(&brw->vs.const_bo);
73 dri_bo_release(&brw->wm.const_bo);
74
75 free(brw->curbe.last_buf);
76 free(brw->curbe.next_buf);
77 }
78
79
80 /**
81 * called from intelDrawBuffer()
82 */
83 static void brw_set_draw_region( struct intel_context *intel,
84 struct intel_region *color_regions[],
85 struct intel_region *depth_region,
86 GLuint num_color_regions)
87 {
88 }
89
90
91 /**
92 * called from intel_batchbuffer_flush and children before sending a
93 * batchbuffer off.
94 */
95 static void brw_finish_batch(struct intel_context *intel)
96 {
97 struct brw_context *brw = brw_context(&intel->ctx);
98 brw_emit_query_end(brw);
99
100 if (brw->curbe.curbe_bo) {
101 drm_intel_gem_bo_unmap_gtt(brw->curbe.curbe_bo);
102 drm_intel_bo_unreference(brw->curbe.curbe_bo);
103 brw->curbe.curbe_bo = NULL;
104 }
105 }
106
107
108 /**
109 * called from intelFlushBatchLocked
110 */
111 static void brw_new_batch( struct intel_context *intel )
112 {
113 struct brw_context *brw = brw_context(&intel->ctx);
114
115 /* Mark all context state as needing to be re-emitted.
116 * This is probably not as severe as on 915, since almost all of our state
117 * is just in referenced buffers.
118 */
119 brw->state.dirty.brw |= BRW_NEW_CONTEXT | BRW_NEW_BATCH;
120
121 brw->vb.nr_current_buffers = 0;
122
123 /* Mark that the current program cache BO has been used by the GPU.
124 * It will be reallocated if we need to put new programs in for the
125 * next batch.
126 */
127 brw->cache.bo_used_by_gpu = true;
128 }
129
130 static void brw_invalidate_state( struct intel_context *intel, GLuint new_state )
131 {
132 /* nothing */
133 }
134
135 /**
136 * \see intel_context.vtbl.is_hiz_depth_format
137 */
138 static bool brw_is_hiz_depth_format(struct intel_context *intel,
139 gl_format format)
140 {
141 /* In the future, this will support Z_FLOAT32. */
142 return intel->has_hiz && (format == MESA_FORMAT_X8_Z24);
143 }
144
145
146 void brwInitVtbl( struct brw_context *brw )
147 {
148 brw->intel.vtbl.check_vertex_size = 0;
149 brw->intel.vtbl.emit_state = 0;
150 brw->intel.vtbl.reduced_primitive_state = 0;
151 brw->intel.vtbl.render_start = 0;
152 brw->intel.vtbl.update_texture_state = 0;
153
154 brw->intel.vtbl.invalidate_state = brw_invalidate_state;
155 brw->intel.vtbl.new_batch = brw_new_batch;
156 brw->intel.vtbl.finish_batch = brw_finish_batch;
157 brw->intel.vtbl.destroy = brw_destroy_context;
158 brw->intel.vtbl.set_draw_region = brw_set_draw_region;
159 brw->intel.vtbl.debug_batch = brw_debug_batch;
160 brw->intel.vtbl.render_target_supported = brw_render_target_supported;
161 brw->intel.vtbl.is_hiz_depth_format = brw_is_hiz_depth_format;
162 }