src/mesa/drivers/dri/i965/brw_vtbl.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26 **********************************************************************/
  27
  28 /*
  29  * Authors:
  30  *   Keith Whitwell <keith@tungstengraphics.com>
  31  */
  32
  33 #include "main/glheader.h"
  34 #include "main/mtypes.h"
  35 #include "main/imports.h"
  36 #include "main/macros.h"
  37 #include "main/colormac.h"
  38 #include "main/renderbuffer.h"
  39 #include "main/framebuffer.h"
  40
  41 #include "intel_batchbuffer.h"
  42 #include "intel_regions.h"
  43 #include "intel_fbo.h"
  44
  45 #include "brw_context.h"
  46 #include "brw_program.h"
  47 #include "brw_defines.h"
  48 #include "brw_state.h"
  49 #include "brw_draw.h"
  50 #include "brw_vs.h"
  51 #include "brw_wm.h"
  52
  53 #include "gen6_blorp.h"
  54 #include "gen7_blorp.h"
  55
  56 #include "glsl/ralloc.h"
  57
  58 static void
  59 dri_bo_release(drm_intel_bo **bo)
  60 {
  61    drm_intel_bo_unreference(*bo);
  62    *bo = NULL;
  63 }
  64
  65
  66 /**
  67  * called from intelDestroyContext()
  68  */
  69 static void brw_destroy_context( struct intel_context *intel )
  70 {
  71    struct brw_context *brw = brw_context(&intel->ctx);
  72
  73    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
  74       /* Force a report. */
  75       brw->shader_time.report_time = 0;
  76
  77       brw_collect_and_report_shader_time(brw);
  78       brw_destroy_shader_time(brw);
  79    }
  80
  81    brw_destroy_state(brw);
  82    brw_draw_destroy( brw );
  83
  84    dri_bo_release(&brw->curbe.curbe_bo);
  85    dri_bo_release(&brw->vs.const_bo);
  86    dri_bo_release(&brw->wm.const_bo);
  87
  88    free(brw->curbe.last_buf);
  89    free(brw->curbe.next_buf);
  90
  91    drm_intel_gem_context_destroy(intel->hw_ctx);
  92 }
  93
  94 /**
  95  * Stub state update function for i915.
  96  *
  97  * In i915, hardware state updates for drawbuffer changes are driven by
  98  * driver-internal calls to GL state update hooks.  In i965, we recompute the
  99  * apporpriate state at draw time as a result of _NEW_BUFFERS being set, so we
 100  * don't need this hook.
 101  */
 102 static void
 103 brw_update_draw_buffer(struct intel_context *intel)
 104 {
 105 }
 106
 107 /**
 108  * called from intel_batchbuffer_flush and children before sending a
 109  * batchbuffer off.
 110  *
 111  * Note that ALL state emitted here must fit in the reserved space
 112  * at the end of a batchbuffer.  If you add more GPU state, increase
 113  * the BATCH_RESERVED macro.
 114  */
 115 static void brw_finish_batch(struct intel_context *intel)
 116 {
 117    struct brw_context *brw = brw_context(&intel->ctx);
 118    brw_emit_query_end(brw);
 119
 120    if (brw->curbe.curbe_bo) {
 121       drm_intel_gem_bo_unmap_gtt(brw->curbe.curbe_bo);
 122       drm_intel_bo_unreference(brw->curbe.curbe_bo);
 123       brw->curbe.curbe_bo = NULL;
 124    }
 125 }
 126
 127
 128 /**
 129  * called from intelFlushBatchLocked
 130  */
 131 static void brw_new_batch( struct intel_context *intel )
 132 {
 133    struct brw_context *brw = brw_context(&intel->ctx);
 134
 135    /* If the kernel supports hardware contexts, then most hardware state is
 136     * preserved between batches; we only need to re-emit state that is required
 137     * to be in every batch.  Otherwise we need to re-emit all the state that
 138     * would otherwise be stored in the context (which for all intents and
 139     * purposes means everything).
 140     */
 141    if (intel->hw_ctx == NULL)
 142       brw->state.dirty.brw |= BRW_NEW_CONTEXT;
 143
 144    brw->state.dirty.brw |= BRW_NEW_BATCH;
 145
 146    /* Assume that the last command before the start of our batch was a
 147     * primitive, for safety.
 148     */
 149    intel->batch.need_workaround_flush = true;
 150
 151    brw->state_batch_count = 0;
 152
 153    brw->ib.type = -1;
 154
 155    /* Mark that the current program cache BO has been used by the GPU.
 156     * It will be reallocated if we need to put new programs in for the
 157     * next batch.
 158     */
 159    brw->cache.bo_used_by_gpu = true;
 160
 161    /* We need to periodically reap the shader time results, because rollover
 162     * happens every few seconds.  We also want to see results every once in a
 163     * while, because many programs won't cleanly destroy our context, so the
 164     * end-of-run printout may not happen.
 165     */
 166    if (INTEL_DEBUG & DEBUG_SHADER_TIME)
 167       brw_collect_and_report_shader_time(brw);
 168 }
 169
 170 static void brw_invalidate_state( struct intel_context *intel, GLuint new_state )
 171 {
 172    /* nothing */
 173 }
 174
 175 /**
 176  * \see intel_context.vtbl.is_hiz_depth_format
 177  */
 178 static bool brw_is_hiz_depth_format(struct intel_context *intel,
 179                                     gl_format format)
 180 {
 181    if (!intel->has_hiz)
 182       return false;
 183
 184    switch (format) {
 185    case MESA_FORMAT_Z32_FLOAT:
 186    case MESA_FORMAT_Z32_FLOAT_X24S8:
 187    case MESA_FORMAT_X8_Z24:
 188    case MESA_FORMAT_S8_Z24:
 189    case MESA_FORMAT_Z16:
 190       return true;
 191    default:
 192       return false;
 193    }
 194 }
 195
 196 void brwInitVtbl( struct brw_context *brw )
 197 {
 198    brw->intel.vtbl.check_vertex_size = 0;
 199    brw->intel.vtbl.emit_state = 0;
 200    brw->intel.vtbl.reduced_primitive_state = 0;
 201    brw->intel.vtbl.render_start = 0;
 202    brw->intel.vtbl.update_texture_state = 0;
 203
 204    brw->intel.vtbl.invalidate_state = brw_invalidate_state;
 205    brw->intel.vtbl.new_batch = brw_new_batch;
 206    brw->intel.vtbl.finish_batch = brw_finish_batch;
 207    brw->intel.vtbl.destroy = brw_destroy_context;
 208    brw->intel.vtbl.update_draw_buffer = brw_update_draw_buffer;
 209    brw->intel.vtbl.debug_batch = brw_debug_batch;
 210    brw->intel.vtbl.annotate_aub = brw_annotate_aub;
 211    brw->intel.vtbl.render_target_supported = brw_render_target_supported;
 212    brw->intel.vtbl.is_hiz_depth_format = brw_is_hiz_depth_format;
 213
 214    assert(brw->intel.gen >= 4);
 215    if (brw->intel.gen >= 7) {
 216       gen7_init_vtable_surface_functions(brw);
 217       brw->intel.vtbl.emit_depth_stencil_hiz = gen7_emit_depth_stencil_hiz;
 218    } else if (brw->intel.gen >= 4) {
 219       gen4_init_vtable_surface_functions(brw);
 220       brw->intel.vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz;
 221    }
 222 }