src/mesa/drivers/dri/i965/brw_vtbl.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34
  35 #include "glheader.h"
  36 #include "mtypes.h"
  37 #include "imports.h"
  38 #include "macros.h"
  39 #include "colormac.h"
  40
  41 #include "intel_batchbuffer.h"
  42 #include "intel_regions.h"
  43
  44 #include "brw_context.h"
  45 #include "brw_defines.h"
  46 #include "brw_state.h"
  47
  48 #include "brw_draw.h"
  49 #include "brw_state.h"
  50 #include "brw_aub.h"
  51 #include "brw_fallback.h"
  52 #include "brw_vs.h"
  53
  54
  55
  56 /* called from intelDestroyContext()
  57  */
  58 static void brw_destroy_context( struct intel_context *intel )
  59 {
  60    GLcontext *ctx = &intel->ctx;
  61    struct brw_context *brw = brw_context(&intel->ctx);
  62
  63    brw_aub_destroy(brw);
  64
  65    brw_destroy_metaops(brw);
  66    brw_destroy_state(brw);
  67    brw_draw_destroy( brw );
  68
  69    brw_ProgramCacheDestroy( ctx );
  70    brw_FrameBufferTexDestroy( brw );
  71 }
  72
  73 /* called from intelDrawBuffer()
  74  */
  75 static void brw_set_draw_region( struct intel_context *intel,
  76                                   struct intel_region *draw_region,
  77                                   struct intel_region *depth_region)
  78 {
  79    struct brw_context *brw = brw_context(&intel->ctx);
  80
  81    intel_region_release(intel, &brw->state.draw_region);
  82    intel_region_release(intel, &brw->state.depth_region);
  83    intel_region_reference(&brw->state.draw_region, draw_region);
  84    intel_region_reference(&brw->state.depth_region, depth_region);
  85 }
  86
  87
  88 /* called from intelFlushBatchLocked
  89  */
  90 static void brw_lost_hardware( struct intel_context *intel )
  91 {
  92    struct brw_context *brw = brw_context(&intel->ctx);
  93
  94    /* Note that we effectively lose the context after this.
  95     *
  96     * Setting this flag provokes a state buffer wrap and also flushes
  97     * the hardware caches.
  98     */
  99    brw->state.dirty.brw |= BRW_NEW_CONTEXT;
 100
 101    /* Which means there shouldn't be any commands already queued:
 102     */
 103    assert(intel->batch->ptr == intel->batch->map + intel->batch->offset);
 104
 105    brw->state.dirty.mesa |= ~0;
 106    brw->state.dirty.brw |= ~0;
 107    brw->state.dirty.cache |= ~0;
 108 }
 109
 110 static void brw_note_fence( struct intel_context *intel,
 111                             GLuint fence )
 112 {
 113    brw_context(&intel->ctx)->state.dirty.brw |= BRW_NEW_FENCE;
 114 }
 115
 116 static void brw_note_unlock( struct intel_context *intel )
 117 {
 118   struct brw_context *brw = brw_context(&intel->ctx);
 119
 120    brw_pool_check_wrap(brw, &brw->pool[BRW_GS_POOL]);
 121    brw_pool_check_wrap(brw, &brw->pool[BRW_SS_POOL]);
 122
 123    brw_context(&intel->ctx)->state.dirty.brw |= BRW_NEW_LOCK;
 124 }
 125
 126
 127 void brw_do_flush( struct brw_context *brw,
 128                    GLuint flags )
 129 {
 130    struct brw_mi_flush flush;
 131    memset(&flush, 0, sizeof(flush));
 132    flush.opcode = CMD_MI_FLUSH;
 133    flush.flags = flags;
 134    BRW_BATCH_STRUCT(brw, &flush);
 135 }
 136
 137
 138 static void brw_emit_flush( struct intel_context *intel,
 139                         GLuint unused )
 140 {
 141    brw_do_flush(brw_context(&intel->ctx),
 142                 BRW_FLUSH_STATE_CACHE|BRW_FLUSH_READ_CACHE);
 143 }
 144
 145
 146 /* called from intelWaitForIdle() and intelFlush()
 147  *
 148  * For now, just flush everything.  Could be smarter later.
 149  */
 150 static GLuint brw_flush_cmd( void )
 151 {
 152    struct brw_mi_flush flush;
 153    flush.opcode = CMD_MI_FLUSH;
 154    flush.pad = 0;
 155    flush.flags = BRW_FLUSH_READ_CACHE | BRW_FLUSH_STATE_CACHE;
 156    return *(GLuint *)&flush;
 157 }
 158
 159
 160
 161
 162 static void brw_invalidate_state( struct intel_context *intel, GLuint new_state )
 163 {
 164    /* nothing */
 165 }
 166
 167
 168 void brwInitVtbl( struct brw_context *brw )
 169 {
 170    brw->intel.vtbl.check_vertex_size = 0;
 171    brw->intel.vtbl.emit_state = 0;
 172    brw->intel.vtbl.reduced_primitive_state = 0;
 173    brw->intel.vtbl.render_start = 0;
 174    brw->intel.vtbl.update_texture_state = 0;
 175
 176    brw->intel.vtbl.invalidate_state = brw_invalidate_state;
 177    brw->intel.vtbl.note_fence = brw_note_fence;
 178    brw->intel.vtbl.note_unlock = brw_note_unlock;
 179    brw->intel.vtbl.lost_hardware = brw_lost_hardware;
 180    brw->intel.vtbl.destroy = brw_destroy_context;
 181    brw->intel.vtbl.set_draw_region = brw_set_draw_region;
 182    brw->intel.vtbl.flush_cmd = brw_flush_cmd;
 183    brw->intel.vtbl.emit_flush = brw_emit_flush;
 184 }
 185