vk: Add four unit tests for our lock-free data-structures
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vue_map.c
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_vue_map.c
26 *
27 * This file computes the "VUE map" for a (non-fragment) shader stage, which
28 * describes the layout of its output varyings. The VUE map is used to match
29 * outputs from one stage with the inputs of the next.
30 *
31 * Largely, varyings can be placed however we like - producers/consumers simply
32 * have to agree on the layout. However, there is also a "VUE Header" that
33 * prescribes a fixed-layout for items that interact with fixed function
34 * hardware, such as the clipper and rasterizer.
35 *
36 * Authors:
37 * Paul Berry <stereotype441@gmail.com>
38 * Chris Forbes <chrisf@ijw.co.nz>
39 * Eric Anholt <eric@anholt.net>
40 */
41
42
43 #include "main/compiler.h"
44 #include "brw_context.h"
45
46 static inline void
47 assign_vue_slot(struct brw_vue_map *vue_map, int varying)
48 {
49 /* Make sure this varying hasn't been assigned a slot already */
50 assert (vue_map->varying_to_slot[varying] == -1);
51
52 vue_map->varying_to_slot[varying] = vue_map->num_slots;
53 vue_map->slot_to_varying[vue_map->num_slots++] = varying;
54 }
55
56 /**
57 * Compute the VUE map for a shader stage.
58 */
59 void
60 brw_compute_vue_map(const struct brw_device_info *devinfo,
61 struct brw_vue_map *vue_map,
62 GLbitfield64 slots_valid)
63 {
64 vue_map->slots_valid = slots_valid;
65 int i;
66
67 /* gl_Layer and gl_ViewportIndex don't get their own varying slots -- they
68 * are stored in the first VUE slot (VARYING_SLOT_PSIZ).
69 */
70 slots_valid &= ~(VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT);
71
72 /* Make sure that the values we store in vue_map->varying_to_slot and
73 * vue_map->slot_to_varying won't overflow the signed chars that are used
74 * to store them. Note that since vue_map->slot_to_varying sometimes holds
75 * values equal to BRW_VARYING_SLOT_COUNT, we need to ensure that
76 * BRW_VARYING_SLOT_COUNT is <= 127, not 128.
77 */
78 STATIC_ASSERT(BRW_VARYING_SLOT_COUNT <= 127);
79
80 vue_map->num_slots = 0;
81 for (i = 0; i < BRW_VARYING_SLOT_COUNT; ++i) {
82 vue_map->varying_to_slot[i] = -1;
83 vue_map->slot_to_varying[i] = BRW_VARYING_SLOT_COUNT;
84 }
85
86 /* VUE header: format depends on chip generation and whether clipping is
87 * enabled.
88 *
89 * See the Sandybridge PRM, Volume 2 Part 1, section 1.5.1 (page 30),
90 * "Vertex URB Entry (VUE) Formats" which describes the VUE header layout.
91 */
92 if (devinfo->gen < 6) {
93 /* There are 8 dwords in VUE header pre-Ironlake:
94 * dword 0-3 is indices, point width, clip flags.
95 * dword 4-7 is ndc position
96 * dword 8-11 is the first vertex data.
97 *
98 * On Ironlake the VUE header is nominally 20 dwords, but the hardware
99 * will accept the same header layout as Gen4 [and should be a bit faster]
100 */
101 assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
102 assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC);
103 assign_vue_slot(vue_map, VARYING_SLOT_POS);
104 } else {
105 /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
106 * dword 0-3 of the header is indices, point width, clip flags.
107 * dword 4-7 is the 4D space position
108 * dword 8-15 of the vertex header is the user clip distance if
109 * enabled.
110 * dword 8-11 or 16-19 is the first vertex element data we fill.
111 */
112 assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
113 assign_vue_slot(vue_map, VARYING_SLOT_POS);
114 if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0))
115 assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0);
116 if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1))
117 assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1);
118
119 /* front and back colors need to be consecutive so that we can use
120 * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing
121 * two-sided color.
122 */
123 if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL0))
124 assign_vue_slot(vue_map, VARYING_SLOT_COL0);
125 if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC0))
126 assign_vue_slot(vue_map, VARYING_SLOT_BFC0);
127 if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL1))
128 assign_vue_slot(vue_map, VARYING_SLOT_COL1);
129 if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC1))
130 assign_vue_slot(vue_map, VARYING_SLOT_BFC1);
131 }
132
133 /* The hardware doesn't care about the rest of the vertex outputs, so just
134 * assign them contiguously. Don't reassign outputs that already have a
135 * slot.
136 *
137 * We generally don't need to assign a slot for VARYING_SLOT_CLIP_VERTEX,
138 * since it's encoded as the clip distances by emit_clip_distances().
139 * However, it may be output by transform feedback, and we'd rather not
140 * recompute state when TF changes, so we just always include it.
141 */
142 for (int i = 0; i < VARYING_SLOT_MAX; ++i) {
143 if ((slots_valid & BITFIELD64_BIT(i)) &&
144 vue_map->varying_to_slot[i] == -1) {
145 assign_vue_slot(vue_map, i);
146 }
147 }
148 }