i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm.c
1 /*
2 * Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 * Intel funded Tungsten Graphics to
4 * develop this 3D driver.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26 #include "brw_context.h"
27 #include "brw_wm.h"
28 #include "brw_state.h"
29 #include "main/enums.h"
30 #include "main/formats.h"
31 #include "main/fbobject.h"
32 #include "main/samplerobj.h"
33 #include "main/framebuffer.h"
34 #include "program/prog_parameter.h"
35 #include "program/program.h"
36 #include "intel_mipmap_tree.h"
37 #include "intel_image.h"
38 #include "compiler/brw_nir.h"
39 #include "brw_program.h"
40
41 #include "util/ralloc.h"
42
43 static void
44 assign_fs_binding_table_offsets(const struct gen_device_info *devinfo,
45 const struct gl_program *prog,
46 const struct brw_wm_prog_key *key,
47 struct brw_wm_prog_data *prog_data)
48 {
49 uint32_t next_binding_table_offset = 0;
50
51 /* If there are no color regions, we still perform an FB write to a null
52 * renderbuffer, which we place at surface index 0.
53 */
54 prog_data->binding_table.render_target_start = next_binding_table_offset;
55 next_binding_table_offset += MAX2(key->nr_color_regions, 1);
56
57 next_binding_table_offset =
58 brw_assign_common_binding_table_offsets(devinfo, prog, &prog_data->base,
59 next_binding_table_offset);
60
61 if (prog->nir->info.outputs_read && !key->coherent_fb_fetch) {
62 prog_data->binding_table.render_target_read_start =
63 next_binding_table_offset;
64 next_binding_table_offset += key->nr_color_regions;
65 }
66 }
67
68 static void
69 brw_wm_debug_recompile(struct brw_context *brw, struct gl_program *prog,
70 const struct brw_wm_prog_key *key)
71 {
72 perf_debug("Recompiling fragment shader for program %d\n", prog->Id);
73
74 bool found = false;
75 const struct brw_wm_prog_key *old_key =
76 brw_find_previous_compile(&brw->cache, BRW_CACHE_FS_PROG,
77 key->program_string_id);
78
79 if (!old_key) {
80 perf_debug(" Didn't find previous compile in the shader cache for debug\n");
81 return;
82 }
83
84 found |= key_debug(brw, "alphatest, computed depth, depth test, or "
85 "depth write",
86 old_key->iz_lookup, key->iz_lookup);
87 found |= key_debug(brw, "depth statistics",
88 old_key->stats_wm, key->stats_wm);
89 found |= key_debug(brw, "flat shading",
90 old_key->flat_shade, key->flat_shade);
91 found |= key_debug(brw, "number of color buffers",
92 old_key->nr_color_regions, key->nr_color_regions);
93 found |= key_debug(brw, "MRT alpha test or alpha-to-coverage",
94 old_key->replicate_alpha, key->replicate_alpha);
95 found |= key_debug(brw, "fragment color clamping",
96 old_key->clamp_fragment_color, key->clamp_fragment_color);
97 found |= key_debug(brw, "per-sample interpolation",
98 old_key->persample_interp, key->persample_interp);
99 found |= key_debug(brw, "multisampled FBO",
100 old_key->multisample_fbo, key->multisample_fbo);
101 found |= key_debug(brw, "frag coord adds sample pos",
102 old_key->frag_coord_adds_sample_pos,
103 key->frag_coord_adds_sample_pos);
104 found |= key_debug(brw, "line smoothing",
105 old_key->line_aa, key->line_aa);
106 found |= key_debug(brw, "high quality derivatives",
107 old_key->high_quality_derivatives,
108 key->high_quality_derivatives);
109 found |= key_debug(brw, "force dual color blending",
110 old_key->force_dual_color_blend,
111 key->force_dual_color_blend);
112 found |= key_debug(brw, "coherent fb fetch",
113 old_key->coherent_fb_fetch, key->coherent_fb_fetch);
114
115 found |= key_debug(brw, "input slots valid",
116 old_key->input_slots_valid, key->input_slots_valid);
117 found |= key_debug(brw, "mrt alpha test function",
118 old_key->alpha_test_func, key->alpha_test_func);
119 found |= key_debug(brw, "mrt alpha test reference value",
120 old_key->alpha_test_ref, key->alpha_test_ref);
121
122 found |= brw_debug_recompile_sampler_key(brw, &old_key->tex, &key->tex);
123
124 if (!found) {
125 perf_debug(" Something else\n");
126 }
127 }
128
129 /**
130 * All Mesa program -> GPU code generation goes through this function.
131 * Depending on the instructions used (i.e. flow control instructions)
132 * we'll use one of two code generators.
133 */
134 static bool
135 brw_codegen_wm_prog(struct brw_context *brw,
136 struct brw_program *fp,
137 struct brw_wm_prog_key *key,
138 struct brw_vue_map *vue_map)
139 {
140 const struct gen_device_info *devinfo = &brw->screen->devinfo;
141 void *mem_ctx = ralloc_context(NULL);
142 struct brw_wm_prog_data prog_data;
143 const GLuint *program;
144 bool start_busy = false;
145 double start_time = 0;
146
147 memset(&prog_data, 0, sizeof(prog_data));
148
149 /* Use ALT floating point mode for ARB programs so that 0^0 == 1. */
150 if (fp->program.is_arb_asm)
151 prog_data.base.use_alt_mode = true;
152
153 assign_fs_binding_table_offsets(devinfo, &fp->program, key, &prog_data);
154
155 if (!fp->program.is_arb_asm) {
156 brw_nir_setup_glsl_uniforms(mem_ctx, fp->program.nir, &fp->program,
157 &prog_data.base, true);
158 brw_nir_analyze_ubo_ranges(brw->screen->compiler, fp->program.nir,
159 prog_data.base.ubo_ranges);
160 } else {
161 brw_nir_setup_arb_uniforms(mem_ctx, fp->program.nir, &fp->program,
162 &prog_data.base);
163
164 if (unlikely(INTEL_DEBUG & DEBUG_WM))
165 brw_dump_arb_asm("fragment", &fp->program);
166 }
167
168 if (unlikely(brw->perf_debug)) {
169 start_busy = (brw->batch.last_bo &&
170 brw_bo_busy(brw->batch.last_bo));
171 start_time = get_time();
172 }
173
174 int st_index8 = -1, st_index16 = -1;
175 if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
176 st_index8 = brw_get_shader_time_index(brw, &fp->program, ST_FS8,
177 !fp->program.is_arb_asm);
178 st_index16 = brw_get_shader_time_index(brw, &fp->program, ST_FS16,
179 !fp->program.is_arb_asm);
180 }
181
182 char *error_str = NULL;
183 program = brw_compile_fs(brw->screen->compiler, brw, mem_ctx,
184 key, &prog_data, fp->program.nir,
185 &fp->program, st_index8, st_index16,
186 true, false, vue_map,
187 &error_str);
188
189 if (program == NULL) {
190 if (!fp->program.is_arb_asm) {
191 fp->program.sh.data->LinkStatus = linking_failure;
192 ralloc_strcat(&fp->program.sh.data->InfoLog, error_str);
193 }
194
195 _mesa_problem(NULL, "Failed to compile fragment shader: %s\n", error_str);
196
197 ralloc_free(mem_ctx);
198 return false;
199 }
200
201 if (unlikely(brw->perf_debug)) {
202 if (fp->compiled_once)
203 brw_wm_debug_recompile(brw, &fp->program, key);
204 fp->compiled_once = true;
205
206 if (start_busy && !brw_bo_busy(brw->batch.last_bo)) {
207 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
208 (get_time() - start_time) * 1000);
209 }
210 }
211
212 brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
213
214 if (unlikely((INTEL_DEBUG & DEBUG_WM) && fp->program.is_arb_asm))
215 fprintf(stderr, "\n");
216
217 /* The param and pull_param arrays will be freed by the shader cache. */
218 ralloc_steal(NULL, prog_data.base.param);
219 ralloc_steal(NULL, prog_data.base.pull_param);
220 brw_upload_cache(&brw->cache, BRW_CACHE_FS_PROG,
221 key, sizeof(struct brw_wm_prog_key),
222 program, prog_data.base.program_size,
223 &prog_data, sizeof(prog_data),
224 &brw->wm.base.prog_offset, &brw->wm.base.prog_data);
225
226 ralloc_free(mem_ctx);
227
228 return true;
229 }
230
231 bool
232 brw_debug_recompile_sampler_key(struct brw_context *brw,
233 const struct brw_sampler_prog_key_data *old_key,
234 const struct brw_sampler_prog_key_data *key)
235 {
236 bool found = false;
237
238 for (unsigned int i = 0; i < MAX_SAMPLERS; i++) {
239 found |= key_debug(brw, "EXT_texture_swizzle or DEPTH_TEXTURE_MODE",
240 old_key->swizzles[i], key->swizzles[i]);
241 }
242 found |= key_debug(brw, "GL_CLAMP enabled on any texture unit's 1st coordinate",
243 old_key->gl_clamp_mask[0], key->gl_clamp_mask[0]);
244 found |= key_debug(brw, "GL_CLAMP enabled on any texture unit's 2nd coordinate",
245 old_key->gl_clamp_mask[1], key->gl_clamp_mask[1]);
246 found |= key_debug(brw, "GL_CLAMP enabled on any texture unit's 3rd coordinate",
247 old_key->gl_clamp_mask[2], key->gl_clamp_mask[2]);
248 found |= key_debug(brw, "gather channel quirk on any texture unit",
249 old_key->gather_channel_quirk_mask, key->gather_channel_quirk_mask);
250 found |= key_debug(brw, "compressed multisample layout",
251 old_key->compressed_multisample_layout_mask,
252 key->compressed_multisample_layout_mask);
253 found |= key_debug(brw, "16x msaa",
254 old_key->msaa_16,
255 key->msaa_16);
256
257 found |= key_debug(brw, "y_uv image bound",
258 old_key->y_uv_image_mask,
259 key->y_uv_image_mask);
260 found |= key_debug(brw, "y_u_v image bound",
261 old_key->y_u_v_image_mask,
262 key->y_u_v_image_mask);
263 found |= key_debug(brw, "yx_xuxv image bound",
264 old_key->yx_xuxv_image_mask,
265 key->yx_xuxv_image_mask);
266 found |= key_debug(brw, "xy_uxvx image bound",
267 old_key->xy_uxvx_image_mask,
268 key->xy_uxvx_image_mask);
269
270
271 for (unsigned int i = 0; i < MAX_SAMPLERS; i++) {
272 found |= key_debug(brw, "textureGather workarounds",
273 old_key->gen6_gather_wa[i], key->gen6_gather_wa[i]);
274 }
275
276 return found;
277 }
278
279 static uint8_t
280 gen6_gather_workaround(GLenum internalformat)
281 {
282 switch (internalformat) {
283 case GL_R8I: return WA_SIGN | WA_8BIT;
284 case GL_R8UI: return WA_8BIT;
285 case GL_R16I: return WA_SIGN | WA_16BIT;
286 case GL_R16UI: return WA_16BIT;
287 default:
288 /* Note that even though GL_R32I and GL_R32UI have format overrides in
289 * the surface state, there is no shader w/a required.
290 */
291 return 0;
292 }
293 }
294
295 void
296 brw_populate_sampler_prog_key_data(struct gl_context *ctx,
297 const struct gl_program *prog,
298 struct brw_sampler_prog_key_data *key)
299 {
300 struct brw_context *brw = brw_context(ctx);
301 const struct gen_device_info *devinfo = &brw->screen->devinfo;
302 GLbitfield mask = prog->SamplersUsed;
303
304 while (mask) {
305 const int s = u_bit_scan(&mask);
306
307 key->swizzles[s] = SWIZZLE_NOOP;
308
309 int unit_id = prog->SamplerUnits[s];
310 const struct gl_texture_unit *unit = &ctx->Texture.Unit[unit_id];
311
312 if (unit->_Current && unit->_Current->Target != GL_TEXTURE_BUFFER) {
313 const struct gl_texture_object *t = unit->_Current;
314 const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
315 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit_id);
316
317 const bool alpha_depth = t->DepthMode == GL_ALPHA &&
318 (img->_BaseFormat == GL_DEPTH_COMPONENT ||
319 img->_BaseFormat == GL_DEPTH_STENCIL);
320
321 /* Haswell handles texture swizzling as surface format overrides
322 * (except for GL_ALPHA); all other platforms need MOVs in the shader.
323 */
324 if (alpha_depth || (devinfo->gen < 8 && !devinfo->is_haswell))
325 key->swizzles[s] = brw_get_texture_swizzle(ctx, t);
326
327 if (devinfo->gen < 8 &&
328 sampler->MinFilter != GL_NEAREST &&
329 sampler->MagFilter != GL_NEAREST) {
330 if (sampler->WrapS == GL_CLAMP)
331 key->gl_clamp_mask[0] |= 1 << s;
332 if (sampler->WrapT == GL_CLAMP)
333 key->gl_clamp_mask[1] |= 1 << s;
334 if (sampler->WrapR == GL_CLAMP)
335 key->gl_clamp_mask[2] |= 1 << s;
336 }
337
338 /* gather4 for RG32* is broken in multiple ways on Gen7. */
339 if (devinfo->gen == 7 && prog->info.uses_texture_gather) {
340 switch (img->InternalFormat) {
341 case GL_RG32I:
342 case GL_RG32UI: {
343 /* We have to override the format to R32G32_FLOAT_LD.
344 * This means that SCS_ALPHA and SCS_ONE will return 0x3f8
345 * (1.0) rather than integer 1. This needs shader hacks.
346 *
347 * On Ivybridge, we whack W (alpha) to ONE in our key's
348 * swizzle. On Haswell, we look at the original texture
349 * swizzle, and use XYZW with channels overridden to ONE,
350 * leaving normal texture swizzling to SCS.
351 */
352 unsigned src_swizzle =
353 devinfo->is_haswell ? t->_Swizzle : key->swizzles[s];
354 for (int i = 0; i < 4; i++) {
355 unsigned src_comp = GET_SWZ(src_swizzle, i);
356 if (src_comp == SWIZZLE_ONE || src_comp == SWIZZLE_W) {
357 key->swizzles[i] &= ~(0x7 << (3 * i));
358 key->swizzles[i] |= SWIZZLE_ONE << (3 * i);
359 }
360 }
361 /* fallthrough */
362 }
363 case GL_RG32F:
364 /* The channel select for green doesn't work - we have to
365 * request blue. Haswell can use SCS for this, but Ivybridge
366 * needs a shader workaround.
367 */
368 if (!devinfo->is_haswell)
369 key->gather_channel_quirk_mask |= 1 << s;
370 break;
371 }
372 }
373
374 /* Gen6's gather4 is broken for UINT/SINT; we treat them as
375 * UNORM/FLOAT instead and fix it in the shader.
376 */
377 if (devinfo->gen == 6 && prog->info.uses_texture_gather) {
378 key->gen6_gather_wa[s] = gen6_gather_workaround(img->InternalFormat);
379 }
380
381 /* If this is a multisample sampler, and uses the CMS MSAA layout,
382 * then we need to emit slightly different code to first sample the
383 * MCS surface.
384 */
385 struct intel_texture_object *intel_tex =
386 intel_texture_object((struct gl_texture_object *)t);
387
388 /* From gen9 onwards some single sampled buffers can also be
389 * compressed. These don't need ld2dms sampling along with mcs fetch.
390 */
391 if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) {
392 assert(devinfo->gen >= 7);
393 assert(intel_tex->mt->surf.samples > 1);
394 assert(intel_tex->mt->mcs_buf);
395 assert(intel_tex->mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
396 key->compressed_multisample_layout_mask |= 1 << s;
397
398 if (intel_tex->mt->surf.samples >= 16) {
399 assert(devinfo->gen >= 9);
400 key->msaa_16 |= 1 << s;
401 }
402 }
403
404 if (t->Target == GL_TEXTURE_EXTERNAL_OES && intel_tex->planar_format) {
405 switch (intel_tex->planar_format->components) {
406 case __DRI_IMAGE_COMPONENTS_Y_UV:
407 key->y_uv_image_mask |= 1 << s;
408 break;
409 case __DRI_IMAGE_COMPONENTS_Y_U_V:
410 key->y_u_v_image_mask |= 1 << s;
411 break;
412 case __DRI_IMAGE_COMPONENTS_Y_XUXV:
413 key->yx_xuxv_image_mask |= 1 << s;
414 break;
415 case __DRI_IMAGE_COMPONENTS_Y_UXVX:
416 key->xy_uxvx_image_mask |= 1 << s;
417 break;
418 default:
419 break;
420 }
421 }
422
423 }
424 }
425 }
426
427 static bool
428 brw_wm_state_dirty(const struct brw_context *brw)
429 {
430 return brw_state_dirty(brw,
431 _NEW_BUFFERS |
432 _NEW_COLOR |
433 _NEW_DEPTH |
434 _NEW_FRAG_CLAMP |
435 _NEW_HINT |
436 _NEW_LIGHT |
437 _NEW_LINE |
438 _NEW_MULTISAMPLE |
439 _NEW_POLYGON |
440 _NEW_STENCIL |
441 _NEW_TEXTURE,
442 BRW_NEW_FRAGMENT_PROGRAM |
443 BRW_NEW_REDUCED_PRIMITIVE |
444 BRW_NEW_STATS_WM |
445 BRW_NEW_VUE_MAP_GEOM_OUT);
446 }
447
448 void
449 brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key)
450 {
451 const struct gen_device_info *devinfo = &brw->screen->devinfo;
452 struct gl_context *ctx = &brw->ctx;
453 /* BRW_NEW_FRAGMENT_PROGRAM */
454 const struct gl_program *prog = brw->programs[MESA_SHADER_FRAGMENT];
455 const struct brw_program *fp = brw_program_const(prog);
456 GLuint lookup = 0;
457 GLuint line_aa;
458
459 memset(key, 0, sizeof(*key));
460
461 /* Build the index for table lookup
462 */
463 if (devinfo->gen < 6) {
464 /* _NEW_COLOR */
465 if (prog->info.fs.uses_discard || ctx->Color.AlphaEnabled) {
466 lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
467 }
468
469 if (prog->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
470 lookup |= BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT;
471 }
472
473 /* _NEW_DEPTH */
474 if (ctx->Depth.Test)
475 lookup |= BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT;
476
477 if (brw_depth_writes_enabled(brw))
478 lookup |= BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT;
479
480 /* _NEW_STENCIL | _NEW_BUFFERS */
481 if (brw->stencil_enabled) {
482 lookup |= BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT;
483
484 if (ctx->Stencil.WriteMask[0] ||
485 ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
486 lookup |= BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT;
487 }
488 key->iz_lookup = lookup;
489 }
490
491 line_aa = BRW_WM_AA_NEVER;
492
493 /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */
494 if (ctx->Line.SmoothFlag) {
495 if (brw->reduced_primitive == GL_LINES) {
496 line_aa = BRW_WM_AA_ALWAYS;
497 }
498 else if (brw->reduced_primitive == GL_TRIANGLES) {
499 if (ctx->Polygon.FrontMode == GL_LINE) {
500 line_aa = BRW_WM_AA_SOMETIMES;
501
502 if (ctx->Polygon.BackMode == GL_LINE ||
503 (ctx->Polygon.CullFlag &&
504 ctx->Polygon.CullFaceMode == GL_BACK))
505 line_aa = BRW_WM_AA_ALWAYS;
506 }
507 else if (ctx->Polygon.BackMode == GL_LINE) {
508 line_aa = BRW_WM_AA_SOMETIMES;
509
510 if ((ctx->Polygon.CullFlag &&
511 ctx->Polygon.CullFaceMode == GL_FRONT))
512 line_aa = BRW_WM_AA_ALWAYS;
513 }
514 }
515 }
516
517 key->line_aa = line_aa;
518
519 /* _NEW_HINT */
520 key->high_quality_derivatives =
521 prog->info.uses_fddx_fddy &&
522 ctx->Hint.FragmentShaderDerivative == GL_NICEST;
523
524 if (devinfo->gen < 6)
525 key->stats_wm = brw->stats_wm;
526
527 /* _NEW_LIGHT */
528 key->flat_shade =
529 (prog->info.inputs_read & (VARYING_BIT_COL0 | VARYING_BIT_COL1)) &&
530 (ctx->Light.ShadeModel == GL_FLAT);
531
532 /* _NEW_FRAG_CLAMP | _NEW_BUFFERS */
533 key->clamp_fragment_color = ctx->Color._ClampFragmentColor;
534
535 /* _NEW_TEXTURE */
536 brw_populate_sampler_prog_key_data(ctx, prog, &key->tex);
537
538 /* _NEW_BUFFERS */
539 key->nr_color_regions = ctx->DrawBuffer->_NumColorDrawBuffers;
540
541 /* _NEW_COLOR */
542 key->force_dual_color_blend = brw->dual_color_blend_by_location &&
543 (ctx->Color.BlendEnabled & 1) && ctx->Color.Blend[0]._UsesDualSrc;
544
545 /* _NEW_MULTISAMPLE, _NEW_COLOR, _NEW_BUFFERS */
546 key->replicate_alpha = ctx->DrawBuffer->_NumColorDrawBuffers > 1 &&
547 (_mesa_is_alpha_test_enabled(ctx) ||
548 _mesa_is_alpha_to_coverage_enabled(ctx));
549
550 /* _NEW_BUFFERS _NEW_MULTISAMPLE */
551 /* Ignore sample qualifier while computing this flag. */
552 if (ctx->Multisample.Enabled) {
553 key->persample_interp =
554 ctx->Multisample.SampleShading &&
555 (ctx->Multisample.MinSampleShadingValue *
556 _mesa_geometric_samples(ctx->DrawBuffer) > 1);
557
558 key->multisample_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
559 }
560
561 /* BRW_NEW_VUE_MAP_GEOM_OUT */
562 if (devinfo->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read &
563 BRW_FS_VARYING_INPUT_MASK) > 16) {
564 key->input_slots_valid = brw->vue_map_geom_out.slots_valid;
565 }
566
567 /* _NEW_COLOR | _NEW_BUFFERS */
568 /* Pre-gen6, the hardware alpha test always used each render
569 * target's alpha to do alpha test, as opposed to render target 0's alpha
570 * like GL requires. Fix that by building the alpha test into the
571 * shader, and we'll skip enabling the fixed function alpha test.
572 */
573 if (devinfo->gen < 6 && ctx->DrawBuffer->_NumColorDrawBuffers > 1 &&
574 ctx->Color.AlphaEnabled) {
575 key->alpha_test_func = ctx->Color.AlphaFunc;
576 key->alpha_test_ref = ctx->Color.AlphaRef;
577 }
578
579 /* The unique fragment program ID */
580 key->program_string_id = fp->id;
581
582 /* Whether reads from the framebuffer should behave coherently. */
583 key->coherent_fb_fetch = ctx->Extensions.MESA_shader_framebuffer_fetch;
584 }
585
586 void
587 brw_upload_wm_prog(struct brw_context *brw)
588 {
589 struct brw_wm_prog_key key;
590 struct brw_program *fp =
591 (struct brw_program *) brw->programs[MESA_SHADER_FRAGMENT];
592
593 if (!brw_wm_state_dirty(brw))
594 return;
595
596 brw_wm_populate_key(brw, &key);
597
598 if (brw_search_cache(&brw->cache, BRW_CACHE_FS_PROG,
599 &key, sizeof(key),
600 &brw->wm.base.prog_offset,
601 &brw->wm.base.prog_data))
602 return;
603
604 if (brw_disk_cache_upload_program(brw, MESA_SHADER_FRAGMENT))
605 return;
606
607 fp = (struct brw_program *) brw->programs[MESA_SHADER_FRAGMENT];
608 fp->id = key.program_string_id;
609
610 MAYBE_UNUSED bool success = brw_codegen_wm_prog(brw, fp, &key,
611 &brw->vue_map_geom_out);
612 assert(success);
613 }
614
615 bool
616 brw_fs_precompile(struct gl_context *ctx, struct gl_program *prog)
617 {
618 struct brw_context *brw = brw_context(ctx);
619 const struct gen_device_info *devinfo = &brw->screen->devinfo;
620 struct brw_wm_prog_key key;
621
622 struct brw_program *bfp = brw_program(prog);
623
624 memset(&key, 0, sizeof(key));
625
626 uint64_t outputs_written = prog->info.outputs_written;
627
628 if (devinfo->gen < 6) {
629 if (prog->info.fs.uses_discard)
630 key.iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
631
632 if (outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
633 key.iz_lookup |= BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT;
634
635 /* Just assume depth testing. */
636 key.iz_lookup |= BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT;
637 key.iz_lookup |= BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT;
638 }
639
640 if (devinfo->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read &
641 BRW_FS_VARYING_INPUT_MASK) > 16) {
642 key.input_slots_valid = prog->info.inputs_read | VARYING_BIT_POS;
643 }
644
645 brw_setup_tex_for_precompile(brw, &key.tex, prog);
646
647 key.nr_color_regions = _mesa_bitcount_64(outputs_written &
648 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH) |
649 BITFIELD64_BIT(FRAG_RESULT_STENCIL) |
650 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)));
651
652 key.program_string_id = bfp->id;
653
654 /* Whether reads from the framebuffer should behave coherently. */
655 key.coherent_fb_fetch = ctx->Extensions.MESA_shader_framebuffer_fetch;
656
657 uint32_t old_prog_offset = brw->wm.base.prog_offset;
658 struct brw_stage_prog_data *old_prog_data = brw->wm.base.prog_data;
659
660 struct brw_vue_map vue_map;
661 if (devinfo->gen < 6) {
662 brw_compute_vue_map(&brw->screen->devinfo, &vue_map,
663 prog->info.inputs_read | VARYING_BIT_POS,
664 false);
665 }
666
667 bool success = brw_codegen_wm_prog(brw, bfp, &key, &vue_map);
668
669 brw->wm.base.prog_offset = old_prog_offset;
670 brw->wm.base.prog_data = old_prog_data;
671
672 return success;
673 }