2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #include "brw_context.h"
34 #include "brw_state.h"
35 #include "main/formats.h"
37 /** Return number of src args for given instruction */
38 GLuint
brw_wm_nr_args( GLuint opcode
)
55 assert(opcode
< MAX_OPCODE
);
56 return _mesa_num_inst_src_regs(opcode
);
61 GLuint
brw_wm_is_scalar_result( GLuint opcode
)
85 * Do GPU code generation for non-GLSL shader. non-GLSL shaders have
86 * no flow control instructions so we can more readily do SSA-style
90 brw_wm_non_glsl_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
92 /* Augment fragment program. Add instructions for pre- and
93 * post-fragment-program tasks such as interpolation and fogging.
97 /* Translate to intermediate representation. Build register usage
102 /* Dead code removal.
106 /* Register allocation.
107 * Divide by two because we operate on 16 pixels at a time and require
108 * two GRF entries for each logical shader register.
110 c
->grf_limit
= BRW_WM_MAX_GRF
/ 2;
114 /* how many general-purpose registers are used */
115 c
->prog_data
.total_grf
= c
->max_wm_grf
;
117 /* Scratch space is used for register spilling */
118 if (c
->last_scratch
) {
119 c
->prog_data
.total_scratch
= c
->last_scratch
+ 0x40;
122 c
->prog_data
.total_scratch
= 0;
132 * All Mesa program -> GPU code generation goes through this function.
133 * Depending on the instructions used (i.e. flow control instructions)
134 * we'll use one of two code generators.
136 static void do_wm_prog( struct brw_context
*brw
,
137 struct brw_fragment_program
*fp
,
138 struct brw_wm_prog_key
*key
)
140 struct brw_wm_compile
*c
;
141 const GLuint
*program
;
144 c
= brw
->wm
.compile_data
;
146 brw
->wm
.compile_data
= calloc(1, sizeof(*brw
->wm
.compile_data
));
147 c
= brw
->wm
.compile_data
;
149 /* Ouch - big out of memory problem. Can't continue
150 * without triggering a segfault, no way to signal,
155 c
->instruction
= calloc(1, BRW_WM_MAX_INSN
* sizeof(*c
->instruction
));
156 c
->prog_instructions
= calloc(1, BRW_WM_MAX_INSN
*
157 sizeof(*c
->prog_instructions
));
158 c
->vreg
= calloc(1, BRW_WM_MAX_VREG
* sizeof(*c
->vreg
));
159 c
->refs
= calloc(1, BRW_WM_MAX_REF
* sizeof(*c
->refs
));
161 void *instruction
= c
->instruction
;
162 void *prog_instructions
= c
->prog_instructions
;
163 void *vreg
= c
->vreg
;
164 void *refs
= c
->refs
;
165 memset(c
, 0, sizeof(*brw
->wm
.compile_data
));
166 c
->instruction
= instruction
;
167 c
->prog_instructions
= prog_instructions
;
171 memcpy(&c
->key
, key
, sizeof(*key
));
174 c
->env_param
= brw
->intel
.ctx
.FragmentProgram
.Parameters
;
176 brw_init_compile(brw
, &c
->func
);
178 /* temporary sanity check assertion */
179 ASSERT(fp
->isGLSL
== brw_wm_is_glsl(&c
->fp
->program
));
181 if (!brw_wm_fs_emit(brw
, c
)) {
183 * Shader which use GLSL features such as flow control are handled
184 * differently from "simple" shaders.
187 c
->dispatch_width
= 8;
188 brw_wm_glsl_emit(brw
, c
);
191 c
->dispatch_width
= 16;
192 brw_wm_non_glsl_emit(brw
, c
);
196 if (INTEL_DEBUG
& DEBUG_WM
)
197 fprintf(stderr
, "\n");
201 program
= brw_get_program(&c
->func
, &program_size
);
203 drm_intel_bo_unreference(brw
->wm
.prog_bo
);
204 brw
->wm
.prog_bo
= brw_upload_cache_with_auxdata(&brw
->cache
, BRW_WM_PROG
,
205 &c
->key
, sizeof(c
->key
),
207 program
, program_size
,
209 sizeof(c
->prog_data
),
215 static void brw_wm_populate_key( struct brw_context
*brw
,
216 struct brw_wm_prog_key
*key
)
218 struct intel_context
*intel
= &brw
->intel
;
219 GLcontext
*ctx
= &brw
->intel
.ctx
;
220 /* BRW_NEW_FRAGMENT_PROGRAM */
221 const struct brw_fragment_program
*fp
=
222 (struct brw_fragment_program
*)brw
->fragment_program
;
223 GLboolean uses_depth
= (fp
->program
.Base
.InputsRead
& (1 << FRAG_ATTRIB_WPOS
)) != 0;
228 memset(key
, 0, sizeof(*key
));
230 /* Build the index for table lookup
233 if (fp
->program
.UsesKill
||
234 ctx
->Color
.AlphaEnabled
)
235 lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
237 if (fp
->program
.Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
238 lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
242 lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
244 if (ctx
->Depth
.Test
&&
245 ctx
->Depth
.Mask
) /* ?? */
246 lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
249 if (ctx
->Stencil
._Enabled
) {
250 lookup
|= IZ_STENCIL_TEST_ENABLE_BIT
;
252 if (ctx
->Stencil
.WriteMask
[0] ||
253 ctx
->Stencil
.WriteMask
[ctx
->Stencil
._BackFace
])
254 lookup
|= IZ_STENCIL_WRITE_ENABLE_BIT
;
259 /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */
260 if (ctx
->Line
.SmoothFlag
) {
261 if (brw
->intel
.reduced_primitive
== GL_LINES
) {
264 else if (brw
->intel
.reduced_primitive
== GL_TRIANGLES
) {
265 if (ctx
->Polygon
.FrontMode
== GL_LINE
) {
266 line_aa
= AA_SOMETIMES
;
268 if (ctx
->Polygon
.BackMode
== GL_LINE
||
269 (ctx
->Polygon
.CullFlag
&&
270 ctx
->Polygon
.CullFaceMode
== GL_BACK
))
273 else if (ctx
->Polygon
.BackMode
== GL_LINE
) {
274 line_aa
= AA_SOMETIMES
;
276 if ((ctx
->Polygon
.CullFlag
&&
277 ctx
->Polygon
.CullFaceMode
== GL_FRONT
))
283 if (intel
->gen
>= 6) {
284 /* R0-1: masks, pixel X/Y coordinates. */
285 key
->nr_payload_regs
= 2;
286 /* R2: only for 32-pixel dispatch.*/
287 /* R3-4: perspective pixel location barycentric */
288 key
->nr_payload_regs
+= 2;
289 /* R5-6: perspective pixel location bary for dispatch width != 8 */
290 if (!fp
->isGLSL
) { /* dispatch_width != 8 */
291 key
->nr_payload_regs
+= 2;
293 /* R7-10: perspective centroid barycentric */
294 /* R11-14: perspective sample barycentric */
295 /* R15-18: linear pixel location barycentric */
296 /* R19-22: linear centroid barycentric */
297 /* R23-26: linear sample barycentric */
299 /* R27: interpolated depth if uses source depth */
301 key
->source_depth_reg
= key
->nr_payload_regs
;
302 key
->nr_payload_regs
++;
303 if (!fp
->isGLSL
) { /* dispatch_width != 8 */
304 /* R28: interpolated depth if not 8-wide. */
305 key
->nr_payload_regs
++;
308 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W.
311 key
->source_w_reg
= key
->nr_payload_regs
;
312 key
->nr_payload_regs
++;
313 if (!fp
->isGLSL
) { /* dispatch_width != 8 */
314 /* R30: interpolated W if not 8-wide. */
315 key
->nr_payload_regs
++;
318 /* R31: MSAA position offsets. */
319 /* R32-: bary for 32-pixel. */
320 /* R58-59: interp W for 32-pixel. */
322 brw_wm_lookup_iz(intel
,
329 /* BRW_NEW_WM_INPUT_DIMENSIONS */
330 key
->proj_attrib_mask
= brw
->wm
.input_size_masks
[4-1];
333 key
->flat_shade
= (ctx
->Light
.ShadeModel
== GL_FLAT
);
336 key
->linear_color
= (ctx
->Hint
.PerspectiveCorrection
== GL_FASTEST
);
339 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
340 const struct gl_texture_unit
*unit
= &ctx
->Texture
.Unit
[i
];
342 if (unit
->_ReallyEnabled
) {
343 const struct gl_texture_object
*t
= unit
->_Current
;
344 const struct gl_texture_image
*img
= t
->Image
[0][t
->BaseLevel
];
345 int swizzles
[SWIZZLE_NIL
+ 1] = {
355 key
->tex_swizzles
[i
] = SWIZZLE_NOOP
;
357 /* GL_DEPTH_TEXTURE_MODE is normally handled through
358 * brw_wm_surface_state, but it applies to shadow compares as
359 * well and our shadow compares always return the result in
362 if (t
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
) {
363 if (t
->DepthMode
== GL_ALPHA
) {
364 swizzles
[0] = SWIZZLE_ZERO
;
365 swizzles
[1] = SWIZZLE_ZERO
;
366 swizzles
[2] = SWIZZLE_ZERO
;
367 } else if (t
->DepthMode
== GL_LUMINANCE
) {
368 swizzles
[3] = SWIZZLE_ONE
;
372 if (img
->InternalFormat
== GL_YCBCR_MESA
) {
373 key
->yuvtex_mask
|= 1 << i
;
374 if (img
->TexFormat
== MESA_FORMAT_YCBCR
)
375 key
->yuvtex_swap_mask
|= 1 << i
;
378 key
->tex_swizzles
[i
] =
379 MAKE_SWIZZLE4(swizzles
[GET_SWZ(t
->_Swizzle
, 0)],
380 swizzles
[GET_SWZ(t
->_Swizzle
, 1)],
381 swizzles
[GET_SWZ(t
->_Swizzle
, 2)],
382 swizzles
[GET_SWZ(t
->_Swizzle
, 3)]);
385 key
->tex_swizzles
[i
] = SWIZZLE_NOOP
;
390 key
->shadowtex_mask
= fp
->program
.Base
.ShadowSamplers
;
394 * Include the draw buffer origin and height so that we can calculate
395 * fragment position values relative to the bottom left of the drawable,
396 * from the incoming screen origin relative position we get as part of our
399 * This is only needed for the WM_WPOSXY opcode when the fragment program
400 * uses the gl_FragCoord input.
402 * We could avoid recompiling by including this as a constant referenced by
403 * our program, but if we were to do that it would also be nice to handle
404 * getting that constant updated at batchbuffer submit time (when we
405 * hold the lock and know where the buffer really is) rather than at emit
406 * time when we don't hold the lock and are just guessing. We could also
407 * just avoid using this as key data if the program doesn't use
410 * For DRI2 the origin_x/y will always be (0,0) but we still need the
411 * drawable height in order to invert the Y axis.
413 if (fp
->program
.Base
.InputsRead
& FRAG_BIT_WPOS
) {
414 key
->drawable_height
= ctx
->DrawBuffer
->Height
;
417 key
->nr_color_regions
= brw
->state
.nr_color_regions
;
419 /* CACHE_NEW_VS_PROG */
420 key
->vp_outputs_written
= brw
->vs
.prog_data
->outputs_written
;
422 /* The unique fragment program ID */
423 key
->program_string_id
= fp
->id
;
427 static void brw_prepare_wm_prog(struct brw_context
*brw
)
429 struct brw_wm_prog_key key
;
430 struct brw_fragment_program
*fp
= (struct brw_fragment_program
*)
431 brw
->fragment_program
;
433 brw_wm_populate_key(brw
, &key
);
435 /* Make an early check for the key.
437 drm_intel_bo_unreference(brw
->wm
.prog_bo
);
438 brw
->wm
.prog_bo
= brw_search_cache(&brw
->cache
, BRW_WM_PROG
,
442 if (brw
->wm
.prog_bo
== NULL
)
443 do_wm_prog(brw
, fp
, &key
);
447 const struct brw_tracked_state brw_wm_prog
= {
449 .mesa
= (_NEW_COLOR
|
458 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
|
459 BRW_NEW_WM_INPUT_DIMENSIONS
|
460 BRW_NEW_REDUCED_PRIMITIVE
),
461 .cache
= CACHE_NEW_VS_PROG
,
463 .prepare
= brw_prepare_wm_prog