src/mesa/drivers/dri/i965/brw_wm.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "brw_context.h"
  33 #include "brw_wm.h"
  34 #include "brw_state.h"
  35 #include "main/formats.h"
  36 #include "main/samplerobj.h"
  37
  38 /** Return number of src args for given instruction */
  39 GLuint brw_wm_nr_args( GLuint opcode )
  40 {
  41    switch (opcode) {
  42    case WM_FRONTFACING:
  43    case WM_PIXELXY:
  44       return 0;
  45    case WM_CINTERP:
  46    case WM_WPOSXY:
  47    case WM_DELTAXY:
  48       return 1;
  49    case WM_LINTERP:
  50    case WM_PIXELW:
  51       return 2;
  52    case WM_FB_WRITE:
  53    case WM_PINTERP:
  54       return 3;
  55    default:
  56       assert(opcode < MAX_OPCODE);
  57       return _mesa_num_inst_src_regs(opcode);
  58    }
  59 }
  60
  61
  62 GLuint brw_wm_is_scalar_result( GLuint opcode )
  63 {
  64    switch (opcode) {
  65    case OPCODE_COS:
  66    case OPCODE_EX2:
  67    case OPCODE_LG2:
  68    case OPCODE_POW:
  69    case OPCODE_RCP:
  70    case OPCODE_RSQ:
  71    case OPCODE_SIN:
  72    case OPCODE_DP2:
  73    case OPCODE_DP3:
  74    case OPCODE_DP4:
  75    case OPCODE_DPH:
  76    case OPCODE_DST:
  77       return 1;
  78
  79    default:
  80       return 0;
  81    }
  82 }
  83
  84
  85 /**
  86  * Do GPU code generation for non-GLSL shader.  non-GLSL shaders have
  87  * no flow control instructions so we can more readily do SSA-style
  88  * optimizations.
  89  */
  90 static void
  91 brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
  92 {
  93    /* Augment fragment program.  Add instructions for pre- and
  94     * post-fragment-program tasks such as interpolation and fogging.
  95     */
  96    brw_wm_pass_fp(c);
  97
  98    /* Translate to intermediate representation.  Build register usage
  99     * chains.
 100     */
 101    brw_wm_pass0(c);
 102
 103    /* Dead code removal.
 104     */
 105    brw_wm_pass1(c);
 106
 107    /* Register allocation.
 108     * Divide by two because we operate on 16 pixels at a time and require
 109     * two GRF entries for each logical shader register.
 110     */
 111    c->grf_limit = BRW_WM_MAX_GRF / 2;
 112
 113    brw_wm_pass2(c);
 114
 115    /* how many general-purpose registers are used */
 116    c->prog_data.total_grf = c->max_wm_grf;
 117
 118    /* Emit GEN4 code.
 119     */
 120    brw_wm_emit(c);
 121 }
 122
 123 void
 124 brw_wm_payload_setup(struct brw_context *brw,
 125                      struct brw_wm_compile *c)
 126 {
 127    struct intel_context *intel = &brw->intel;
 128    bool uses_depth = (c->fp->program.Base.InputsRead &
 129                       (1 << FRAG_ATTRIB_WPOS)) != 0;
 130
 131    if (intel->gen >= 6) {
 132       /* R0-1: masks, pixel X/Y coordinates. */
 133       c->nr_payload_regs = 2;
 134       /* R2: only for 32-pixel dispatch.*/
 135       /* R3-4: perspective pixel location barycentric */
 136       c->nr_payload_regs += 2;
 137       /* R5-6: perspective pixel location bary for dispatch width != 8 */
 138       if (c->dispatch_width == 16) {
 139          c->nr_payload_regs += 2;
 140       }
 141       /* R7-10: perspective centroid barycentric */
 142       /* R11-14: perspective sample barycentric */
 143       /* R15-18: linear pixel location barycentric */
 144       /* R19-22: linear centroid barycentric */
 145       /* R23-26: linear sample barycentric */
 146
 147       /* R27: interpolated depth if uses source depth */
 148       if (uses_depth) {
 149          c->source_depth_reg = c->nr_payload_regs;
 150          c->nr_payload_regs++;
 151          if (c->dispatch_width == 16) {
 152             /* R28: interpolated depth if not 8-wide. */
 153             c->nr_payload_regs++;
 154          }
 155       }
 156       /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W.
 157        */
 158       if (uses_depth) {
 159          c->source_w_reg = c->nr_payload_regs;
 160          c->nr_payload_regs++;
 161          if (c->dispatch_width == 16) {
 162             /* R30: interpolated W if not 8-wide. */
 163             c->nr_payload_regs++;
 164          }
 165       }
 166       /* R31: MSAA position offsets. */
 167       /* R32-: bary for 32-pixel. */
 168       /* R58-59: interp W for 32-pixel. */
 169
 170       if (c->fp->program.Base.OutputsWritten &
 171           BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
 172          c->source_depth_to_render_target = GL_TRUE;
 173          c->computes_depth = GL_TRUE;
 174       }
 175    } else {
 176       brw_wm_lookup_iz(intel, c);
 177    }
 178 }
 179
 180 /**
 181  * All Mesa program -> GPU code generation goes through this function.
 182  * Depending on the instructions used (i.e. flow control instructions)
 183  * we'll use one of two code generators.
 184  */
 185 static void do_wm_prog( struct brw_context *brw,
 186                         struct brw_fragment_program *fp,
 187                         struct brw_wm_prog_key *key)
 188 {
 189    struct intel_context *intel = &brw->intel;
 190    struct brw_wm_compile *c;
 191    const GLuint *program;
 192    GLuint program_size;
 193
 194    c = brw->wm.compile_data;
 195    if (c == NULL) {
 196       brw->wm.compile_data = calloc(1, sizeof(*brw->wm.compile_data));
 197       c = brw->wm.compile_data;
 198       if (c == NULL) {
 199          /* Ouch - big out of memory problem.  Can't continue
 200           * without triggering a segfault, no way to signal,
 201           * so just return.
 202           */
 203          return;
 204       }
 205       c->instruction = calloc(1, BRW_WM_MAX_INSN * sizeof(*c->instruction));
 206       c->prog_instructions = calloc(1, BRW_WM_MAX_INSN *
 207                                           sizeof(*c->prog_instructions));
 208       c->vreg = calloc(1, BRW_WM_MAX_VREG * sizeof(*c->vreg));
 209       c->refs = calloc(1, BRW_WM_MAX_REF * sizeof(*c->refs));
 210    } else {
 211       void *instruction = c->instruction;
 212       void *prog_instructions = c->prog_instructions;
 213       void *vreg = c->vreg;
 214       void *refs = c->refs;
 215       memset(c, 0, sizeof(*brw->wm.compile_data));
 216       c->instruction = instruction;
 217       c->prog_instructions = prog_instructions;
 218       c->vreg = vreg;
 219       c->refs = refs;
 220    }
 221    memcpy(&c->key, key, sizeof(*key));
 222
 223    c->fp = fp;
 224    c->env_param = brw->intel.ctx.FragmentProgram.Parameters;
 225
 226    brw_init_compile(brw, &c->func);
 227
 228    if (!brw_wm_fs_emit(brw, c)) {
 229       /* Fallback for fixed function and ARB_fp shaders. */
 230       c->dispatch_width = 16;
 231       brw_wm_payload_setup(brw, c);
 232       brw_wm_non_glsl_emit(brw, c);
 233       c->prog_data.dispatch_width = 16;
 234    }
 235
 236    /* Scratch space is used for register spilling */
 237    if (c->last_scratch) {
 238       uint32_t total_scratch;
 239
 240       /* Per-thread scratch space is power-of-two sized. */
 241       for (c->prog_data.total_scratch = 1024;
 242            c->prog_data.total_scratch <= c->last_scratch;
 243            c->prog_data.total_scratch *= 2) {
 244          /* empty */
 245       }
 246       total_scratch = c->prog_data.total_scratch * brw->wm_max_threads;
 247
 248       if (brw->wm.scratch_bo && total_scratch > brw->wm.scratch_bo->size) {
 249          drm_intel_bo_unreference(brw->wm.scratch_bo);
 250          brw->wm.scratch_bo = NULL;
 251       }
 252       if (brw->wm.scratch_bo == NULL) {
 253          brw->wm.scratch_bo = drm_intel_bo_alloc(intel->bufmgr,
 254                                                  "wm scratch",
 255                                                  total_scratch,
 256                                                  4096);
 257       }
 258    }
 259    else {
 260       c->prog_data.total_scratch = 0;
 261    }
 262
 263    if (unlikely(INTEL_DEBUG & DEBUG_WM))
 264       fprintf(stderr, "\n");
 265
 266    /* get the program
 267     */
 268    program = brw_get_program(&c->func, &program_size);
 269
 270    drm_intel_bo_unreference(brw->wm.prog_bo);
 271    brw->wm.prog_bo = brw_upload_cache(&brw->cache, BRW_WM_PROG,
 272                                       &c->key, sizeof(c->key),
 273                                       program, program_size,
 274                                       &c->prog_data, sizeof(c->prog_data),
 275                                       &brw->wm.prog_data);
 276 }
 277
 278
 279
 280 static void brw_wm_populate_key( struct brw_context *brw,
 281                                  struct brw_wm_prog_key *key )
 282 {
 283    struct gl_context *ctx = &brw->intel.ctx;
 284    /* BRW_NEW_FRAGMENT_PROGRAM */
 285    const struct brw_fragment_program *fp =
 286       (struct brw_fragment_program *)brw->fragment_program;
 287    GLuint lookup = 0;
 288    GLuint line_aa;
 289    GLuint i;
 290
 291    memset(key, 0, sizeof(*key));
 292
 293    /* Build the index for table lookup
 294     */
 295    /* _NEW_COLOR */
 296    key->alpha_test = ctx->Color.AlphaEnabled;
 297    if (fp->program.UsesKill ||
 298        ctx->Color.AlphaEnabled)
 299       lookup |= IZ_PS_KILL_ALPHATEST_BIT;
 300
 301    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 302       lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
 303
 304    /* _NEW_DEPTH */
 305    if (ctx->Depth.Test)
 306       lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
 307
 308    if (ctx->Depth.Test &&
 309        ctx->Depth.Mask) /* ?? */
 310       lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
 311
 312    /* _NEW_STENCIL */
 313    if (ctx->Stencil._Enabled) {
 314       lookup |= IZ_STENCIL_TEST_ENABLE_BIT;
 315
 316       if (ctx->Stencil.WriteMask[0] ||
 317           ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
 318          lookup |= IZ_STENCIL_WRITE_ENABLE_BIT;
 319    }
 320
 321    line_aa = AA_NEVER;
 322
 323    /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */
 324    if (ctx->Line.SmoothFlag) {
 325       if (brw->intel.reduced_primitive == GL_LINES) {
 326          line_aa = AA_ALWAYS;
 327       }
 328       else if (brw->intel.reduced_primitive == GL_TRIANGLES) {
 329          if (ctx->Polygon.FrontMode == GL_LINE) {
 330             line_aa = AA_SOMETIMES;
 331
 332             if (ctx->Polygon.BackMode == GL_LINE ||
 333                 (ctx->Polygon.CullFlag &&
 334                  ctx->Polygon.CullFaceMode == GL_BACK))
 335                line_aa = AA_ALWAYS;
 336          }
 337          else if (ctx->Polygon.BackMode == GL_LINE) {
 338             line_aa = AA_SOMETIMES;
 339
 340             if ((ctx->Polygon.CullFlag &&
 341                  ctx->Polygon.CullFaceMode == GL_FRONT))
 342                line_aa = AA_ALWAYS;
 343          }
 344       }
 345    }
 346
 347    key->iz_lookup = lookup;
 348    key->line_aa = line_aa;
 349    key->stats_wm = brw->intel.stats_wm;
 350
 351    /* BRW_NEW_WM_INPUT_DIMENSIONS */
 352    key->proj_attrib_mask = brw->wm.input_size_masks[4-1];
 353
 354    /* _NEW_LIGHT */
 355    key->flat_shade = (ctx->Light.ShadeModel == GL_FLAT);
 356
 357    /* _NEW_HINT */
 358    key->linear_color = (ctx->Hint.PerspectiveCorrection == GL_FASTEST);
 359
 360    /* _NEW_FRAG_CLAMP | _NEW_BUFFERS */
 361    key->clamp_fragment_color = ctx->Color._ClampFragmentColor;
 362
 363    /* _NEW_TEXTURE */
 364    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 365       const struct gl_texture_unit *unit = &ctx->Texture.Unit[i];
 366
 367       if (unit->_ReallyEnabled) {
 368          const struct gl_texture_object *t = unit->_Current;
 369          const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
 370          struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, i);
 371          int swizzles[SWIZZLE_NIL + 1] = {
 372             SWIZZLE_X,
 373             SWIZZLE_Y,
 374             SWIZZLE_Z,
 375             SWIZZLE_W,
 376             SWIZZLE_ZERO,
 377             SWIZZLE_ONE,
 378             SWIZZLE_NIL
 379          };
 380
 381          /* GL_DEPTH_TEXTURE_MODE is normally handled through
 382           * brw_wm_surface_state, but it applies to shadow compares as
 383           * well and our shadow compares always return the result in
 384           * all 4 channels.
 385           */
 386          if (sampler->CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB) {
 387             if (sampler->DepthMode == GL_ALPHA) {
 388                swizzles[0] = SWIZZLE_ZERO;
 389                swizzles[1] = SWIZZLE_ZERO;
 390                swizzles[2] = SWIZZLE_ZERO;
 391             } else if (sampler->DepthMode == GL_LUMINANCE) {
 392                swizzles[3] = SWIZZLE_ONE;
 393             } else if (sampler->DepthMode == GL_RED) {
 394                /* See table 3.23 of the GL 3.0 spec. */
 395                swizzles[1] = SWIZZLE_ZERO;
 396                swizzles[2] = SWIZZLE_ZERO;
 397                swizzles[3] = SWIZZLE_ONE;
 398             }
 399          }
 400
 401          if (img->InternalFormat == GL_YCBCR_MESA) {
 402             key->yuvtex_mask |= 1 << i;
 403             if (img->TexFormat == MESA_FORMAT_YCBCR)
 404                 key->yuvtex_swap_mask |= 1 << i;
 405          }
 406
 407          key->tex_swizzles[i] =
 408             MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
 409                           swizzles[GET_SWZ(t->_Swizzle, 1)],
 410                           swizzles[GET_SWZ(t->_Swizzle, 2)],
 411                           swizzles[GET_SWZ(t->_Swizzle, 3)]);
 412       }
 413       else {
 414          key->tex_swizzles[i] = SWIZZLE_NOOP;
 415       }
 416    }
 417
 418    /* Shadow */
 419    key->shadowtex_mask = fp->program.Base.ShadowSamplers;
 420
 421    /* _NEW_BUFFERS */
 422    /*
 423     * Include the draw buffer origin and height so that we can calculate
 424     * fragment position values relative to the bottom left of the drawable,
 425     * from the incoming screen origin relative position we get as part of our
 426     * payload.
 427     *
 428     * This is only needed for the WM_WPOSXY opcode when the fragment program
 429     * uses the gl_FragCoord input.
 430     *
 431     * We could avoid recompiling by including this as a constant referenced by
 432     * our program, but if we were to do that it would also be nice to handle
 433     * getting that constant updated at batchbuffer submit time (when we
 434     * hold the lock and know where the buffer really is) rather than at emit
 435     * time when we don't hold the lock and are just guessing.  We could also
 436     * just avoid using this as key data if the program doesn't use
 437     * fragment.position.
 438     *
 439     * For DRI2 the origin_x/y will always be (0,0) but we still need the
 440     * drawable height in order to invert the Y axis.
 441     */
 442    if (fp->program.Base.InputsRead & FRAG_BIT_WPOS) {
 443       key->drawable_height = ctx->DrawBuffer->Height;
 444       key->render_to_fbo = ctx->DrawBuffer->Name != 0;
 445    }
 446
 447    /* _NEW_BUFFERS */
 448    key->nr_color_regions = ctx->DrawBuffer->_NumColorDrawBuffers;
 449
 450    /* CACHE_NEW_VS_PROG */
 451    key->vp_outputs_written = brw->vs.prog_data->outputs_written;
 452
 453    /* The unique fragment program ID */
 454    key->program_string_id = fp->id;
 455 }
 456
 457
 458 static void brw_prepare_wm_prog(struct brw_context *brw)
 459 {
 460    struct brw_wm_prog_key key;
 461    struct brw_fragment_program *fp = (struct brw_fragment_program *)
 462       brw->fragment_program;
 463
 464    brw_wm_populate_key(brw, &key);
 465
 466    /* Make an early check for the key.
 467     */
 468    drm_intel_bo_unreference(brw->wm.prog_bo);
 469    brw->wm.prog_bo = brw_search_cache(&brw->cache, BRW_WM_PROG,
 470                                       &key, sizeof(key),
 471                                       &brw->wm.prog_data);
 472    if (brw->wm.prog_bo == NULL)
 473       do_wm_prog(brw, fp, &key);
 474 }
 475
 476
 477 const struct brw_tracked_state brw_wm_prog = {
 478    .dirty = {
 479       .mesa  = (_NEW_COLOR |
 480                 _NEW_DEPTH |
 481                 _NEW_HINT |
 482                 _NEW_STENCIL |
 483                 _NEW_POLYGON |
 484                 _NEW_LINE |
 485                 _NEW_LIGHT |
 486                 _NEW_FRAG_CLAMP |
 487                 _NEW_BUFFERS |
 488                 _NEW_TEXTURE),
 489       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 490                 BRW_NEW_WM_INPUT_DIMENSIONS |
 491                 BRW_NEW_REDUCED_PRIMITIVE),
 492       .cache = CACHE_NEW_VS_PROG,
 493    },
 494    .prepare = brw_prepare_wm_prog
 495 };
 496