src/mesa/drivers/dri/i965/brw_wm.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "brw_context.h"
  33 #include "brw_wm.h"
  34 #include "brw_state.h"
  35 #include "main/formats.h"
  36 #include "main/samplerobj.h"
  37 #include "program/prog_parameter.h"
  38
  39 #include "../glsl/ralloc.h"
  40
  41 /** Return number of src args for given instruction */
  42 GLuint brw_wm_nr_args( GLuint opcode )
  43 {
  44    switch (opcode) {
  45    case WM_FRONTFACING:
  46    case WM_PIXELXY:
  47       return 0;
  48    case WM_CINTERP:
  49    case WM_WPOSXY:
  50    case WM_DELTAXY:
  51       return 1;
  52    case WM_LINTERP:
  53    case WM_PIXELW:
  54       return 2;
  55    case WM_FB_WRITE:
  56    case WM_PINTERP:
  57       return 3;
  58    default:
  59       assert(opcode < MAX_OPCODE);
  60       return _mesa_num_inst_src_regs(opcode);
  61    }
  62 }
  63
  64
  65 GLuint brw_wm_is_scalar_result( GLuint opcode )
  66 {
  67    switch (opcode) {
  68    case OPCODE_COS:
  69    case OPCODE_EX2:
  70    case OPCODE_LG2:
  71    case OPCODE_POW:
  72    case OPCODE_RCP:
  73    case OPCODE_RSQ:
  74    case OPCODE_SIN:
  75    case OPCODE_DP2:
  76    case OPCODE_DP3:
  77    case OPCODE_DP4:
  78    case OPCODE_DPH:
  79    case OPCODE_DST:
  80       return 1;
  81
  82    default:
  83       return 0;
  84    }
  85 }
  86
  87
  88 /**
  89  * Do GPU code generation for non-GLSL shader.  non-GLSL shaders have
  90  * no flow control instructions so we can more readily do SSA-style
  91  * optimizations.
  92  */
  93 static void
  94 brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
  95 {
  96    /* Augment fragment program.  Add instructions for pre- and
  97     * post-fragment-program tasks such as interpolation and fogging.
  98     */
  99    brw_wm_pass_fp(c);
 100
 101    /* Translate to intermediate representation.  Build register usage
 102     * chains.
 103     */
 104    brw_wm_pass0(c);
 105
 106    /* Dead code removal.
 107     */
 108    brw_wm_pass1(c);
 109
 110    /* Register allocation.
 111     * Divide by two because we operate on 16 pixels at a time and require
 112     * two GRF entries for each logical shader register.
 113     */
 114    c->grf_limit = BRW_WM_MAX_GRF / 2;
 115
 116    brw_wm_pass2(c);
 117
 118    /* how many general-purpose registers are used */
 119    c->prog_data.reg_blocks = brw_register_blocks(c->max_wm_grf);
 120
 121    /* Emit GEN4 code.
 122     */
 123    brw_wm_emit(c);
 124 }
 125
 126 void
 127 brw_wm_payload_setup(struct brw_context *brw,
 128                      struct brw_wm_compile *c)
 129 {
 130    struct intel_context *intel = &brw->intel;
 131    bool uses_depth = (c->fp->program.Base.InputsRead &
 132                       (1 << FRAG_ATTRIB_WPOS)) != 0;
 133
 134    if (intel->gen >= 6) {
 135       /* R0-1: masks, pixel X/Y coordinates. */
 136       c->nr_payload_regs = 2;
 137       /* R2: only for 32-pixel dispatch.*/
 138       /* R3-4: perspective pixel location barycentric */
 139       c->nr_payload_regs += 2;
 140       /* R5-6: perspective pixel location bary for dispatch width != 8 */
 141       if (c->dispatch_width == 16) {
 142          c->nr_payload_regs += 2;
 143       }
 144       /* R7-10: perspective centroid barycentric */
 145       /* R11-14: perspective sample barycentric */
 146       /* R15-18: linear pixel location barycentric */
 147       /* R19-22: linear centroid barycentric */
 148       /* R23-26: linear sample barycentric */
 149
 150       /* R27: interpolated depth if uses source depth */
 151       if (uses_depth) {
 152          c->source_depth_reg = c->nr_payload_regs;
 153          c->nr_payload_regs++;
 154          if (c->dispatch_width == 16) {
 155             /* R28: interpolated depth if not 8-wide. */
 156             c->nr_payload_regs++;
 157          }
 158       }
 159       /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W.
 160        */
 161       if (uses_depth) {
 162          c->source_w_reg = c->nr_payload_regs;
 163          c->nr_payload_regs++;
 164          if (c->dispatch_width == 16) {
 165             /* R30: interpolated W if not 8-wide. */
 166             c->nr_payload_regs++;
 167          }
 168       }
 169       /* R31: MSAA position offsets. */
 170       /* R32-: bary for 32-pixel. */
 171       /* R58-59: interp W for 32-pixel. */
 172
 173       if (c->fp->program.Base.OutputsWritten &
 174           BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
 175          c->source_depth_to_render_target = GL_TRUE;
 176          c->computes_depth = GL_TRUE;
 177       }
 178    } else {
 179       brw_wm_lookup_iz(intel, c);
 180    }
 181 }
 182
 183 /**
 184  * All Mesa program -> GPU code generation goes through this function.
 185  * Depending on the instructions used (i.e. flow control instructions)
 186  * we'll use one of two code generators.
 187  */
 188 bool do_wm_prog(struct brw_context *brw,
 189                 struct gl_shader_program *prog,
 190                 struct brw_fragment_program *fp,
 191                 struct brw_wm_prog_key *key)
 192 {
 193    struct intel_context *intel = &brw->intel;
 194    struct brw_wm_compile *c;
 195    const GLuint *program;
 196    GLuint program_size;
 197
 198    c = brw->wm.compile_data;
 199    if (c == NULL) {
 200       brw->wm.compile_data = rzalloc(NULL, struct brw_wm_compile);
 201       c = brw->wm.compile_data;
 202       if (c == NULL) {
 203          /* Ouch - big out of memory problem.  Can't continue
 204           * without triggering a segfault, no way to signal,
 205           * so just return.
 206           */
 207          return false;
 208       }
 209    } else {
 210       void *instruction = c->instruction;
 211       void *prog_instructions = c->prog_instructions;
 212       void *vreg = c->vreg;
 213       void *refs = c->refs;
 214       memset(c, 0, sizeof(*brw->wm.compile_data));
 215       c->instruction = instruction;
 216       c->prog_instructions = prog_instructions;
 217       c->vreg = vreg;
 218       c->refs = refs;
 219    }
 220    memcpy(&c->key, key, sizeof(*key));
 221
 222    c->fp = fp;
 223    c->env_param = brw->intel.ctx.FragmentProgram.Parameters;
 224
 225    brw_init_compile(brw, &c->func, c);
 226
 227    if (prog && prog->FragmentProgram) {
 228       if (!brw_wm_fs_emit(brw, c, prog))
 229          return false;
 230    } else {
 231       if (!c->instruction) {
 232          c->instruction = rzalloc_array(c, struct brw_wm_instruction, BRW_WM_MAX_INSN);
 233          c->prog_instructions = rzalloc_array(c, struct prog_instruction, BRW_WM_MAX_INSN);
 234          c->vreg = rzalloc_array(c, struct brw_wm_value, BRW_WM_MAX_VREG);
 235          c->refs = rzalloc_array(c, struct brw_wm_ref, BRW_WM_MAX_REF);
 236       }
 237
 238       /* Fallback for fixed function and ARB_fp shaders. */
 239       c->dispatch_width = 16;
 240       brw_wm_payload_setup(brw, c);
 241       brw_wm_non_glsl_emit(brw, c);
 242       c->prog_data.dispatch_width = 16;
 243    }
 244
 245    /* Scratch space is used for register spilling */
 246    if (c->last_scratch) {
 247       c->prog_data.total_scratch = brw_get_scratch_size(c->last_scratch);
 248
 249       brw_get_scratch_bo(intel, &brw->wm.scratch_bo,
 250                          c->prog_data.total_scratch * brw->wm_max_threads);
 251    }
 252
 253    if (unlikely(INTEL_DEBUG & DEBUG_WM))
 254       fprintf(stderr, "\n");
 255
 256    /* get the program
 257     */
 258    program = brw_get_program(&c->func, &program_size);
 259
 260    brw_upload_cache(&brw->cache, BRW_WM_PROG,
 261                     &c->key, sizeof(c->key),
 262                     program, program_size,
 263                     &c->prog_data, sizeof(c->prog_data),
 264                     &brw->wm.prog_offset, &brw->wm.prog_data);
 265
 266    return true;
 267 }
 268
 269
 270
 271 static void brw_wm_populate_key( struct brw_context *brw,
 272                                  struct brw_wm_prog_key *key )
 273 {
 274    struct gl_context *ctx = &brw->intel.ctx;
 275    /* BRW_NEW_FRAGMENT_PROGRAM */
 276    const struct brw_fragment_program *fp =
 277       (struct brw_fragment_program *)brw->fragment_program;
 278    GLuint lookup = 0;
 279    GLuint line_aa;
 280    GLuint i;
 281
 282    memset(key, 0, sizeof(*key));
 283
 284    /* Build the index for table lookup
 285     */
 286    /* _NEW_COLOR */
 287    key->alpha_test = ctx->Color.AlphaEnabled;
 288    if (fp->program.UsesKill ||
 289        ctx->Color.AlphaEnabled)
 290       lookup |= IZ_PS_KILL_ALPHATEST_BIT;
 291
 292    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 293       lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
 294
 295    /* _NEW_DEPTH */
 296    if (ctx->Depth.Test)
 297       lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
 298
 299    if (ctx->Depth.Test &&
 300        ctx->Depth.Mask) /* ?? */
 301       lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
 302
 303    /* _NEW_STENCIL */
 304    if (ctx->Stencil._Enabled) {
 305       lookup |= IZ_STENCIL_TEST_ENABLE_BIT;
 306
 307       if (ctx->Stencil.WriteMask[0] ||
 308           ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
 309          lookup |= IZ_STENCIL_WRITE_ENABLE_BIT;
 310    }
 311
 312    line_aa = AA_NEVER;
 313
 314    /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */
 315    if (ctx->Line.SmoothFlag) {
 316       if (brw->intel.reduced_primitive == GL_LINES) {
 317          line_aa = AA_ALWAYS;
 318       }
 319       else if (brw->intel.reduced_primitive == GL_TRIANGLES) {
 320          if (ctx->Polygon.FrontMode == GL_LINE) {
 321             line_aa = AA_SOMETIMES;
 322
 323             if (ctx->Polygon.BackMode == GL_LINE ||
 324                 (ctx->Polygon.CullFlag &&
 325                  ctx->Polygon.CullFaceMode == GL_BACK))
 326                line_aa = AA_ALWAYS;
 327          }
 328          else if (ctx->Polygon.BackMode == GL_LINE) {
 329             line_aa = AA_SOMETIMES;
 330
 331             if ((ctx->Polygon.CullFlag &&
 332                  ctx->Polygon.CullFaceMode == GL_FRONT))
 333                line_aa = AA_ALWAYS;
 334          }
 335       }
 336    }
 337
 338    key->iz_lookup = lookup;
 339    key->line_aa = line_aa;
 340    key->stats_wm = brw->intel.stats_wm;
 341
 342    /* BRW_NEW_WM_INPUT_DIMENSIONS */
 343    key->proj_attrib_mask = brw->wm.input_size_masks[4-1];
 344
 345    /* _NEW_LIGHT */
 346    key->flat_shade = (ctx->Light.ShadeModel == GL_FLAT);
 347
 348    /* _NEW_FRAG_CLAMP | _NEW_BUFFERS */
 349    key->clamp_fragment_color = ctx->Color._ClampFragmentColor;
 350
 351    /* _NEW_TEXTURE */
 352    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 353       const struct gl_texture_unit *unit = &ctx->Texture.Unit[i];
 354
 355       if (unit->_ReallyEnabled) {
 356          const struct gl_texture_object *t = unit->_Current;
 357          const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
 358          struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, i);
 359          int swizzles[SWIZZLE_NIL + 1] = {
 360             SWIZZLE_X,
 361             SWIZZLE_Y,
 362             SWIZZLE_Z,
 363             SWIZZLE_W,
 364             SWIZZLE_ZERO,
 365             SWIZZLE_ONE,
 366             SWIZZLE_NIL
 367          };
 368
 369          /* GL_DEPTH_TEXTURE_MODE is normally handled through
 370           * brw_wm_surface_state, but it applies to shadow compares as
 371           * well and our shadow compares always return the result in
 372           * all 4 channels.
 373           */
 374          if (sampler->CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB) {
 375             key->compare_funcs[i] = sampler->CompareFunc;
 376
 377             if (sampler->DepthMode == GL_ALPHA) {
 378                swizzles[0] = SWIZZLE_ZERO;
 379                swizzles[1] = SWIZZLE_ZERO;
 380                swizzles[2] = SWIZZLE_ZERO;
 381             } else if (sampler->DepthMode == GL_LUMINANCE) {
 382                swizzles[3] = SWIZZLE_ONE;
 383             } else if (sampler->DepthMode == GL_RED) {
 384                /* See table 3.23 of the GL 3.0 spec. */
 385                swizzles[1] = SWIZZLE_ZERO;
 386                swizzles[2] = SWIZZLE_ZERO;
 387                swizzles[3] = SWIZZLE_ONE;
 388             }
 389          }
 390
 391          if (img->InternalFormat == GL_YCBCR_MESA) {
 392             key->yuvtex_mask |= 1 << i;
 393             if (img->TexFormat == MESA_FORMAT_YCBCR)
 394                 key->yuvtex_swap_mask |= 1 << i;
 395          }
 396
 397          key->tex_swizzles[i] =
 398             MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
 399                           swizzles[GET_SWZ(t->_Swizzle, 1)],
 400                           swizzles[GET_SWZ(t->_Swizzle, 2)],
 401                           swizzles[GET_SWZ(t->_Swizzle, 3)]);
 402
 403          if (sampler->MinFilter != GL_NEAREST &&
 404              sampler->MagFilter != GL_NEAREST) {
 405             if (sampler->WrapS == GL_CLAMP)
 406                key->gl_clamp_mask[0] |= 1 << i;
 407             if (sampler->WrapT == GL_CLAMP)
 408                key->gl_clamp_mask[1] |= 1 << i;
 409             if (sampler->WrapR == GL_CLAMP)
 410                key->gl_clamp_mask[2] |= 1 << i;
 411          }
 412       }
 413       else {
 414          key->tex_swizzles[i] = SWIZZLE_NOOP;
 415       }
 416    }
 417
 418    /* _NEW_BUFFERS */
 419    /*
 420     * Include the draw buffer origin and height so that we can calculate
 421     * fragment position values relative to the bottom left of the drawable,
 422     * from the incoming screen origin relative position we get as part of our
 423     * payload.
 424     *
 425     * This is only needed for the WM_WPOSXY opcode when the fragment program
 426     * uses the gl_FragCoord input.
 427     *
 428     * We could avoid recompiling by including this as a constant referenced by
 429     * our program, but if we were to do that it would also be nice to handle
 430     * getting that constant updated at batchbuffer submit time (when we
 431     * hold the lock and know where the buffer really is) rather than at emit
 432     * time when we don't hold the lock and are just guessing.  We could also
 433     * just avoid using this as key data if the program doesn't use
 434     * fragment.position.
 435     *
 436     * For DRI2 the origin_x/y will always be (0,0) but we still need the
 437     * drawable height in order to invert the Y axis.
 438     */
 439    if (fp->program.Base.InputsRead & FRAG_BIT_WPOS) {
 440       key->drawable_height = ctx->DrawBuffer->Height;
 441       key->render_to_fbo = ctx->DrawBuffer->Name != 0;
 442    }
 443
 444    /* _NEW_BUFFERS */
 445    key->nr_color_regions = ctx->DrawBuffer->_NumColorDrawBuffers;
 446
 447    /* CACHE_NEW_VS_PROG */
 448    key->vp_outputs_written = brw->vs.prog_data->outputs_written;
 449
 450    /* The unique fragment program ID */
 451    key->program_string_id = fp->id;
 452 }
 453
 454
 455 static void brw_prepare_wm_prog(struct brw_context *brw)
 456 {
 457    struct intel_context *intel = &brw->intel;
 458    struct gl_context *ctx = &intel->ctx;
 459    struct brw_wm_prog_key key;
 460    struct brw_fragment_program *fp = (struct brw_fragment_program *)
 461       brw->fragment_program;
 462
 463    brw_wm_populate_key(brw, &key);
 464
 465    if (!brw_search_cache(&brw->cache, BRW_WM_PROG,
 466                          &key, sizeof(key),
 467                          &brw->wm.prog_offset, &brw->wm.prog_data)) {
 468       bool success = do_wm_prog(brw, ctx->Shader.CurrentFragmentProgram, fp,
 469                                 &key);
 470       assert(success);
 471    }
 472 }
 473
 474
 475 const struct brw_tracked_state brw_wm_prog = {
 476    .dirty = {
 477       .mesa  = (_NEW_COLOR |
 478                 _NEW_DEPTH |
 479                 _NEW_STENCIL |
 480                 _NEW_POLYGON |
 481                 _NEW_LINE |
 482                 _NEW_LIGHT |
 483                 _NEW_FRAG_CLAMP |
 484                 _NEW_BUFFERS |
 485                 _NEW_TEXTURE),
 486       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 487                 BRW_NEW_WM_INPUT_DIMENSIONS |
 488                 BRW_NEW_REDUCED_PRIMITIVE),
 489       .cache = CACHE_NEW_VS_PROG,
 490    },
 491    .prepare = brw_prepare_wm_prog
 492 };
 493