2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #include "brw_context.h"
34 #include "brw_state.h"
35 #include "main/formats.h"
36 #include "main/samplerobj.h"
38 #include "../glsl/ralloc.h"
40 /** Return number of src args for given instruction */
41 GLuint
brw_wm_nr_args( GLuint opcode
)
58 assert(opcode
< MAX_OPCODE
);
59 return _mesa_num_inst_src_regs(opcode
);
64 GLuint
brw_wm_is_scalar_result( GLuint opcode
)
88 * Do GPU code generation for non-GLSL shader. non-GLSL shaders have
89 * no flow control instructions so we can more readily do SSA-style
93 brw_wm_non_glsl_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
95 /* Augment fragment program. Add instructions for pre- and
96 * post-fragment-program tasks such as interpolation and fogging.
100 /* Translate to intermediate representation. Build register usage
105 /* Dead code removal.
109 /* Register allocation.
110 * Divide by two because we operate on 16 pixels at a time and require
111 * two GRF entries for each logical shader register.
113 c
->grf_limit
= BRW_WM_MAX_GRF
/ 2;
117 /* how many general-purpose registers are used */
118 c
->prog_data
.total_grf
= c
->max_wm_grf
;
126 brw_wm_payload_setup(struct brw_context
*brw
,
127 struct brw_wm_compile
*c
)
129 struct intel_context
*intel
= &brw
->intel
;
130 bool uses_depth
= (c
->fp
->program
.Base
.InputsRead
&
131 (1 << FRAG_ATTRIB_WPOS
)) != 0;
133 if (intel
->gen
>= 6) {
134 /* R0-1: masks, pixel X/Y coordinates. */
135 c
->nr_payload_regs
= 2;
136 /* R2: only for 32-pixel dispatch.*/
137 /* R3-4: perspective pixel location barycentric */
138 c
->nr_payload_regs
+= 2;
139 /* R5-6: perspective pixel location bary for dispatch width != 8 */
140 if (c
->dispatch_width
== 16) {
141 c
->nr_payload_regs
+= 2;
143 /* R7-10: perspective centroid barycentric */
144 /* R11-14: perspective sample barycentric */
145 /* R15-18: linear pixel location barycentric */
146 /* R19-22: linear centroid barycentric */
147 /* R23-26: linear sample barycentric */
149 /* R27: interpolated depth if uses source depth */
151 c
->source_depth_reg
= c
->nr_payload_regs
;
152 c
->nr_payload_regs
++;
153 if (c
->dispatch_width
== 16) {
154 /* R28: interpolated depth if not 8-wide. */
155 c
->nr_payload_regs
++;
158 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W.
161 c
->source_w_reg
= c
->nr_payload_regs
;
162 c
->nr_payload_regs
++;
163 if (c
->dispatch_width
== 16) {
164 /* R30: interpolated W if not 8-wide. */
165 c
->nr_payload_regs
++;
168 /* R31: MSAA position offsets. */
169 /* R32-: bary for 32-pixel. */
170 /* R58-59: interp W for 32-pixel. */
172 if (c
->fp
->program
.Base
.OutputsWritten
&
173 BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
174 c
->source_depth_to_render_target
= GL_TRUE
;
175 c
->computes_depth
= GL_TRUE
;
178 brw_wm_lookup_iz(intel
, c
);
183 * All Mesa program -> GPU code generation goes through this function.
184 * Depending on the instructions used (i.e. flow control instructions)
185 * we'll use one of two code generators.
187 static void do_wm_prog( struct brw_context
*brw
,
188 struct brw_fragment_program
*fp
,
189 struct brw_wm_prog_key
*key
)
191 struct intel_context
*intel
= &brw
->intel
;
192 struct brw_wm_compile
*c
;
193 const GLuint
*program
;
196 c
= brw
->wm
.compile_data
;
198 brw
->wm
.compile_data
= rzalloc(NULL
, struct brw_wm_compile
);
199 c
= brw
->wm
.compile_data
;
201 /* Ouch - big out of memory problem. Can't continue
202 * without triggering a segfault, no way to signal,
207 c
->instruction
= rzalloc_array(c
, struct brw_wm_instruction
, BRW_WM_MAX_INSN
);
208 c
->prog_instructions
= rzalloc_array(c
, struct prog_instruction
, BRW_WM_MAX_INSN
);
209 c
->vreg
= rzalloc_array(c
, struct brw_wm_value
, BRW_WM_MAX_VREG
);
210 c
->refs
= rzalloc_array(c
, struct brw_wm_ref
, BRW_WM_MAX_REF
);
212 void *instruction
= c
->instruction
;
213 void *prog_instructions
= c
->prog_instructions
;
214 void *vreg
= c
->vreg
;
215 void *refs
= c
->refs
;
216 memset(c
, 0, sizeof(*brw
->wm
.compile_data
));
217 c
->instruction
= instruction
;
218 c
->prog_instructions
= prog_instructions
;
222 memcpy(&c
->key
, key
, sizeof(*key
));
225 c
->env_param
= brw
->intel
.ctx
.FragmentProgram
.Parameters
;
227 brw_init_compile(brw
, &c
->func
, c
);
229 if (!brw_wm_fs_emit(brw
, c
)) {
230 /* Fallback for fixed function and ARB_fp shaders. */
231 c
->dispatch_width
= 16;
232 brw_wm_payload_setup(brw
, c
);
233 brw_wm_non_glsl_emit(brw
, c
);
234 c
->prog_data
.dispatch_width
= 16;
237 /* Scratch space is used for register spilling */
238 if (c
->last_scratch
) {
239 uint32_t total_scratch
;
241 /* Per-thread scratch space is power-of-two sized. */
242 for (c
->prog_data
.total_scratch
= 1024;
243 c
->prog_data
.total_scratch
<= c
->last_scratch
;
244 c
->prog_data
.total_scratch
*= 2) {
247 total_scratch
= c
->prog_data
.total_scratch
* brw
->wm_max_threads
;
249 if (brw
->wm
.scratch_bo
&& total_scratch
> brw
->wm
.scratch_bo
->size
) {
250 drm_intel_bo_unreference(brw
->wm
.scratch_bo
);
251 brw
->wm
.scratch_bo
= NULL
;
253 if (brw
->wm
.scratch_bo
== NULL
) {
254 brw
->wm
.scratch_bo
= drm_intel_bo_alloc(intel
->bufmgr
,
261 c
->prog_data
.total_scratch
= 0;
264 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
265 fprintf(stderr
, "\n");
269 program
= brw_get_program(&c
->func
, &program_size
);
271 drm_intel_bo_unreference(brw
->wm
.prog_bo
);
272 brw
->wm
.prog_bo
= brw_upload_cache(&brw
->cache
, BRW_WM_PROG
,
273 &c
->key
, sizeof(c
->key
),
274 program
, program_size
,
275 &c
->prog_data
, sizeof(c
->prog_data
),
281 static void brw_wm_populate_key( struct brw_context
*brw
,
282 struct brw_wm_prog_key
*key
)
284 struct gl_context
*ctx
= &brw
->intel
.ctx
;
285 /* BRW_NEW_FRAGMENT_PROGRAM */
286 const struct brw_fragment_program
*fp
=
287 (struct brw_fragment_program
*)brw
->fragment_program
;
292 memset(key
, 0, sizeof(*key
));
294 /* Build the index for table lookup
297 key
->alpha_test
= ctx
->Color
.AlphaEnabled
;
298 if (fp
->program
.UsesKill
||
299 ctx
->Color
.AlphaEnabled
)
300 lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
302 if (fp
->program
.Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
303 lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
307 lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
309 if (ctx
->Depth
.Test
&&
310 ctx
->Depth
.Mask
) /* ?? */
311 lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
314 if (ctx
->Stencil
._Enabled
) {
315 lookup
|= IZ_STENCIL_TEST_ENABLE_BIT
;
317 if (ctx
->Stencil
.WriteMask
[0] ||
318 ctx
->Stencil
.WriteMask
[ctx
->Stencil
._BackFace
])
319 lookup
|= IZ_STENCIL_WRITE_ENABLE_BIT
;
324 /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */
325 if (ctx
->Line
.SmoothFlag
) {
326 if (brw
->intel
.reduced_primitive
== GL_LINES
) {
329 else if (brw
->intel
.reduced_primitive
== GL_TRIANGLES
) {
330 if (ctx
->Polygon
.FrontMode
== GL_LINE
) {
331 line_aa
= AA_SOMETIMES
;
333 if (ctx
->Polygon
.BackMode
== GL_LINE
||
334 (ctx
->Polygon
.CullFlag
&&
335 ctx
->Polygon
.CullFaceMode
== GL_BACK
))
338 else if (ctx
->Polygon
.BackMode
== GL_LINE
) {
339 line_aa
= AA_SOMETIMES
;
341 if ((ctx
->Polygon
.CullFlag
&&
342 ctx
->Polygon
.CullFaceMode
== GL_FRONT
))
348 key
->iz_lookup
= lookup
;
349 key
->line_aa
= line_aa
;
350 key
->stats_wm
= brw
->intel
.stats_wm
;
352 /* BRW_NEW_WM_INPUT_DIMENSIONS */
353 key
->proj_attrib_mask
= brw
->wm
.input_size_masks
[4-1];
356 key
->flat_shade
= (ctx
->Light
.ShadeModel
== GL_FLAT
);
359 key
->linear_color
= (ctx
->Hint
.PerspectiveCorrection
== GL_FASTEST
);
361 /* _NEW_FRAG_CLAMP | _NEW_BUFFERS */
362 key
->clamp_fragment_color
= ctx
->Color
._ClampFragmentColor
;
365 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
366 const struct gl_texture_unit
*unit
= &ctx
->Texture
.Unit
[i
];
368 if (unit
->_ReallyEnabled
) {
369 const struct gl_texture_object
*t
= unit
->_Current
;
370 const struct gl_texture_image
*img
= t
->Image
[0][t
->BaseLevel
];
371 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, i
);
372 int swizzles
[SWIZZLE_NIL
+ 1] = {
382 /* GL_DEPTH_TEXTURE_MODE is normally handled through
383 * brw_wm_surface_state, but it applies to shadow compares as
384 * well and our shadow compares always return the result in
387 if (sampler
->CompareMode
== GL_COMPARE_R_TO_TEXTURE_ARB
) {
388 if (sampler
->DepthMode
== GL_ALPHA
) {
389 swizzles
[0] = SWIZZLE_ZERO
;
390 swizzles
[1] = SWIZZLE_ZERO
;
391 swizzles
[2] = SWIZZLE_ZERO
;
392 } else if (sampler
->DepthMode
== GL_LUMINANCE
) {
393 swizzles
[3] = SWIZZLE_ONE
;
394 } else if (sampler
->DepthMode
== GL_RED
) {
395 /* See table 3.23 of the GL 3.0 spec. */
396 swizzles
[1] = SWIZZLE_ZERO
;
397 swizzles
[2] = SWIZZLE_ZERO
;
398 swizzles
[3] = SWIZZLE_ONE
;
402 if (img
->InternalFormat
== GL_YCBCR_MESA
) {
403 key
->yuvtex_mask
|= 1 << i
;
404 if (img
->TexFormat
== MESA_FORMAT_YCBCR
)
405 key
->yuvtex_swap_mask
|= 1 << i
;
408 key
->tex_swizzles
[i
] =
409 MAKE_SWIZZLE4(swizzles
[GET_SWZ(t
->_Swizzle
, 0)],
410 swizzles
[GET_SWZ(t
->_Swizzle
, 1)],
411 swizzles
[GET_SWZ(t
->_Swizzle
, 2)],
412 swizzles
[GET_SWZ(t
->_Swizzle
, 3)]);
415 key
->tex_swizzles
[i
] = SWIZZLE_NOOP
;
420 key
->shadowtex_mask
= fp
->program
.Base
.ShadowSamplers
;
424 * Include the draw buffer origin and height so that we can calculate
425 * fragment position values relative to the bottom left of the drawable,
426 * from the incoming screen origin relative position we get as part of our
429 * This is only needed for the WM_WPOSXY opcode when the fragment program
430 * uses the gl_FragCoord input.
432 * We could avoid recompiling by including this as a constant referenced by
433 * our program, but if we were to do that it would also be nice to handle
434 * getting that constant updated at batchbuffer submit time (when we
435 * hold the lock and know where the buffer really is) rather than at emit
436 * time when we don't hold the lock and are just guessing. We could also
437 * just avoid using this as key data if the program doesn't use
440 * For DRI2 the origin_x/y will always be (0,0) but we still need the
441 * drawable height in order to invert the Y axis.
443 if (fp
->program
.Base
.InputsRead
& FRAG_BIT_WPOS
) {
444 key
->drawable_height
= ctx
->DrawBuffer
->Height
;
445 key
->render_to_fbo
= ctx
->DrawBuffer
->Name
!= 0;
449 key
->nr_color_regions
= ctx
->DrawBuffer
->_NumColorDrawBuffers
;
451 /* CACHE_NEW_VS_PROG */
452 key
->vp_outputs_written
= brw
->vs
.prog_data
->outputs_written
;
454 /* The unique fragment program ID */
455 key
->program_string_id
= fp
->id
;
459 static void brw_prepare_wm_prog(struct brw_context
*brw
)
461 struct brw_wm_prog_key key
;
462 struct brw_fragment_program
*fp
= (struct brw_fragment_program
*)
463 brw
->fragment_program
;
465 brw_wm_populate_key(brw
, &key
);
467 /* Make an early check for the key.
469 drm_intel_bo_unreference(brw
->wm
.prog_bo
);
470 brw
->wm
.prog_bo
= brw_search_cache(&brw
->cache
, BRW_WM_PROG
,
473 if (brw
->wm
.prog_bo
== NULL
)
474 do_wm_prog(brw
, fp
, &key
);
478 const struct brw_tracked_state brw_wm_prog
= {
480 .mesa
= (_NEW_COLOR
|
490 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
|
491 BRW_NEW_WM_INPUT_DIMENSIONS
|
492 BRW_NEW_REDUCED_PRIMITIVE
),
493 .cache
= CACHE_NEW_VS_PROG
,
495 .prepare
= brw_prepare_wm_prog