Merge remote branch 'origin/master' into pipe-video
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #include "brw_context.h"
33 #include "brw_wm.h"
34 #include "brw_state.h"
35 #include "main/formats.h"
36
37 /** Return number of src args for given instruction */
38 GLuint brw_wm_nr_args( GLuint opcode )
39 {
40 switch (opcode) {
41 case WM_FRONTFACING:
42 case WM_PIXELXY:
43 return 0;
44 case WM_CINTERP:
45 case WM_WPOSXY:
46 case WM_DELTAXY:
47 return 1;
48 case WM_LINTERP:
49 case WM_PIXELW:
50 return 2;
51 case WM_FB_WRITE:
52 case WM_PINTERP:
53 return 3;
54 default:
55 assert(opcode < MAX_OPCODE);
56 return _mesa_num_inst_src_regs(opcode);
57 }
58 }
59
60
61 GLuint brw_wm_is_scalar_result( GLuint opcode )
62 {
63 switch (opcode) {
64 case OPCODE_COS:
65 case OPCODE_EX2:
66 case OPCODE_LG2:
67 case OPCODE_POW:
68 case OPCODE_RCP:
69 case OPCODE_RSQ:
70 case OPCODE_SIN:
71 case OPCODE_DP2:
72 case OPCODE_DP3:
73 case OPCODE_DP4:
74 case OPCODE_DPH:
75 case OPCODE_DST:
76 return 1;
77
78 default:
79 return 0;
80 }
81 }
82
83
84 /**
85 * Do GPU code generation for non-GLSL shader. non-GLSL shaders have
86 * no flow control instructions so we can more readily do SSA-style
87 * optimizations.
88 */
89 static void
90 brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
91 {
92 /* Augment fragment program. Add instructions for pre- and
93 * post-fragment-program tasks such as interpolation and fogging.
94 */
95 brw_wm_pass_fp(c);
96
97 /* Translate to intermediate representation. Build register usage
98 * chains.
99 */
100 brw_wm_pass0(c);
101
102 /* Dead code removal.
103 */
104 brw_wm_pass1(c);
105
106 /* Register allocation.
107 * Divide by two because we operate on 16 pixels at a time and require
108 * two GRF entries for each logical shader register.
109 */
110 c->grf_limit = BRW_WM_MAX_GRF / 2;
111
112 brw_wm_pass2(c);
113
114 /* how many general-purpose registers are used */
115 c->prog_data.total_grf = c->max_wm_grf;
116
117 /* Emit GEN4 code.
118 */
119 brw_wm_emit(c);
120 }
121
122 static void
123 brw_wm_payload_setup(struct brw_context *brw,
124 struct brw_wm_compile *c)
125 {
126 struct intel_context *intel = &brw->intel;
127 bool uses_depth = (c->fp->program.Base.InputsRead &
128 (1 << FRAG_ATTRIB_WPOS)) != 0;
129
130 if (intel->gen >= 6) {
131 /* R0-1: masks, pixel X/Y coordinates. */
132 c->nr_payload_regs = 2;
133 /* R2: only for 32-pixel dispatch.*/
134 /* R3-4: perspective pixel location barycentric */
135 c->nr_payload_regs += 2;
136 /* R5-6: perspective pixel location bary for dispatch width != 8 */
137 if (c->dispatch_width == 16) {
138 c->nr_payload_regs += 2;
139 }
140 /* R7-10: perspective centroid barycentric */
141 /* R11-14: perspective sample barycentric */
142 /* R15-18: linear pixel location barycentric */
143 /* R19-22: linear centroid barycentric */
144 /* R23-26: linear sample barycentric */
145
146 /* R27: interpolated depth if uses source depth */
147 if (uses_depth) {
148 c->source_depth_reg = c->nr_payload_regs;
149 c->nr_payload_regs++;
150 if (c->dispatch_width == 16) {
151 /* R28: interpolated depth if not 8-wide. */
152 c->nr_payload_regs++;
153 }
154 }
155 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W.
156 */
157 if (uses_depth) {
158 c->source_w_reg = c->nr_payload_regs;
159 c->nr_payload_regs++;
160 if (c->dispatch_width == 16) {
161 /* R30: interpolated W if not 8-wide. */
162 c->nr_payload_regs++;
163 }
164 }
165 /* R31: MSAA position offsets. */
166 /* R32-: bary for 32-pixel. */
167 /* R58-59: interp W for 32-pixel. */
168
169 if (c->fp->program.Base.OutputsWritten &
170 BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
171 c->source_depth_to_render_target = GL_TRUE;
172 c->computes_depth = GL_TRUE;
173 }
174 } else {
175 brw_wm_lookup_iz(intel, c);
176 }
177 }
178
179 /**
180 * All Mesa program -> GPU code generation goes through this function.
181 * Depending on the instructions used (i.e. flow control instructions)
182 * we'll use one of two code generators.
183 */
184 static void do_wm_prog( struct brw_context *brw,
185 struct brw_fragment_program *fp,
186 struct brw_wm_prog_key *key)
187 {
188 struct intel_context *intel = &brw->intel;
189 struct brw_wm_compile *c;
190 const GLuint *program;
191 GLuint program_size;
192
193 c = brw->wm.compile_data;
194 if (c == NULL) {
195 brw->wm.compile_data = calloc(1, sizeof(*brw->wm.compile_data));
196 c = brw->wm.compile_data;
197 if (c == NULL) {
198 /* Ouch - big out of memory problem. Can't continue
199 * without triggering a segfault, no way to signal,
200 * so just return.
201 */
202 return;
203 }
204 c->instruction = calloc(1, BRW_WM_MAX_INSN * sizeof(*c->instruction));
205 c->prog_instructions = calloc(1, BRW_WM_MAX_INSN *
206 sizeof(*c->prog_instructions));
207 c->vreg = calloc(1, BRW_WM_MAX_VREG * sizeof(*c->vreg));
208 c->refs = calloc(1, BRW_WM_MAX_REF * sizeof(*c->refs));
209 } else {
210 void *instruction = c->instruction;
211 void *prog_instructions = c->prog_instructions;
212 void *vreg = c->vreg;
213 void *refs = c->refs;
214 memset(c, 0, sizeof(*brw->wm.compile_data));
215 c->instruction = instruction;
216 c->prog_instructions = prog_instructions;
217 c->vreg = vreg;
218 c->refs = refs;
219 }
220 memcpy(&c->key, key, sizeof(*key));
221
222 c->fp = fp;
223 c->env_param = brw->intel.ctx.FragmentProgram.Parameters;
224
225 brw_init_compile(brw, &c->func);
226
227 brw_wm_payload_setup(brw, c);
228
229 if (!brw_wm_fs_emit(brw, c)) {
230 /*
231 * Shader which use GLSL features such as flow control are handled
232 * differently from "simple" shaders.
233 */
234 c->dispatch_width = 16;
235 brw_wm_payload_setup(brw, c);
236 brw_wm_non_glsl_emit(brw, c);
237 }
238 c->prog_data.dispatch_width = c->dispatch_width;
239
240 /* Scratch space is used for register spilling */
241 if (c->last_scratch) {
242 uint32_t total_scratch;
243
244 /* Per-thread scratch space is power-of-two sized. */
245 for (c->prog_data.total_scratch = 1024;
246 c->prog_data.total_scratch <= c->last_scratch;
247 c->prog_data.total_scratch *= 2) {
248 /* empty */
249 }
250 total_scratch = c->prog_data.total_scratch * brw->wm_max_threads;
251
252 if (brw->wm.scratch_bo && total_scratch > brw->wm.scratch_bo->size) {
253 drm_intel_bo_unreference(brw->wm.scratch_bo);
254 brw->wm.scratch_bo = NULL;
255 }
256 if (brw->wm.scratch_bo == NULL) {
257 brw->wm.scratch_bo = drm_intel_bo_alloc(intel->bufmgr,
258 "wm scratch",
259 total_scratch,
260 4096);
261 }
262 }
263 else {
264 c->prog_data.total_scratch = 0;
265 }
266
267 if (unlikely(INTEL_DEBUG & DEBUG_WM))
268 fprintf(stderr, "\n");
269
270 /* get the program
271 */
272 program = brw_get_program(&c->func, &program_size);
273
274 drm_intel_bo_unreference(brw->wm.prog_bo);
275 brw->wm.prog_bo = brw_upload_cache_with_auxdata(&brw->cache, BRW_WM_PROG,
276 &c->key, sizeof(c->key),
277 NULL, 0,
278 program, program_size,
279 &c->prog_data,
280 sizeof(c->prog_data),
281 &brw->wm.prog_data);
282 }
283
284
285
286 static void brw_wm_populate_key( struct brw_context *brw,
287 struct brw_wm_prog_key *key )
288 {
289 struct gl_context *ctx = &brw->intel.ctx;
290 /* BRW_NEW_FRAGMENT_PROGRAM */
291 const struct brw_fragment_program *fp =
292 (struct brw_fragment_program *)brw->fragment_program;
293 GLuint lookup = 0;
294 GLuint line_aa;
295 GLuint i;
296
297 memset(key, 0, sizeof(*key));
298
299 /* Build the index for table lookup
300 */
301 /* _NEW_COLOR */
302 key->alpha_test = ctx->Color.AlphaEnabled;
303 if (fp->program.UsesKill ||
304 ctx->Color.AlphaEnabled)
305 lookup |= IZ_PS_KILL_ALPHATEST_BIT;
306
307 if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
308 lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
309
310 /* _NEW_DEPTH */
311 if (ctx->Depth.Test)
312 lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
313
314 if (ctx->Depth.Test &&
315 ctx->Depth.Mask) /* ?? */
316 lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
317
318 /* _NEW_STENCIL */
319 if (ctx->Stencil._Enabled) {
320 lookup |= IZ_STENCIL_TEST_ENABLE_BIT;
321
322 if (ctx->Stencil.WriteMask[0] ||
323 ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
324 lookup |= IZ_STENCIL_WRITE_ENABLE_BIT;
325 }
326
327 line_aa = AA_NEVER;
328
329 /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */
330 if (ctx->Line.SmoothFlag) {
331 if (brw->intel.reduced_primitive == GL_LINES) {
332 line_aa = AA_ALWAYS;
333 }
334 else if (brw->intel.reduced_primitive == GL_TRIANGLES) {
335 if (ctx->Polygon.FrontMode == GL_LINE) {
336 line_aa = AA_SOMETIMES;
337
338 if (ctx->Polygon.BackMode == GL_LINE ||
339 (ctx->Polygon.CullFlag &&
340 ctx->Polygon.CullFaceMode == GL_BACK))
341 line_aa = AA_ALWAYS;
342 }
343 else if (ctx->Polygon.BackMode == GL_LINE) {
344 line_aa = AA_SOMETIMES;
345
346 if ((ctx->Polygon.CullFlag &&
347 ctx->Polygon.CullFaceMode == GL_FRONT))
348 line_aa = AA_ALWAYS;
349 }
350 }
351 }
352
353 key->iz_lookup = lookup;
354 key->line_aa = line_aa;
355 key->stats_wm = brw->intel.stats_wm;
356
357 /* BRW_NEW_WM_INPUT_DIMENSIONS */
358 key->proj_attrib_mask = brw->wm.input_size_masks[4-1];
359
360 /* _NEW_LIGHT */
361 key->flat_shade = (ctx->Light.ShadeModel == GL_FLAT);
362
363 /* _NEW_HINT */
364 key->linear_color = (ctx->Hint.PerspectiveCorrection == GL_FASTEST);
365
366 /* _NEW_FRAG_CLAMP | _NEW_BUFFERS */
367 key->clamp_fragment_color = ctx->Color._ClampFragmentColor;
368
369 /* _NEW_TEXTURE */
370 for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
371 const struct gl_texture_unit *unit = &ctx->Texture.Unit[i];
372
373 if (unit->_ReallyEnabled) {
374 const struct gl_texture_object *t = unit->_Current;
375 const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
376 int swizzles[SWIZZLE_NIL + 1] = {
377 SWIZZLE_X,
378 SWIZZLE_Y,
379 SWIZZLE_Z,
380 SWIZZLE_W,
381 SWIZZLE_ZERO,
382 SWIZZLE_ONE,
383 SWIZZLE_NIL
384 };
385
386 /* GL_DEPTH_TEXTURE_MODE is normally handled through
387 * brw_wm_surface_state, but it applies to shadow compares as
388 * well and our shadow compares always return the result in
389 * all 4 channels.
390 */
391 if (t->Sampler.CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB) {
392 if (t->Sampler.DepthMode == GL_ALPHA) {
393 swizzles[0] = SWIZZLE_ZERO;
394 swizzles[1] = SWIZZLE_ZERO;
395 swizzles[2] = SWIZZLE_ZERO;
396 } else if (t->Sampler.DepthMode == GL_LUMINANCE) {
397 swizzles[3] = SWIZZLE_ONE;
398 } else if (t->Sampler.DepthMode == GL_RED) {
399 /* See table 3.23 of the GL 3.0 spec. */
400 swizzles[1] = SWIZZLE_ZERO;
401 swizzles[2] = SWIZZLE_ZERO;
402 swizzles[3] = SWIZZLE_ONE;
403 }
404 }
405
406 if (img->InternalFormat == GL_YCBCR_MESA) {
407 key->yuvtex_mask |= 1 << i;
408 if (img->TexFormat == MESA_FORMAT_YCBCR)
409 key->yuvtex_swap_mask |= 1 << i;
410 }
411
412 key->tex_swizzles[i] =
413 MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
414 swizzles[GET_SWZ(t->_Swizzle, 1)],
415 swizzles[GET_SWZ(t->_Swizzle, 2)],
416 swizzles[GET_SWZ(t->_Swizzle, 3)]);
417 }
418 else {
419 key->tex_swizzles[i] = SWIZZLE_NOOP;
420 }
421 }
422
423 /* Shadow */
424 key->shadowtex_mask = fp->program.Base.ShadowSamplers;
425
426 /* _NEW_BUFFERS */
427 /*
428 * Include the draw buffer origin and height so that we can calculate
429 * fragment position values relative to the bottom left of the drawable,
430 * from the incoming screen origin relative position we get as part of our
431 * payload.
432 *
433 * This is only needed for the WM_WPOSXY opcode when the fragment program
434 * uses the gl_FragCoord input.
435 *
436 * We could avoid recompiling by including this as a constant referenced by
437 * our program, but if we were to do that it would also be nice to handle
438 * getting that constant updated at batchbuffer submit time (when we
439 * hold the lock and know where the buffer really is) rather than at emit
440 * time when we don't hold the lock and are just guessing. We could also
441 * just avoid using this as key data if the program doesn't use
442 * fragment.position.
443 *
444 * For DRI2 the origin_x/y will always be (0,0) but we still need the
445 * drawable height in order to invert the Y axis.
446 */
447 if (fp->program.Base.InputsRead & FRAG_BIT_WPOS) {
448 key->drawable_height = ctx->DrawBuffer->Height;
449 key->render_to_fbo = ctx->DrawBuffer->Name != 0;
450 }
451
452 /* _NEW_BUFFERS */
453 key->nr_color_regions = ctx->DrawBuffer->_NumColorDrawBuffers;
454
455 /* CACHE_NEW_VS_PROG */
456 key->vp_outputs_written = brw->vs.prog_data->outputs_written;
457
458 /* The unique fragment program ID */
459 key->program_string_id = fp->id;
460 }
461
462
463 static void brw_prepare_wm_prog(struct brw_context *brw)
464 {
465 struct brw_wm_prog_key key;
466 struct brw_fragment_program *fp = (struct brw_fragment_program *)
467 brw->fragment_program;
468
469 brw_wm_populate_key(brw, &key);
470
471 /* Make an early check for the key.
472 */
473 drm_intel_bo_unreference(brw->wm.prog_bo);
474 brw->wm.prog_bo = brw_search_cache(&brw->cache, BRW_WM_PROG,
475 &key, sizeof(key),
476 NULL, 0,
477 &brw->wm.prog_data);
478 if (brw->wm.prog_bo == NULL)
479 do_wm_prog(brw, fp, &key);
480 }
481
482
483 const struct brw_tracked_state brw_wm_prog = {
484 .dirty = {
485 .mesa = (_NEW_COLOR |
486 _NEW_DEPTH |
487 _NEW_HINT |
488 _NEW_STENCIL |
489 _NEW_POLYGON |
490 _NEW_LINE |
491 _NEW_LIGHT |
492 _NEW_FRAG_CLAMP |
493 _NEW_BUFFERS |
494 _NEW_TEXTURE),
495 .brw = (BRW_NEW_FRAGMENT_PROGRAM |
496 BRW_NEW_WM_INPUT_DIMENSIONS |
497 BRW_NEW_REDUCED_PRIMITIVE),
498 .cache = CACHE_NEW_VS_PROG,
499 },
500 .prepare = brw_prepare_wm_prog
501 };
502