src/mesa/drivers/dri/i965/brw_wm.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_WM_H
  34 #define BRW_WM_H
  35
  36
  37 #include "shader/prog_instruction.h"
  38 #include "brw_context.h"
  39 #include "brw_eu.h"
  40
  41 /* A big lookup table is used to figure out which and how many
  42  * additional regs will inserted before the main payload in the WM
  43  * program execution.  These mainly relate to depth and stencil
  44  * processing and the early-depth-test optimization.
  45  */
  46 #define IZ_PS_KILL_ALPHATEST_BIT    0x1
  47 #define IZ_PS_COMPUTES_DEPTH_BIT    0x2
  48 #define IZ_DEPTH_WRITE_ENABLE_BIT   0x4
  49 #define IZ_DEPTH_TEST_ENABLE_BIT    0x8
  50 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
  51 #define IZ_STENCIL_TEST_ENABLE_BIT  0x20
  52 #define IZ_BIT_MAX                  0x40
  53
  54 #define AA_NEVER     0
  55 #define AA_SOMETIMES 1
  56 #define AA_ALWAYS    2
  57
  58 struct brw_wm_prog_key {
  59    GLuint source_depth_reg:3;
  60    GLuint aa_dest_stencil_reg:3;
  61    GLuint dest_depth_reg:3;
  62    GLuint nr_depth_regs:3;
  63    GLuint computes_depth:1;     /* could be derived from program string */
  64    GLuint source_depth_to_render_target:1;
  65    GLuint flat_shade:1;
  66    GLuint runtime_check_aads_emit:1;
  67
  68    GLbitfield proj_attrib_mask; /**< one bit per fragment program attribute */
  69    GLuint shadowtex_mask:16;
  70    GLuint yuvtex_mask:16;
  71    GLuint yuvtex_swap_mask:16;  /* UV swaped */
  72
  73    GLuint tex_swizzles[BRW_MAX_TEX_UNIT];
  74
  75    GLuint program_string_id:32;
  76    GLuint origin_x, origin_y;
  77    GLuint drawable_height;
  78 };
  79
  80
  81 /* A bit of a glossary:
  82  *
  83  * brw_wm_value: A computed value or program input.  Values are
  84  * constant, they are created once and are never modified.  When a
  85  * fragment program register is written or overwritten, new values are
  86  * created fresh, preserving the rule that values are constant.
  87  *
  88  * brw_wm_ref: A reference to a value.  Wherever a value used is by an
  89  * instruction or as a program output, that is tracked with an
  90  * instance of this struct.  All references to a value occur after it
  91  * is created.  After the last reference, a value is dead and can be
  92  * discarded.
  93  *
  94  * brw_wm_grf: Represents a physical hardware register.  May be either
  95  * empty or hold a value.  Register allocation is the process of
  96  * assigning values to grf registers.  This occurs in pass2 and the
  97  * brw_wm_grf struct is not used before that.
  98  *
  99  * Fragment program registers: These are time-varying constructs that
 100  * are hard to reason about and which we translate away in pass0.  A
 101  * single fragment program register element (eg. temp[0].x) will be
 102  * translated to one or more brw_wm_value structs, one for each time
 103  * that temp[0].x is written to during the program.
 104  */
 105
 106
 107
 108 /* Used in pass2 to track register allocation.
 109  */
 110 struct brw_wm_grf {
 111    struct brw_wm_value *value;
 112    GLuint nextuse;
 113 };
 114
 115 struct brw_wm_value {
 116    struct brw_reg hw_reg;       /* emitted to this reg, may not always be there */
 117    struct brw_wm_ref *lastuse;
 118    struct brw_wm_grf *resident;
 119    GLuint contributes_to_output:1;
 120    GLuint spill_slot:16;        /* if non-zero, spill immediately after calculation */
 121 };
 122
 123 struct brw_wm_ref {
 124    struct brw_reg hw_reg;       /* nr filled in in pass2, everything else, pass0 */
 125    struct brw_wm_value *value;
 126    struct brw_wm_ref *prevuse;
 127    GLuint unspill_reg:7;        /* unspill to reg */
 128    GLuint emitted:1;
 129    GLuint insn:24;
 130 };
 131
 132 struct brw_wm_constref {
 133    const struct brw_wm_ref *ref;
 134    GLfloat constval;
 135 };
 136
 137
 138 struct brw_wm_instruction {
 139    struct brw_wm_value *dst[4];
 140    struct brw_wm_ref *src[3][4];
 141    GLuint opcode:8;
 142    GLuint saturate:1;
 143    GLuint writemask:4;
 144    GLuint tex_unit:4;   /* texture unit for TEX, TXD, TXP instructions */
 145    GLuint tex_idx:3;    /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
 146    GLuint tex_shadow:1; /* do shadow comparison? */
 147    GLuint eot:1;        /* End of thread indicator for FB_WRITE*/
 148    GLuint target:10;    /* target binding table index for FB_WRITE*/
 149 };
 150
 151
 152 #define BRW_WM_MAX_INSN  (MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3)
 153 #define BRW_WM_MAX_GRF   128            /* hardware limit */
 154 #define BRW_WM_MAX_VREG  (BRW_WM_MAX_INSN * 4)
 155 #define BRW_WM_MAX_REF   (BRW_WM_MAX_INSN * 12)
 156 #define BRW_WM_MAX_PARAM 256
 157 #define BRW_WM_MAX_CONST 256
 158 #define BRW_WM_MAX_KILLS MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS
 159 #define BRW_WM_MAX_SUBROUTINE 16
 160
 161
 162
 163 /* New opcodes to track internal operations required for WM unit.
 164  * These are added early so that the registers used can be tracked,
 165  * freed and reused like those of other instructions.
 166  */
 167 #define WM_PIXELXY        (MAX_OPCODE)
 168 #define WM_DELTAXY        (MAX_OPCODE + 1)
 169 #define WM_PIXELW         (MAX_OPCODE + 2)
 170 #define WM_LINTERP        (MAX_OPCODE + 3)
 171 #define WM_PINTERP        (MAX_OPCODE + 4)
 172 #define WM_CINTERP        (MAX_OPCODE + 5)
 173 #define WM_WPOSXY         (MAX_OPCODE + 6)
 174 #define WM_FB_WRITE       (MAX_OPCODE + 7)
 175 #define WM_FRONTFACING    (MAX_OPCODE + 8)
 176 #define MAX_WM_OPCODE     (MAX_OPCODE + 9)
 177
 178 #define PROGRAM_PAYLOAD   (PROGRAM_FILE_MAX)
 179 #define PAYLOAD_DEPTH     (FRAG_ATTRIB_MAX)
 180
 181 struct brw_wm_compile {
 182    struct brw_compile func;
 183    struct brw_wm_prog_key key;
 184    struct brw_wm_prog_data prog_data;
 185
 186    struct brw_fragment_program *fp;
 187
 188    GLfloat (*env_param)[4];
 189
 190    enum {
 191       START,
 192       PASS2_DONE
 193    } state;
 194
 195    /* Initial pass - translate fp instructions to fp instructions,
 196     * simplifying and adding instructions for interpolation and
 197     * framebuffer writes.
 198     */
 199    struct prog_instruction prog_instructions[BRW_WM_MAX_INSN];
 200    GLuint nr_fp_insns;
 201    GLuint fp_temp;
 202    GLuint fp_interp_emitted;
 203    GLuint fp_fragcolor_emitted;
 204    GLuint fp_deriv_emitted;
 205
 206    struct prog_src_register pixel_xy;
 207    struct prog_src_register delta_xy;
 208    struct prog_src_register pixel_w;
 209
 210
 211    struct brw_wm_value vreg[BRW_WM_MAX_VREG];
 212    GLuint nr_vreg;
 213
 214    struct brw_wm_value creg[BRW_WM_MAX_PARAM];
 215    GLuint nr_creg;
 216
 217    struct {
 218       struct brw_wm_value depth[4]; /* includes r0/r1 */
 219       struct brw_wm_value input_interp[FRAG_ATTRIB_MAX];
 220    } payload;
 221
 222
 223    const struct brw_wm_ref *pass0_fp_reg[PROGRAM_PAYLOAD+1][256][4];
 224
 225    struct brw_wm_ref undef_ref;
 226    struct brw_wm_value undef_value;
 227
 228    struct brw_wm_ref refs[BRW_WM_MAX_REF];
 229    GLuint nr_refs;
 230
 231    struct brw_wm_instruction instruction[BRW_WM_MAX_INSN];
 232    GLuint nr_insns;
 233
 234    struct brw_wm_constref constref[BRW_WM_MAX_CONST];
 235    GLuint nr_constrefs;
 236
 237    struct brw_wm_grf pass2_grf[BRW_WM_MAX_GRF/2];
 238
 239    GLuint grf_limit;
 240    GLuint max_wm_grf;
 241    GLuint last_scratch;
 242
 243    /** Mapping from Mesa registers to hardware registers */
 244    struct {
 245       GLboolean inited;
 246       struct brw_reg reg;
 247    } wm_regs[PROGRAM_PAYLOAD+1][256][4];
 248
 249    struct brw_reg stack;
 250    struct brw_reg emit_mask_reg;
 251    GLuint reg_index;  /**< Index of next free GRF register */
 252    GLuint tmp_regs[BRW_WM_MAX_GRF];
 253    GLuint tmp_index;
 254    GLuint tmp_max;
 255    GLuint subroutines[BRW_WM_MAX_SUBROUTINE];
 256
 257    /** we may need up to 3 constants per instruction (if use_const_buffer) */
 258    struct {
 259       GLint index;
 260       struct brw_reg reg;
 261    } current_const[3];
 262 };
 263
 264
 265 GLuint brw_wm_nr_args( GLuint opcode );
 266 GLuint brw_wm_is_scalar_result( GLuint opcode );
 267
 268 void brw_wm_pass_fp( struct brw_wm_compile *c );
 269 void brw_wm_pass0( struct brw_wm_compile *c );
 270 void brw_wm_pass1( struct brw_wm_compile *c );
 271 void brw_wm_pass2( struct brw_wm_compile *c );
 272 void brw_wm_emit( struct brw_wm_compile *c );
 273
 274 void brw_wm_print_value( struct brw_wm_compile *c,
 275                          struct brw_wm_value *value );
 276
 277 void brw_wm_print_ref( struct brw_wm_compile *c,
 278                        struct brw_wm_ref *ref );
 279
 280 void brw_wm_print_insn( struct brw_wm_compile *c,
 281                         struct brw_wm_instruction *inst );
 282
 283 void brw_wm_print_program( struct brw_wm_compile *c,
 284                            const char *stage );
 285
 286 void brw_wm_lookup_iz( GLuint line_aa,
 287                        GLuint lookup,
 288                        struct brw_wm_prog_key *key );
 289
 290 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp);
 291 void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c);
 292
 293
 294 #endif