2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
37 #include "brw_context.h"
39 #include "prog_instruction.h"
41 /* A big lookup table is used to figure out which and how many
42 * additional regs will inserted before the main payload in the WM
43 * program execution. These mainly relate to depth and stencil
44 * processing and the early-depth-test optimization.
46 #define IZ_PS_KILL_ALPHATEST_BIT 0x1
47 #define IZ_PS_COMPUTES_DEPTH_BIT 0x2
48 #define IZ_DEPTH_WRITE_ENABLE_BIT 0x4
49 #define IZ_DEPTH_TEST_ENABLE_BIT 0x8
50 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
51 #define IZ_STENCIL_TEST_ENABLE_BIT 0x20
52 #define IZ_EARLY_DEPTH_TEST_BIT 0x40
53 #define IZ_BIT_MAX 0x80
56 #define AA_SOMETIMES 1
59 struct brw_wm_prog_key
{
60 GLuint source_depth_reg
:3;
61 GLuint aa_dest_stencil_reg
:3;
62 GLuint dest_depth_reg
:3;
63 GLuint nr_depth_regs
:3;
64 GLuint projtex_mask
:8;
65 GLuint shadowtex_mask
:8;
66 GLuint computes_depth
:1; /* could be derived from program string */
67 GLuint source_depth_to_render_target
:1;
69 GLuint runtime_check_aads_emit
:1;
74 GLuint program_string_id
:32;
78 /* A bit of a glossary:
80 * brw_wm_value: A computed value or program input. Values are
81 * constant, they are created once and are never modified. When a
82 * fragment program register is written or overwritten, new values are
83 * created fresh, preserving the rule that values are constant.
85 * brw_wm_ref: A reference to a value. Wherever a value used is by an
86 * instruction or as a program output, that is tracked with an
87 * instance of this struct. All references to a value occur after it
88 * is created. After the last reference, a value is dead and can be
91 * brw_wm_grf: Represents a physical hardware register. May be either
92 * empty or hold a value. Register allocation is the process of
93 * assigning values to grf registers. This occurs in pass2 and the
94 * brw_wm_grf struct is not used before that.
96 * Fragment program registers: These are time-varying constructs that
97 * are hard to reason about and which we translate away in pass0. A
98 * single fragment program register element (eg. temp[0].x) will be
99 * translated to one or more brw_wm_value structs, one for each time
100 * that temp[0].x is written to during the program.
105 /* Used in pass2 to track register allocation.
108 struct brw_wm_value
*value
;
112 struct brw_wm_value
{
113 struct brw_reg hw_reg
; /* emitted to this reg, may not always be there */
114 struct brw_wm_ref
*lastuse
;
115 struct brw_wm_grf
*resident
;
116 GLuint contributes_to_output
:1;
117 GLuint spill_slot
:16; /* if non-zero, spill immediately after calculation */
121 struct brw_reg hw_reg
; /* nr filled in in pass2, everything else, pass0 */
122 struct brw_wm_value
*value
;
123 struct brw_wm_ref
*prevuse
;
124 GLuint unspill_reg
:7; /* unspill to reg */
129 struct brw_wm_constref
{
130 const struct brw_wm_ref
*ref
;
135 struct brw_wm_instruction
{
136 struct brw_wm_value
*dst
[4];
137 struct brw_wm_ref
*src
[3][4];
141 GLuint tex_unit
:4; /* texture unit for TEX, TXD, TXP instructions */
142 GLuint tex_idx
:3; /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
146 #define PROGRAM_INTERNAL_PARAM
148 #define BRW_WM_MAX_INSN (MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3)
149 #define BRW_WM_MAX_GRF 128 /* hardware limit */
150 #define BRW_WM_MAX_VREG (BRW_WM_MAX_INSN * 4)
151 #define BRW_WM_MAX_REF (BRW_WM_MAX_INSN * 12)
152 #define BRW_WM_MAX_PARAM 256
153 #define BRW_WM_MAX_CONST 256
154 #define BRW_WM_MAX_KILLS MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS
158 /* New opcodes to track internal operations required for WM unit.
159 * These are added early so that the registers used can be tracked,
160 * freed and reused like those of other instructions.
162 #define WM_PIXELXY (MAX_OPCODE)
163 #define WM_DELTAXY (MAX_OPCODE + 1)
164 #define WM_PIXELW (MAX_OPCODE + 2)
165 #define WM_LINTERP (MAX_OPCODE + 3)
166 #define WM_PINTERP (MAX_OPCODE + 4)
167 #define WM_CINTERP (MAX_OPCODE + 5)
168 #define WM_WPOSXY (MAX_OPCODE + 6)
169 #define WM_FB_WRITE (MAX_OPCODE + 7)
170 #define MAX_WM_OPCODE (MAX_OPCODE + 8)
172 #define PROGRAM_PAYLOAD (PROGRAM_FILE_MAX)
173 #define PAYLOAD_DEPTH (FRAG_ATTRIB_MAX)
175 struct brw_wm_compile
{
176 struct brw_compile func
;
177 struct brw_wm_prog_key key
;
178 struct brw_wm_prog_data prog_data
;
180 struct brw_fragment_program
*fp
;
182 GLfloat (*env_param
)[4];
189 /* Initial pass - translate fp instructions to fp instructions,
190 * simplifying and adding instructions for interpolation and
191 * framebuffer writes.
193 struct prog_instruction prog_instructions
[BRW_WM_MAX_INSN
];
196 GLuint fp_interp_emitted
;
198 struct prog_src_register pixel_xy
;
199 struct prog_src_register delta_xy
;
200 struct prog_src_register pixel_w
;
203 struct brw_wm_value vreg
[BRW_WM_MAX_VREG
];
206 struct brw_wm_value creg
[BRW_WM_MAX_PARAM
];
210 struct brw_wm_value depth
[4]; /* includes r0/r1 */
211 struct brw_wm_value input_interp
[FRAG_ATTRIB_MAX
];
215 const struct brw_wm_ref
*pass0_fp_reg
[PROGRAM_PAYLOAD
+1][256][4];
217 struct brw_wm_ref undef_ref
;
218 struct brw_wm_value undef_value
;
220 struct brw_wm_ref refs
[BRW_WM_MAX_REF
];
223 struct brw_wm_instruction instruction
[BRW_WM_MAX_INSN
];
226 struct brw_wm_constref constref
[BRW_WM_MAX_CONST
];
229 struct brw_wm_grf pass2_grf
[BRW_WM_MAX_GRF
/2];
238 } wm_regs
[PROGRAM_PAYLOAD
+1][256][4];
239 struct brw_reg ret_reg
;
245 GLuint
brw_wm_nr_args( GLuint opcode
);
246 GLuint
brw_wm_is_scalar_result( GLuint opcode
);
248 void brw_wm_pass_fp( struct brw_wm_compile
*c
);
249 void brw_wm_pass0( struct brw_wm_compile
*c
);
250 void brw_wm_pass1( struct brw_wm_compile
*c
);
251 void brw_wm_pass2( struct brw_wm_compile
*c
);
252 void brw_wm_emit( struct brw_wm_compile
*c
);
254 void brw_wm_print_value( struct brw_wm_compile
*c
,
255 struct brw_wm_value
*value
);
257 void brw_wm_print_ref( struct brw_wm_compile
*c
,
258 struct brw_wm_ref
*ref
);
260 void brw_wm_print_insn( struct brw_wm_compile
*c
,
261 struct brw_wm_instruction
*inst
);
263 void brw_wm_print_program( struct brw_wm_compile
*c
,
266 void brw_wm_lookup_iz( GLuint line_aa
,
268 struct brw_wm_prog_key
*key
);
270 GLboolean
brw_wm_is_glsl(struct gl_fragment_program
*fp
);
271 void brw_wm_glsl_emit(struct brw_wm_compile
*c
);