src/mesa/drivers/dri/i965/brw_wm.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_WM_H
  34 #define BRW_WM_H
  35
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39 #include "program_instruction.h"
  40
  41 /* A big lookup table is used to figure out which and how many
  42  * additional regs will inserted before the main payload in the WM
  43  * program execution.  These mainly relate to depth and stencil
  44  * processing and the early-depth-test optimization.
  45  */
  46 #define IZ_PS_KILL_ALPHATEST_BIT    0x1
  47 #define IZ_PS_COMPUTES_DEPTH_BIT    0x2
  48 #define IZ_DEPTH_WRITE_ENABLE_BIT   0x4
  49 #define IZ_DEPTH_TEST_ENABLE_BIT    0x8
  50 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
  51 #define IZ_STENCIL_TEST_ENABLE_BIT  0x20
  52 #define IZ_EARLY_DEPTH_TEST_BIT     0x40
  53 #define IZ_BIT_MAX                  0x80
  54
  55 #define AA_NEVER     0
  56 #define AA_SOMETIMES 1
  57 #define AA_ALWAYS    2
  58
  59 struct brw_wm_prog_key {
  60    GLuint source_depth_reg:3;
  61    GLuint aa_dest_stencil_reg:3;
  62    GLuint dest_depth_reg:3;
  63    GLuint nr_depth_regs:3;
  64    GLuint projtex_mask:8;
  65    GLuint shadowtex_mask:8;
  66    GLuint computes_depth:1;     /* could be derived from program string */
  67    GLuint source_depth_to_render_target:1;
  68    GLuint flat_shade:1;
  69    GLuint runtime_check_aads_emit:1;
  70
  71    GLuint yuvtex_mask:8;
  72    GLuint pad1:24;
  73
  74    GLuint program_string_id:32;
  75 };
  76
  77
  78 /* A bit of a glossary:
  79  *
  80  * brw_wm_value: A computed value or program input.  Values are
  81  * constant, they are created once and are never modified.  When a
  82  * fragment program register is written or overwritten, new values are
  83  * created fresh, preserving the rule that values are constant.
  84  *
  85  * brw_wm_ref: A reference to a value.  Wherever a value used is by an
  86  * instruction or as a program output, that is tracked with an
  87  * instance of this struct.  All references to a value occur after it
  88  * is created.  After the last reference, a value is dead and can be
  89  * discarded.
  90  *
  91  * brw_wm_grf: Represents a physical hardware register.  May be either
  92  * empty or hold a value.  Register allocation is the process of
  93  * assigning values to grf registers.  This occurs in pass2 and the
  94  * brw_wm_grf struct is not used before that.
  95  *
  96  * Fragment program registers: These are time-varying constructs that
  97  * are hard to reason about and which we translate away in pass0.  A
  98  * single fragment program register element (eg. temp[0].x) will be
  99  * translated to one or more brw_wm_value structs, one for each time
 100  * that temp[0].x is written to during the program.
 101  */
 102
 103
 104
 105 /* Used in pass2 to track register allocation.
 106  */
 107 struct brw_wm_grf {
 108    struct brw_wm_value *value;
 109    GLuint nextuse;
 110 };
 111
 112 struct brw_wm_value {
 113    struct brw_reg hw_reg;       /* emitted to this reg, may not always be there */
 114    struct brw_wm_ref *lastuse;
 115    struct brw_wm_grf *resident;
 116    GLuint contributes_to_output:1;
 117    GLuint spill_slot:16;        /* if non-zero, spill immediately after calculation */
 118 };
 119
 120 struct brw_wm_ref {
 121    struct brw_reg hw_reg;       /* nr filled in in pass2, everything else, pass0 */
 122    struct brw_wm_value *value;
 123    struct brw_wm_ref *prevuse;
 124    GLuint unspill_reg:7;        /* unspill to reg */
 125    GLuint emitted:1;
 126    GLuint insn:24;
 127 };
 128
 129 struct brw_wm_constref {
 130    const struct brw_wm_ref *ref;
 131    GLfloat constval;
 132 };
 133
 134
 135 struct brw_wm_instruction {
 136    struct brw_wm_value *dst[4];
 137    struct brw_wm_ref *src[3][4];
 138    GLuint opcode:8;
 139    GLuint saturate:1;
 140    GLuint writemask:4;
 141    GLuint tex_unit:4;   /* texture unit for TEX, TXD, TXP instructions */
 142    GLuint tex_idx:3;    /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
 143 };
 144
 145
 146 #define PROGRAM_INTERNAL_PARAM
 147
 148 #define BRW_WM_MAX_INSN  (MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3)
 149 #define BRW_WM_MAX_GRF   128            /* hardware limit */
 150 #define BRW_WM_MAX_VREG  (BRW_WM_MAX_INSN * 4)
 151 #define BRW_WM_MAX_REF   (BRW_WM_MAX_INSN * 12)
 152 #define BRW_WM_MAX_PARAM 256
 153 #define BRW_WM_MAX_CONST 256
 154 #define BRW_WM_MAX_KILLS MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS
 155
 156
 157
 158 /* New opcodes to track internal operations required for WM unit.
 159  * These are added early so that the registers used can be tracked,
 160  * freed and reused like those of other instructions.
 161  */
 162 #define WM_PIXELXY        (MAX_OPCODE)
 163 #define WM_DELTAXY        (MAX_OPCODE + 1)
 164 #define WM_PIXELW         (MAX_OPCODE + 2)
 165 #define WM_LINTERP        (MAX_OPCODE + 3)
 166 #define WM_PINTERP        (MAX_OPCODE + 4)
 167 #define WM_CINTERP        (MAX_OPCODE + 5)
 168 #define WM_WPOSXY         (MAX_OPCODE + 6)
 169 #define WM_FB_WRITE       (MAX_OPCODE + 7)
 170
 171 #define PROGRAM_PAYLOAD   (PROGRAM_FILE_MAX)
 172 #define PAYLOAD_DEPTH     (FRAG_ATTRIB_MAX)
 173
 174 struct brw_wm_compile {
 175    struct brw_compile func;
 176    struct brw_wm_prog_key key;
 177    struct brw_wm_prog_data prog_data;
 178
 179    struct brw_fragment_program *fp;
 180
 181    GLfloat (*env_param)[4];
 182
 183    enum {
 184       START,
 185       PASS2_DONE
 186    } state;
 187
 188    /* Initial pass - translate fp instructions to fp instructions,
 189     * simplifying and adding instructions for interpolation and
 190     * framebuffer writes.
 191     */
 192    struct prog_instruction prog_instructions[BRW_WM_MAX_INSN];
 193    GLuint nr_fp_insns;
 194    GLuint fp_temp;
 195    GLuint fp_interp_emitted;
 196
 197    struct prog_src_register pixel_xy;
 198    struct prog_src_register delta_xy;
 199    struct prog_src_register pixel_w;
 200
 201
 202    struct brw_wm_value vreg[BRW_WM_MAX_VREG];
 203    GLuint nr_vreg;
 204
 205    struct brw_wm_value creg[BRW_WM_MAX_PARAM];
 206    GLuint nr_creg;
 207
 208    struct {
 209       struct brw_wm_value depth[4]; /* includes r0/r1 */
 210       struct brw_wm_value input_interp[FRAG_ATTRIB_MAX];
 211    } payload;
 212
 213
 214    const struct brw_wm_ref *pass0_fp_reg[PROGRAM_PAYLOAD+1][256][4];
 215
 216    struct brw_wm_ref undef_ref;
 217    struct brw_wm_value undef_value;
 218
 219    struct brw_wm_ref refs[BRW_WM_MAX_REF];
 220    GLuint nr_refs;
 221
 222    struct brw_wm_instruction instruction[BRW_WM_MAX_INSN];
 223    GLuint nr_insns;
 224
 225    struct brw_wm_constref constref[BRW_WM_MAX_CONST];
 226    GLuint nr_constrefs;
 227
 228    struct brw_wm_grf pass2_grf[BRW_WM_MAX_GRF/2];
 229
 230    GLuint grf_limit;
 231    GLuint max_wm_grf;
 232    GLuint last_scratch;
 233 };
 234
 235
 236 GLuint brw_wm_nr_args( GLuint opcode );
 237 GLuint brw_wm_is_scalar_result( GLuint opcode );
 238
 239 void brw_wm_pass_fp( struct brw_wm_compile *c );
 240 void brw_wm_pass0( struct brw_wm_compile *c );
 241 void brw_wm_pass1( struct brw_wm_compile *c );
 242 void brw_wm_pass2( struct brw_wm_compile *c );
 243 void brw_wm_emit( struct brw_wm_compile *c );
 244
 245 void brw_wm_print_value( struct brw_wm_compile *c,
 246                          struct brw_wm_value *value );
 247
 248 void brw_wm_print_ref( struct brw_wm_compile *c,
 249                        struct brw_wm_ref *ref );
 250
 251 void brw_wm_print_insn( struct brw_wm_compile *c,
 252                         struct brw_wm_instruction *inst );
 253
 254 void brw_wm_print_program( struct brw_wm_compile *c,
 255                            const char *stage );
 256
 257 void brw_wm_lookup_iz( GLuint line_aa,
 258                        GLuint lookup,
 259                        struct brw_wm_prog_key *key );
 260
 261 #endif