2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
37 #include "shader/prog_instruction.h"
38 #include "brw_context.h"
41 #define SATURATE (1<<5)
43 /* A big lookup table is used to figure out which and how many
44 * additional regs will inserted before the main payload in the WM
45 * program execution. These mainly relate to depth and stencil
46 * processing and the early-depth-test optimization.
48 #define IZ_PS_KILL_ALPHATEST_BIT 0x1
49 #define IZ_PS_COMPUTES_DEPTH_BIT 0x2
50 #define IZ_DEPTH_WRITE_ENABLE_BIT 0x4
51 #define IZ_DEPTH_TEST_ENABLE_BIT 0x8
52 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
53 #define IZ_STENCIL_TEST_ENABLE_BIT 0x20
54 #define IZ_BIT_MAX 0x40
57 #define AA_SOMETIMES 1
60 struct brw_wm_prog_key
{
61 GLuint source_depth_reg
:3;
62 GLuint aa_dest_stencil_reg
:3;
63 GLuint dest_depth_reg
:3;
64 GLuint nr_depth_regs
:3;
65 GLuint computes_depth
:1; /* could be derived from program string */
66 GLuint source_depth_to_render_target
:1;
68 GLuint linear_color
:1; /**< linear interpolation vs perspective interp */
69 GLuint runtime_check_aads_emit
:1;
71 GLbitfield proj_attrib_mask
; /**< one bit per fragment program attribute */
72 GLuint shadowtex_mask
:16;
73 GLuint yuvtex_mask
:16;
74 GLuint yuvtex_swap_mask
:16; /* UV swaped */
76 GLuint tex_swizzles
[BRW_MAX_TEX_UNIT
];
78 GLuint program_string_id
:32;
79 GLuint origin_x
, origin_y
;
80 GLuint drawable_height
;
81 GLuint vp_outputs_written
;
85 /* A bit of a glossary:
87 * brw_wm_value: A computed value or program input. Values are
88 * constant, they are created once and are never modified. When a
89 * fragment program register is written or overwritten, new values are
90 * created fresh, preserving the rule that values are constant.
92 * brw_wm_ref: A reference to a value. Wherever a value used is by an
93 * instruction or as a program output, that is tracked with an
94 * instance of this struct. All references to a value occur after it
95 * is created. After the last reference, a value is dead and can be
98 * brw_wm_grf: Represents a physical hardware register. May be either
99 * empty or hold a value. Register allocation is the process of
100 * assigning values to grf registers. This occurs in pass2 and the
101 * brw_wm_grf struct is not used before that.
103 * Fragment program registers: These are time-varying constructs that
104 * are hard to reason about and which we translate away in pass0. A
105 * single fragment program register element (eg. temp[0].x) will be
106 * translated to one or more brw_wm_value structs, one for each time
107 * that temp[0].x is written to during the program.
112 /* Used in pass2 to track register allocation.
115 struct brw_wm_value
*value
;
119 struct brw_wm_value
{
120 struct brw_reg hw_reg
; /* emitted to this reg, may not always be there */
121 struct brw_wm_ref
*lastuse
;
122 struct brw_wm_grf
*resident
;
123 GLuint contributes_to_output
:1;
124 GLuint spill_slot
:16; /* if non-zero, spill immediately after calculation */
128 struct brw_reg hw_reg
; /* nr filled in in pass2, everything else, pass0 */
129 struct brw_wm_value
*value
;
130 struct brw_wm_ref
*prevuse
;
131 GLuint unspill_reg
:7; /* unspill to reg */
136 struct brw_wm_constref
{
137 const struct brw_wm_ref
*ref
;
142 struct brw_wm_instruction
{
143 struct brw_wm_value
*dst
[4];
144 struct brw_wm_ref
*src
[3][4];
148 GLuint tex_unit
:4; /* texture unit for TEX, TXD, TXP instructions */
149 GLuint tex_idx
:3; /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
150 GLuint tex_shadow
:1; /* do shadow comparison? */
151 GLuint eot
:1; /* End of thread indicator for FB_WRITE*/
152 GLuint target
:10; /* target binding table index for FB_WRITE*/
156 #define BRW_WM_MAX_INSN (MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3)
157 #define BRW_WM_MAX_GRF 128 /* hardware limit */
158 #define BRW_WM_MAX_VREG (BRW_WM_MAX_INSN * 4)
159 #define BRW_WM_MAX_REF (BRW_WM_MAX_INSN * 12)
160 #define BRW_WM_MAX_PARAM 256
161 #define BRW_WM_MAX_CONST 256
162 #define BRW_WM_MAX_KILLS MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS
163 #define BRW_WM_MAX_SUBROUTINE 16
167 /* New opcodes to track internal operations required for WM unit.
168 * These are added early so that the registers used can be tracked,
169 * freed and reused like those of other instructions.
171 #define WM_PIXELXY (MAX_OPCODE)
172 #define WM_DELTAXY (MAX_OPCODE + 1)
173 #define WM_PIXELW (MAX_OPCODE + 2)
174 #define WM_LINTERP (MAX_OPCODE + 3)
175 #define WM_PINTERP (MAX_OPCODE + 4)
176 #define WM_CINTERP (MAX_OPCODE + 5)
177 #define WM_WPOSXY (MAX_OPCODE + 6)
178 #define WM_FB_WRITE (MAX_OPCODE + 7)
179 #define WM_FRONTFACING (MAX_OPCODE + 8)
180 #define MAX_WM_OPCODE (MAX_OPCODE + 9)
182 #define PROGRAM_PAYLOAD (PROGRAM_FILE_MAX)
183 #define PAYLOAD_DEPTH (FRAG_ATTRIB_MAX)
185 struct brw_wm_compile
{
186 struct brw_compile func
;
187 struct brw_wm_prog_key key
;
188 struct brw_wm_prog_data prog_data
;
190 struct brw_fragment_program
*fp
;
192 GLfloat (*env_param
)[4];
199 /* Initial pass - translate fp instructions to fp instructions,
200 * simplifying and adding instructions for interpolation and
201 * framebuffer writes.
203 struct prog_instruction prog_instructions
[BRW_WM_MAX_INSN
];
206 GLuint fp_interp_emitted
;
207 GLuint fp_fragcolor_emitted
;
209 struct prog_src_register pixel_xy
;
210 struct prog_src_register delta_xy
;
211 struct prog_src_register pixel_w
;
214 struct brw_wm_value vreg
[BRW_WM_MAX_VREG
];
217 struct brw_wm_value creg
[BRW_WM_MAX_PARAM
];
221 struct brw_wm_value depth
[4]; /* includes r0/r1 */
222 struct brw_wm_value input_interp
[FRAG_ATTRIB_MAX
];
226 const struct brw_wm_ref
*pass0_fp_reg
[PROGRAM_PAYLOAD
+1][256][4];
228 struct brw_wm_ref undef_ref
;
229 struct brw_wm_value undef_value
;
231 struct brw_wm_ref refs
[BRW_WM_MAX_REF
];
234 struct brw_wm_instruction instruction
[BRW_WM_MAX_INSN
];
237 struct brw_wm_constref constref
[BRW_WM_MAX_CONST
];
240 struct brw_wm_grf pass2_grf
[BRW_WM_MAX_GRF
/2];
246 GLuint cur_inst
; /**< index of current instruction */
248 GLboolean out_of_regs
; /**< ran out of GRF registers? */
250 /** Mapping from Mesa registers to hardware registers */
254 } wm_regs
[PROGRAM_PAYLOAD
+1][256][4];
256 GLboolean used_grf
[BRW_WM_MAX_GRF
];
257 GLuint first_free_grf
;
258 struct brw_reg stack
;
259 struct brw_reg emit_mask_reg
;
260 GLuint tmp_regs
[BRW_WM_MAX_GRF
];
263 GLuint subroutines
[BRW_WM_MAX_SUBROUTINE
];
264 GLuint dispatch_width
;
266 /** we may need up to 3 constants per instruction (if use_const_buffer) */
274 GLuint
brw_wm_nr_args( GLuint opcode
);
275 GLuint
brw_wm_is_scalar_result( GLuint opcode
);
277 void brw_wm_pass_fp( struct brw_wm_compile
*c
);
278 void brw_wm_pass0( struct brw_wm_compile
*c
);
279 void brw_wm_pass1( struct brw_wm_compile
*c
);
280 void brw_wm_pass2( struct brw_wm_compile
*c
);
281 void brw_wm_emit( struct brw_wm_compile
*c
);
283 void brw_wm_print_value( struct brw_wm_compile
*c
,
284 struct brw_wm_value
*value
);
286 void brw_wm_print_ref( struct brw_wm_compile
*c
,
287 struct brw_wm_ref
*ref
);
289 void brw_wm_print_insn( struct brw_wm_compile
*c
,
290 struct brw_wm_instruction
*inst
);
292 void brw_wm_print_program( struct brw_wm_compile
*c
,
295 void brw_wm_lookup_iz( GLuint line_aa
,
297 GLboolean ps_uses_depth
,
298 struct brw_wm_prog_key
*key
);
300 GLboolean
brw_wm_is_glsl(const struct gl_fragment_program
*fp
);
301 void brw_wm_glsl_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
);
303 void emit_ddxy(struct brw_compile
*p
,
304 const struct brw_reg
*dst
,
307 const struct brw_reg
*arg0
);