src/mesa/drivers/dri/i965/brw_wm.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_WM_H
  34 #define BRW_WM_H
  35
  36
  37 #include "shader/prog_instruction.h"
  38 #include "brw_context.h"
  39 #include "brw_eu.h"
  40
  41 /* A big lookup table is used to figure out which and how many
  42  * additional regs will inserted before the main payload in the WM
  43  * program execution.  These mainly relate to depth and stencil
  44  * processing and the early-depth-test optimization.
  45  */
  46 #define IZ_PS_KILL_ALPHATEST_BIT    0x1
  47 #define IZ_PS_COMPUTES_DEPTH_BIT    0x2
  48 #define IZ_DEPTH_WRITE_ENABLE_BIT   0x4
  49 #define IZ_DEPTH_TEST_ENABLE_BIT    0x8
  50 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
  51 #define IZ_STENCIL_TEST_ENABLE_BIT  0x20
  52 #define IZ_BIT_MAX                  0x40
  53
  54 #define AA_NEVER     0
  55 #define AA_SOMETIMES 1
  56 #define AA_ALWAYS    2
  57
  58 struct brw_wm_prog_key {
  59    GLuint source_depth_reg:3;
  60    GLuint aa_dest_stencil_reg:3;
  61    GLuint dest_depth_reg:3;
  62    GLuint nr_depth_regs:3;
  63    GLuint computes_depth:1;     /* could be derived from program string */
  64    GLuint source_depth_to_render_target:1;
  65    GLuint flat_shade:1;
  66    GLuint linear_color:1;  /**< linear interpolation vs perspective interp */
  67    GLuint runtime_check_aads_emit:1;
  68
  69    GLbitfield proj_attrib_mask; /**< one bit per fragment program attribute */
  70    GLuint shadowtex_mask:16;
  71    GLuint yuvtex_mask:16;
  72    GLuint yuvtex_swap_mask:16;  /* UV swaped */
  73
  74    GLuint tex_swizzles[BRW_MAX_TEX_UNIT];
  75
  76    GLuint program_string_id:32;
  77    GLuint origin_x, origin_y;
  78    GLuint drawable_height;
  79    GLuint vp_outputs_written;
  80 };
  81
  82
  83 /* A bit of a glossary:
  84  *
  85  * brw_wm_value: A computed value or program input.  Values are
  86  * constant, they are created once and are never modified.  When a
  87  * fragment program register is written or overwritten, new values are
  88  * created fresh, preserving the rule that values are constant.
  89  *
  90  * brw_wm_ref: A reference to a value.  Wherever a value used is by an
  91  * instruction or as a program output, that is tracked with an
  92  * instance of this struct.  All references to a value occur after it
  93  * is created.  After the last reference, a value is dead and can be
  94  * discarded.
  95  *
  96  * brw_wm_grf: Represents a physical hardware register.  May be either
  97  * empty or hold a value.  Register allocation is the process of
  98  * assigning values to grf registers.  This occurs in pass2 and the
  99  * brw_wm_grf struct is not used before that.
 100  *
 101  * Fragment program registers: These are time-varying constructs that
 102  * are hard to reason about and which we translate away in pass0.  A
 103  * single fragment program register element (eg. temp[0].x) will be
 104  * translated to one or more brw_wm_value structs, one for each time
 105  * that temp[0].x is written to during the program.
 106  */
 107
 108
 109
 110 /* Used in pass2 to track register allocation.
 111  */
 112 struct brw_wm_grf {
 113    struct brw_wm_value *value;
 114    GLuint nextuse;
 115 };
 116
 117 struct brw_wm_value {
 118    struct brw_reg hw_reg;       /* emitted to this reg, may not always be there */
 119    struct brw_wm_ref *lastuse;
 120    struct brw_wm_grf *resident;
 121    GLuint contributes_to_output:1;
 122    GLuint spill_slot:16;        /* if non-zero, spill immediately after calculation */
 123 };
 124
 125 struct brw_wm_ref {
 126    struct brw_reg hw_reg;       /* nr filled in in pass2, everything else, pass0 */
 127    struct brw_wm_value *value;
 128    struct brw_wm_ref *prevuse;
 129    GLuint unspill_reg:7;        /* unspill to reg */
 130    GLuint emitted:1;
 131    GLuint insn:24;
 132 };
 133
 134 struct brw_wm_constref {
 135    const struct brw_wm_ref *ref;
 136    GLfloat constval;
 137 };
 138
 139
 140 struct brw_wm_instruction {
 141    struct brw_wm_value *dst[4];
 142    struct brw_wm_ref *src[3][4];
 143    GLuint opcode:8;
 144    GLuint saturate:1;
 145    GLuint writemask:4;
 146    GLuint tex_unit:4;   /* texture unit for TEX, TXD, TXP instructions */
 147    GLuint tex_idx:3;    /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
 148    GLuint tex_shadow:1; /* do shadow comparison? */
 149    GLuint eot:1;        /* End of thread indicator for FB_WRITE*/
 150    GLuint target:10;    /* target binding table index for FB_WRITE*/
 151 };
 152
 153
 154 #define BRW_WM_MAX_INSN  (MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3)
 155 #define BRW_WM_MAX_GRF   128            /* hardware limit */
 156 #define BRW_WM_MAX_VREG  (BRW_WM_MAX_INSN * 4)
 157 #define BRW_WM_MAX_REF   (BRW_WM_MAX_INSN * 12)
 158 #define BRW_WM_MAX_PARAM 256
 159 #define BRW_WM_MAX_CONST 256
 160 #define BRW_WM_MAX_KILLS MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS
 161 #define BRW_WM_MAX_SUBROUTINE 16
 162
 163
 164
 165 /* New opcodes to track internal operations required for WM unit.
 166  * These are added early so that the registers used can be tracked,
 167  * freed and reused like those of other instructions.
 168  */
 169 #define WM_PIXELXY        (MAX_OPCODE)
 170 #define WM_DELTAXY        (MAX_OPCODE + 1)
 171 #define WM_PIXELW         (MAX_OPCODE + 2)
 172 #define WM_LINTERP        (MAX_OPCODE + 3)
 173 #define WM_PINTERP        (MAX_OPCODE + 4)
 174 #define WM_CINTERP        (MAX_OPCODE + 5)
 175 #define WM_WPOSXY         (MAX_OPCODE + 6)
 176 #define WM_FB_WRITE       (MAX_OPCODE + 7)
 177 #define WM_FRONTFACING    (MAX_OPCODE + 8)
 178 #define MAX_WM_OPCODE     (MAX_OPCODE + 9)
 179
 180 #define PROGRAM_PAYLOAD   (PROGRAM_FILE_MAX)
 181 #define PAYLOAD_DEPTH     (FRAG_ATTRIB_MAX)
 182
 183 struct brw_wm_compile {
 184    struct brw_compile func;
 185    struct brw_wm_prog_key key;
 186    struct brw_wm_prog_data prog_data;
 187
 188    struct brw_fragment_program *fp;
 189
 190    GLfloat (*env_param)[4];
 191
 192    enum {
 193       START,
 194       PASS2_DONE
 195    } state;
 196
 197    /* Initial pass - translate fp instructions to fp instructions,
 198     * simplifying and adding instructions for interpolation and
 199     * framebuffer writes.
 200     */
 201    struct prog_instruction prog_instructions[BRW_WM_MAX_INSN];
 202    GLuint nr_fp_insns;
 203    GLuint fp_temp;
 204    GLuint fp_interp_emitted;
 205    GLuint fp_fragcolor_emitted;
 206    GLuint fp_deriv_emitted;
 207
 208    struct prog_src_register pixel_xy;
 209    struct prog_src_register delta_xy;
 210    struct prog_src_register pixel_w;
 211
 212
 213    struct brw_wm_value vreg[BRW_WM_MAX_VREG];
 214    GLuint nr_vreg;
 215
 216    struct brw_wm_value creg[BRW_WM_MAX_PARAM];
 217    GLuint nr_creg;
 218
 219    struct {
 220       struct brw_wm_value depth[4]; /* includes r0/r1 */
 221       struct brw_wm_value input_interp[FRAG_ATTRIB_MAX];
 222    } payload;
 223
 224
 225    const struct brw_wm_ref *pass0_fp_reg[PROGRAM_PAYLOAD+1][256][4];
 226
 227    struct brw_wm_ref undef_ref;
 228    struct brw_wm_value undef_value;
 229
 230    struct brw_wm_ref refs[BRW_WM_MAX_REF];
 231    GLuint nr_refs;
 232
 233    struct brw_wm_instruction instruction[BRW_WM_MAX_INSN];
 234    GLuint nr_insns;
 235
 236    struct brw_wm_constref constref[BRW_WM_MAX_CONST];
 237    GLuint nr_constrefs;
 238
 239    struct brw_wm_grf pass2_grf[BRW_WM_MAX_GRF/2];
 240
 241    GLuint grf_limit;
 242    GLuint max_wm_grf;
 243    GLuint last_scratch;
 244
 245    GLuint cur_inst;  /**< index of current instruction */
 246
 247    GLboolean out_of_regs;  /**< ran out of GRF registers? */
 248
 249    /** Mapping from Mesa registers to hardware registers */
 250    struct {
 251       GLboolean inited;
 252       struct brw_reg reg;
 253    } wm_regs[PROGRAM_PAYLOAD+1][256][4];
 254
 255    GLboolean used_grf[BRW_WM_MAX_GRF];
 256    GLuint first_free_grf;
 257    struct brw_reg stack;
 258    struct brw_reg emit_mask_reg;
 259    GLuint tmp_regs[BRW_WM_MAX_GRF];
 260    GLuint tmp_index;
 261    GLuint tmp_max;
 262    GLuint subroutines[BRW_WM_MAX_SUBROUTINE];
 263
 264    /** we may need up to 3 constants per instruction (if use_const_buffer) */
 265    struct {
 266       GLint index;
 267       struct brw_reg reg;
 268    } current_const[3];
 269 };
 270
 271
 272 GLuint brw_wm_nr_args( GLuint opcode );
 273 GLuint brw_wm_is_scalar_result( GLuint opcode );
 274
 275 void brw_wm_pass_fp( struct brw_wm_compile *c );
 276 void brw_wm_pass0( struct brw_wm_compile *c );
 277 void brw_wm_pass1( struct brw_wm_compile *c );
 278 void brw_wm_pass2( struct brw_wm_compile *c );
 279 void brw_wm_emit( struct brw_wm_compile *c );
 280
 281 void brw_wm_print_value( struct brw_wm_compile *c,
 282                          struct brw_wm_value *value );
 283
 284 void brw_wm_print_ref( struct brw_wm_compile *c,
 285                        struct brw_wm_ref *ref );
 286
 287 void brw_wm_print_insn( struct brw_wm_compile *c,
 288                         struct brw_wm_instruction *inst );
 289
 290 void brw_wm_print_program( struct brw_wm_compile *c,
 291                            const char *stage );
 292
 293 void brw_wm_lookup_iz( GLuint line_aa,
 294                        GLuint lookup,
 295                        struct brw_wm_prog_key *key );
 296
 297 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp);
 298 void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c);
 299
 300
 301 #endif