2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
37 #include "shader/prog_instruction.h"
38 #include "brw_context.h"
41 #define SATURATE (1<<5)
43 /* A big lookup table is used to figure out which and how many
44 * additional regs will inserted before the main payload in the WM
45 * program execution. These mainly relate to depth and stencil
46 * processing and the early-depth-test optimization.
48 #define IZ_PS_KILL_ALPHATEST_BIT 0x1
49 #define IZ_PS_COMPUTES_DEPTH_BIT 0x2
50 #define IZ_DEPTH_WRITE_ENABLE_BIT 0x4
51 #define IZ_DEPTH_TEST_ENABLE_BIT 0x8
52 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
53 #define IZ_STENCIL_TEST_ENABLE_BIT 0x20
54 #define IZ_BIT_MAX 0x40
57 #define AA_SOMETIMES 1
60 struct brw_wm_prog_key
{
61 GLuint source_depth_reg
:3;
62 GLuint aa_dest_stencil_reg
:3;
63 GLuint dest_depth_reg
:3;
64 GLuint nr_depth_regs
:3;
65 GLuint computes_depth
:1; /* could be derived from program string */
66 GLuint source_depth_to_render_target
:1;
68 GLuint linear_color
:1; /**< linear interpolation vs perspective interp */
69 GLuint runtime_check_aads_emit
:1;
70 GLuint nr_color_regions
:2;
72 GLbitfield proj_attrib_mask
; /**< one bit per fragment program attribute */
73 GLuint shadowtex_mask
:16;
74 GLuint yuvtex_mask
:16;
75 GLuint yuvtex_swap_mask
:16; /* UV swaped */
77 GLushort tex_swizzles
[BRW_MAX_TEX_UNIT
];
79 GLushort origin_x
, origin_y
;
80 GLushort drawable_height
;
81 GLbitfield64 vp_outputs_written
;
82 GLuint program_string_id
:32;
86 /* A bit of a glossary:
88 * brw_wm_value: A computed value or program input. Values are
89 * constant, they are created once and are never modified. When a
90 * fragment program register is written or overwritten, new values are
91 * created fresh, preserving the rule that values are constant.
93 * brw_wm_ref: A reference to a value. Wherever a value used is by an
94 * instruction or as a program output, that is tracked with an
95 * instance of this struct. All references to a value occur after it
96 * is created. After the last reference, a value is dead and can be
99 * brw_wm_grf: Represents a physical hardware register. May be either
100 * empty or hold a value. Register allocation is the process of
101 * assigning values to grf registers. This occurs in pass2 and the
102 * brw_wm_grf struct is not used before that.
104 * Fragment program registers: These are time-varying constructs that
105 * are hard to reason about and which we translate away in pass0. A
106 * single fragment program register element (eg. temp[0].x) will be
107 * translated to one or more brw_wm_value structs, one for each time
108 * that temp[0].x is written to during the program.
113 /* Used in pass2 to track register allocation.
116 struct brw_wm_value
*value
;
120 struct brw_wm_value
{
121 struct brw_reg hw_reg
; /* emitted to this reg, may not always be there */
122 struct brw_wm_ref
*lastuse
;
123 struct brw_wm_grf
*resident
;
124 GLuint contributes_to_output
:1;
125 GLuint spill_slot
:16; /* if non-zero, spill immediately after calculation */
129 struct brw_reg hw_reg
; /* nr filled in in pass2, everything else, pass0 */
130 struct brw_wm_value
*value
;
131 struct brw_wm_ref
*prevuse
;
132 GLuint unspill_reg
:7; /* unspill to reg */
137 struct brw_wm_constref
{
138 const struct brw_wm_ref
*ref
;
143 struct brw_wm_instruction
{
144 struct brw_wm_value
*dst
[4];
145 struct brw_wm_ref
*src
[3][4];
149 GLuint tex_unit
:4; /* texture unit for TEX, TXD, TXP instructions */
150 GLuint tex_idx
:3; /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
151 GLuint tex_shadow
:1; /* do shadow comparison? */
152 GLuint eot
:1; /* End of thread indicator for FB_WRITE*/
153 GLuint target
:10; /* target binding table index for FB_WRITE*/
157 #define BRW_WM_MAX_INSN (MAX_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3)
158 #define BRW_WM_MAX_GRF 128 /* hardware limit */
159 #define BRW_WM_MAX_VREG (BRW_WM_MAX_INSN * 4)
160 #define BRW_WM_MAX_REF (BRW_WM_MAX_INSN * 12)
161 #define BRW_WM_MAX_PARAM 256
162 #define BRW_WM_MAX_CONST 256
163 #define BRW_WM_MAX_SUBROUTINE 16
165 /* used in masks next to WRITEMASK_*. */
166 #define SATURATE (1<<5)
169 /* New opcodes to track internal operations required for WM unit.
170 * These are added early so that the registers used can be tracked,
171 * freed and reused like those of other instructions.
173 #define WM_PIXELXY (MAX_OPCODE)
174 #define WM_DELTAXY (MAX_OPCODE + 1)
175 #define WM_PIXELW (MAX_OPCODE + 2)
176 #define WM_LINTERP (MAX_OPCODE + 3)
177 #define WM_PINTERP (MAX_OPCODE + 4)
178 #define WM_CINTERP (MAX_OPCODE + 5)
179 #define WM_WPOSXY (MAX_OPCODE + 6)
180 #define WM_FB_WRITE (MAX_OPCODE + 7)
181 #define WM_FRONTFACING (MAX_OPCODE + 8)
182 #define MAX_WM_OPCODE (MAX_OPCODE + 9)
184 #define PROGRAM_PAYLOAD (PROGRAM_FILE_MAX)
185 #define PAYLOAD_DEPTH (FRAG_ATTRIB_MAX)
187 struct brw_wm_compile
{
188 struct brw_compile func
;
189 struct brw_wm_prog_key key
;
190 struct brw_wm_prog_data prog_data
;
192 struct brw_fragment_program
*fp
;
194 GLfloat (*env_param
)[4];
201 /* Initial pass - translate fp instructions to fp instructions,
202 * simplifying and adding instructions for interpolation and
203 * framebuffer writes.
205 struct prog_instruction
*prog_instructions
;
208 GLuint fp_interp_emitted
;
209 GLuint fp_fragcolor_emitted
;
211 struct prog_src_register pixel_xy
;
212 struct prog_src_register delta_xy
;
213 struct prog_src_register pixel_w
;
216 struct brw_wm_value
*vreg
;
219 struct brw_wm_value creg
[BRW_WM_MAX_PARAM
];
223 struct brw_wm_value depth
[4]; /* includes r0/r1 */
224 struct brw_wm_value input_interp
[FRAG_ATTRIB_MAX
];
228 const struct brw_wm_ref
*pass0_fp_reg
[PROGRAM_PAYLOAD
+1][256][4];
230 struct brw_wm_ref undef_ref
;
231 struct brw_wm_value undef_value
;
233 struct brw_wm_ref
*refs
;
236 struct brw_wm_instruction
*instruction
;
239 struct brw_wm_constref constref
[BRW_WM_MAX_CONST
];
242 struct brw_wm_grf pass2_grf
[BRW_WM_MAX_GRF
/2];
248 GLuint cur_inst
; /**< index of current instruction */
250 GLboolean out_of_regs
; /**< ran out of GRF registers? */
252 /** Mapping from Mesa registers to hardware registers */
256 } wm_regs
[PROGRAM_PAYLOAD
+1][256][4];
258 GLboolean used_grf
[BRW_WM_MAX_GRF
];
259 GLuint first_free_grf
;
260 struct brw_reg stack
;
261 struct brw_reg emit_mask_reg
;
262 GLuint tmp_regs
[BRW_WM_MAX_GRF
];
265 GLuint subroutines
[BRW_WM_MAX_SUBROUTINE
];
266 GLuint dispatch_width
;
268 /** we may need up to 3 constants per instruction (if use_const_buffer) */
276 /** Bits for prog_instruction::Aux field */
277 #define INST_AUX_EOT 0x1
278 #define INST_AUX_TARGET(T) (T << 1)
279 #define INST_AUX_GET_TARGET(AUX) ((AUX) >> 1)
282 GLuint
brw_wm_nr_args( GLuint opcode
);
283 GLuint
brw_wm_is_scalar_result( GLuint opcode
);
285 void brw_wm_pass_fp( struct brw_wm_compile
*c
);
286 void brw_wm_pass0( struct brw_wm_compile
*c
);
287 void brw_wm_pass1( struct brw_wm_compile
*c
);
288 void brw_wm_pass2( struct brw_wm_compile
*c
);
289 void brw_wm_emit( struct brw_wm_compile
*c
);
291 void brw_wm_print_value( struct brw_wm_compile
*c
,
292 struct brw_wm_value
*value
);
294 void brw_wm_print_ref( struct brw_wm_compile
*c
,
295 struct brw_wm_ref
*ref
);
297 void brw_wm_print_insn( struct brw_wm_compile
*c
,
298 struct brw_wm_instruction
*inst
);
300 void brw_wm_print_program( struct brw_wm_compile
*c
,
303 void brw_wm_lookup_iz( GLuint line_aa
,
305 GLboolean ps_uses_depth
,
306 struct brw_wm_prog_key
*key
);
308 GLboolean
brw_wm_is_glsl(const struct gl_fragment_program
*fp
);
309 void brw_wm_glsl_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
);
312 void emit_alu1(struct brw_compile
*p
,
313 struct brw_instruction
*(*func
)(struct brw_compile
*,
316 const struct brw_reg
*dst
,
318 const struct brw_reg
*arg0
);
319 void emit_alu2(struct brw_compile
*p
,
320 struct brw_instruction
*(*func
)(struct brw_compile
*,
324 const struct brw_reg
*dst
,
326 const struct brw_reg
*arg0
,
327 const struct brw_reg
*arg1
);
328 void emit_cinterp(struct brw_compile
*p
,
329 const struct brw_reg
*dst
,
331 const struct brw_reg
*arg0
);
332 void emit_ddxy(struct brw_compile
*p
,
333 const struct brw_reg
*dst
,
336 const struct brw_reg
*arg0
);
337 void emit_delta_xy(struct brw_compile
*p
,
338 const struct brw_reg
*dst
,
340 const struct brw_reg
*arg0
);
341 void emit_dp3(struct brw_compile
*p
,
342 const struct brw_reg
*dst
,
344 const struct brw_reg
*arg0
,
345 const struct brw_reg
*arg1
);
346 void emit_dp4(struct brw_compile
*p
,
347 const struct brw_reg
*dst
,
349 const struct brw_reg
*arg0
,
350 const struct brw_reg
*arg1
);
351 void emit_dph(struct brw_compile
*p
,
352 const struct brw_reg
*dst
,
354 const struct brw_reg
*arg0
,
355 const struct brw_reg
*arg1
);
356 void emit_fb_write(struct brw_wm_compile
*c
,
357 struct brw_reg
*arg0
,
358 struct brw_reg
*arg1
,
359 struct brw_reg
*arg2
,
362 void emit_frontfacing(struct brw_compile
*p
,
363 const struct brw_reg
*dst
,
365 void emit_linterp(struct brw_compile
*p
,
366 const struct brw_reg
*dst
,
368 const struct brw_reg
*arg0
,
369 const struct brw_reg
*deltas
);
370 void emit_lrp(struct brw_compile
*p
,
371 const struct brw_reg
*dst
,
373 const struct brw_reg
*arg0
,
374 const struct brw_reg
*arg1
,
375 const struct brw_reg
*arg2
);
376 void emit_mad(struct brw_compile
*p
,
377 const struct brw_reg
*dst
,
379 const struct brw_reg
*arg0
,
380 const struct brw_reg
*arg1
,
381 const struct brw_reg
*arg2
);
382 void emit_math1(struct brw_wm_compile
*c
,
384 const struct brw_reg
*dst
,
386 const struct brw_reg
*arg0
);
387 void emit_math2(struct brw_wm_compile
*c
,
389 const struct brw_reg
*dst
,
391 const struct brw_reg
*arg0
,
392 const struct brw_reg
*arg1
);
393 void emit_min(struct brw_compile
*p
,
394 const struct brw_reg
*dst
,
396 const struct brw_reg
*arg0
,
397 const struct brw_reg
*arg1
);
398 void emit_max(struct brw_compile
*p
,
399 const struct brw_reg
*dst
,
401 const struct brw_reg
*arg0
,
402 const struct brw_reg
*arg1
);
403 void emit_pinterp(struct brw_compile
*p
,
404 const struct brw_reg
*dst
,
406 const struct brw_reg
*arg0
,
407 const struct brw_reg
*deltas
,
408 const struct brw_reg
*w
);
409 void emit_pixel_xy(struct brw_wm_compile
*c
,
410 const struct brw_reg
*dst
,
412 void emit_pixel_w(struct brw_wm_compile
*c
,
413 const struct brw_reg
*dst
,
415 const struct brw_reg
*arg0
,
416 const struct brw_reg
*deltas
);
417 void emit_sop(struct brw_compile
*p
,
418 const struct brw_reg
*dst
,
421 const struct brw_reg
*arg0
,
422 const struct brw_reg
*arg1
);
423 void emit_tex(struct brw_wm_compile
*c
,
427 struct brw_reg depth_payload
,
431 void emit_txb(struct brw_wm_compile
*c
,
435 struct brw_reg depth_payload
,
438 void emit_wpos_xy(struct brw_wm_compile
*c
,
439 const struct brw_reg
*dst
,
441 const struct brw_reg
*arg0
);
442 void emit_xpd(struct brw_compile
*p
,
443 const struct brw_reg
*dst
,
445 const struct brw_reg
*arg0
,
446 const struct brw_reg
*arg1
);