2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
38 #include "program/prog_instruction.h"
39 #include "brw_context.h"
42 #define SATURATE (1<<5)
44 /* A big lookup table is used to figure out which and how many
45 * additional regs will inserted before the main payload in the WM
46 * program execution. These mainly relate to depth and stencil
47 * processing and the early-depth-test optimization.
49 #define IZ_PS_KILL_ALPHATEST_BIT 0x1
50 #define IZ_PS_COMPUTES_DEPTH_BIT 0x2
51 #define IZ_DEPTH_WRITE_ENABLE_BIT 0x4
52 #define IZ_DEPTH_TEST_ENABLE_BIT 0x8
53 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
54 #define IZ_STENCIL_TEST_ENABLE_BIT 0x20
55 #define IZ_BIT_MAX 0x40
58 #define AA_SOMETIMES 1
61 struct brw_wm_prog_key
{
62 GLuint source_depth_reg
:3;
63 GLuint source_w_reg
:3;
64 GLuint aa_dest_stencil_reg
:3;
65 GLuint dest_depth_reg
:3;
66 GLuint nr_payload_regs
:4;
67 GLuint computes_depth
:1; /* could be derived from program string */
68 GLuint source_depth_to_render_target
:1;
70 GLuint linear_color
:1; /**< linear interpolation vs perspective interp */
71 GLuint runtime_check_aads_emit
:1;
72 GLuint nr_color_regions
:5;
73 GLuint render_to_fbo
:1;
75 GLbitfield proj_attrib_mask
; /**< one bit per fragment program attribute */
76 GLuint shadowtex_mask
:16;
77 GLuint yuvtex_mask
:16;
78 GLuint yuvtex_swap_mask
:16; /* UV swaped */
80 GLushort tex_swizzles
[BRW_MAX_TEX_UNIT
];
82 GLushort drawable_height
;
83 GLbitfield64 vp_outputs_written
;
84 GLuint program_string_id
:32;
88 /* A bit of a glossary:
90 * brw_wm_value: A computed value or program input. Values are
91 * constant, they are created once and are never modified. When a
92 * fragment program register is written or overwritten, new values are
93 * created fresh, preserving the rule that values are constant.
95 * brw_wm_ref: A reference to a value. Wherever a value used is by an
96 * instruction or as a program output, that is tracked with an
97 * instance of this struct. All references to a value occur after it
98 * is created. After the last reference, a value is dead and can be
101 * brw_wm_grf: Represents a physical hardware register. May be either
102 * empty or hold a value. Register allocation is the process of
103 * assigning values to grf registers. This occurs in pass2 and the
104 * brw_wm_grf struct is not used before that.
106 * Fragment program registers: These are time-varying constructs that
107 * are hard to reason about and which we translate away in pass0. A
108 * single fragment program register element (eg. temp[0].x) will be
109 * translated to one or more brw_wm_value structs, one for each time
110 * that temp[0].x is written to during the program.
115 /* Used in pass2 to track register allocation.
118 struct brw_wm_value
*value
;
122 struct brw_wm_value
{
123 struct brw_reg hw_reg
; /* emitted to this reg, may not always be there */
124 struct brw_wm_ref
*lastuse
;
125 struct brw_wm_grf
*resident
;
126 GLuint contributes_to_output
:1;
127 GLuint spill_slot
:16; /* if non-zero, spill immediately after calculation */
131 struct brw_reg hw_reg
; /* nr filled in in pass2, everything else, pass0 */
132 struct brw_wm_value
*value
;
133 struct brw_wm_ref
*prevuse
;
134 GLuint unspill_reg
:7; /* unspill to reg */
139 struct brw_wm_constref
{
140 const struct brw_wm_ref
*ref
;
145 struct brw_wm_instruction
{
146 struct brw_wm_value
*dst
[4];
147 struct brw_wm_ref
*src
[3][4];
151 GLuint tex_unit
:4; /* texture unit for TEX, TXD, TXP instructions */
152 GLuint tex_idx
:3; /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
153 GLuint tex_shadow
:1; /* do shadow comparison? */
154 GLuint eot
:1; /* End of thread indicator for FB_WRITE*/
155 GLuint target
:10; /* target binding table index for FB_WRITE*/
159 #define BRW_WM_MAX_INSN (MAX_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3)
160 #define BRW_WM_MAX_GRF 128 /* hardware limit */
161 #define BRW_WM_MAX_VREG (BRW_WM_MAX_INSN * 4)
162 #define BRW_WM_MAX_REF (BRW_WM_MAX_INSN * 12)
163 #define BRW_WM_MAX_PARAM 256
164 #define BRW_WM_MAX_CONST 256
165 #define BRW_WM_MAX_SUBROUTINE 16
167 /* used in masks next to WRITEMASK_*. */
168 #define SATURATE (1<<5)
171 /* New opcodes to track internal operations required for WM unit.
172 * These are added early so that the registers used can be tracked,
173 * freed and reused like those of other instructions.
175 #define WM_PIXELXY (MAX_OPCODE)
176 #define WM_DELTAXY (MAX_OPCODE + 1)
177 #define WM_PIXELW (MAX_OPCODE + 2)
178 #define WM_LINTERP (MAX_OPCODE + 3)
179 #define WM_PINTERP (MAX_OPCODE + 4)
180 #define WM_CINTERP (MAX_OPCODE + 5)
181 #define WM_WPOSXY (MAX_OPCODE + 6)
182 #define WM_FB_WRITE (MAX_OPCODE + 7)
183 #define WM_FRONTFACING (MAX_OPCODE + 8)
184 #define MAX_WM_OPCODE (MAX_OPCODE + 9)
186 #define PROGRAM_PAYLOAD (PROGRAM_FILE_MAX)
187 #define NUM_FILES (PROGRAM_PAYLOAD + 1)
189 #define PAYLOAD_DEPTH (FRAG_ATTRIB_MAX)
190 #define PAYLOAD_W (FRAG_ATTRIB_MAX + 1)
191 #define PAYLOAD_FP_REG_MAX (FRAG_ATTRIB_MAX + 2)
193 struct brw_wm_compile
{
194 struct brw_compile func
;
195 struct brw_wm_prog_key key
;
196 struct brw_wm_prog_data prog_data
;
198 struct brw_fragment_program
*fp
;
200 GLfloat (*env_param
)[4];
207 /* Initial pass - translate fp instructions to fp instructions,
208 * simplifying and adding instructions for interpolation and
209 * framebuffer writes.
211 struct prog_instruction
*prog_instructions
;
214 GLuint fp_interp_emitted
;
215 GLuint fp_fragcolor_emitted
;
217 struct prog_src_register pixel_xy
;
218 struct prog_src_register delta_xy
;
219 struct prog_src_register pixel_w
;
222 struct brw_wm_value
*vreg
;
225 struct brw_wm_value creg
[BRW_WM_MAX_PARAM
];
229 struct brw_wm_value depth
[4]; /* includes r0/r1 */
230 struct brw_wm_value input_interp
[FRAG_ATTRIB_MAX
];
234 const struct brw_wm_ref
*pass0_fp_reg
[NUM_FILES
][256][4];
236 struct brw_wm_ref undef_ref
;
237 struct brw_wm_value undef_value
;
239 struct brw_wm_ref
*refs
;
242 struct brw_wm_instruction
*instruction
;
245 struct brw_wm_constref constref
[BRW_WM_MAX_CONST
];
248 struct brw_wm_grf pass2_grf
[BRW_WM_MAX_GRF
/2];
254 GLuint cur_inst
; /**< index of current instruction */
256 GLboolean out_of_regs
; /**< ran out of GRF registers? */
258 /** Mapping from Mesa registers to hardware registers */
262 } wm_regs
[NUM_FILES
][256][4];
264 GLboolean used_grf
[BRW_WM_MAX_GRF
];
265 GLuint first_free_grf
;
266 struct brw_reg stack
;
267 struct brw_reg emit_mask_reg
;
268 GLuint tmp_regs
[BRW_WM_MAX_GRF
];
271 GLuint subroutines
[BRW_WM_MAX_SUBROUTINE
];
272 GLuint dispatch_width
;
274 /** we may need up to 3 constants per instruction (if use_const_buffer) */
282 /** Bits for prog_instruction::Aux field */
283 #define INST_AUX_EOT 0x1
284 #define INST_AUX_TARGET(T) (T << 1)
285 #define INST_AUX_GET_TARGET(AUX) ((AUX) >> 1)
288 GLuint
brw_wm_nr_args( GLuint opcode
);
289 GLuint
brw_wm_is_scalar_result( GLuint opcode
);
291 void brw_wm_pass_fp( struct brw_wm_compile
*c
);
292 void brw_wm_pass0( struct brw_wm_compile
*c
);
293 void brw_wm_pass1( struct brw_wm_compile
*c
);
294 void brw_wm_pass2( struct brw_wm_compile
*c
);
295 void brw_wm_emit( struct brw_wm_compile
*c
);
296 GLboolean
brw_wm_arg_can_be_immediate(enum prog_opcode
, int arg
);
297 void brw_wm_print_value( struct brw_wm_compile
*c
,
298 struct brw_wm_value
*value
);
300 void brw_wm_print_ref( struct brw_wm_compile
*c
,
301 struct brw_wm_ref
*ref
);
303 void brw_wm_print_insn( struct brw_wm_compile
*c
,
304 struct brw_wm_instruction
*inst
);
306 void brw_wm_print_program( struct brw_wm_compile
*c
,
309 void brw_wm_lookup_iz( struct intel_context
*intel
,
312 GLboolean ps_uses_depth
,
313 struct brw_wm_prog_key
*key
);
315 GLboolean
brw_wm_is_glsl(const struct gl_fragment_program
*fp
);
316 void brw_wm_glsl_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
);
317 GLboolean
brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
);
320 void emit_alu1(struct brw_compile
*p
,
321 struct brw_instruction
*(*func
)(struct brw_compile
*,
324 const struct brw_reg
*dst
,
326 const struct brw_reg
*arg0
);
327 void emit_alu2(struct brw_compile
*p
,
328 struct brw_instruction
*(*func
)(struct brw_compile
*,
332 const struct brw_reg
*dst
,
334 const struct brw_reg
*arg0
,
335 const struct brw_reg
*arg1
);
336 void emit_cinterp(struct brw_compile
*p
,
337 const struct brw_reg
*dst
,
339 const struct brw_reg
*arg0
);
340 void emit_cmp(struct brw_compile
*p
,
341 const struct brw_reg
*dst
,
343 const struct brw_reg
*arg0
,
344 const struct brw_reg
*arg1
,
345 const struct brw_reg
*arg2
);
346 void emit_ddxy(struct brw_compile
*p
,
347 const struct brw_reg
*dst
,
350 const struct brw_reg
*arg0
);
351 void emit_delta_xy(struct brw_compile
*p
,
352 const struct brw_reg
*dst
,
354 const struct brw_reg
*arg0
);
355 void emit_dp2(struct brw_compile
*p
,
356 const struct brw_reg
*dst
,
358 const struct brw_reg
*arg0
,
359 const struct brw_reg
*arg1
);
360 void emit_dp3(struct brw_compile
*p
,
361 const struct brw_reg
*dst
,
363 const struct brw_reg
*arg0
,
364 const struct brw_reg
*arg1
);
365 void emit_dp4(struct brw_compile
*p
,
366 const struct brw_reg
*dst
,
368 const struct brw_reg
*arg0
,
369 const struct brw_reg
*arg1
);
370 void emit_dph(struct brw_compile
*p
,
371 const struct brw_reg
*dst
,
373 const struct brw_reg
*arg0
,
374 const struct brw_reg
*arg1
);
375 void emit_fb_write(struct brw_wm_compile
*c
,
376 struct brw_reg
*arg0
,
377 struct brw_reg
*arg1
,
378 struct brw_reg
*arg2
,
381 void emit_frontfacing(struct brw_compile
*p
,
382 const struct brw_reg
*dst
,
384 void emit_kil_nv(struct brw_wm_compile
*c
);
385 void emit_linterp(struct brw_compile
*p
,
386 const struct brw_reg
*dst
,
388 const struct brw_reg
*arg0
,
389 const struct brw_reg
*deltas
);
390 void emit_lrp(struct brw_compile
*p
,
391 const struct brw_reg
*dst
,
393 const struct brw_reg
*arg0
,
394 const struct brw_reg
*arg1
,
395 const struct brw_reg
*arg2
);
396 void emit_mad(struct brw_compile
*p
,
397 const struct brw_reg
*dst
,
399 const struct brw_reg
*arg0
,
400 const struct brw_reg
*arg1
,
401 const struct brw_reg
*arg2
);
402 void emit_math1(struct brw_wm_compile
*c
,
404 const struct brw_reg
*dst
,
406 const struct brw_reg
*arg0
);
407 void emit_math2(struct brw_wm_compile
*c
,
409 const struct brw_reg
*dst
,
411 const struct brw_reg
*arg0
,
412 const struct brw_reg
*arg1
);
413 void emit_min(struct brw_compile
*p
,
414 const struct brw_reg
*dst
,
416 const struct brw_reg
*arg0
,
417 const struct brw_reg
*arg1
);
418 void emit_max(struct brw_compile
*p
,
419 const struct brw_reg
*dst
,
421 const struct brw_reg
*arg0
,
422 const struct brw_reg
*arg1
);
423 void emit_pinterp(struct brw_compile
*p
,
424 const struct brw_reg
*dst
,
426 const struct brw_reg
*arg0
,
427 const struct brw_reg
*deltas
,
428 const struct brw_reg
*w
);
429 void emit_pixel_xy(struct brw_wm_compile
*c
,
430 const struct brw_reg
*dst
,
432 void emit_pixel_w(struct brw_wm_compile
*c
,
433 const struct brw_reg
*dst
,
435 const struct brw_reg
*arg0
,
436 const struct brw_reg
*deltas
);
437 void emit_sop(struct brw_compile
*p
,
438 const struct brw_reg
*dst
,
441 const struct brw_reg
*arg0
,
442 const struct brw_reg
*arg1
);
443 void emit_sign(struct brw_compile
*p
,
444 const struct brw_reg
*dst
,
446 const struct brw_reg
*arg0
);
447 void emit_tex(struct brw_wm_compile
*c
,
451 struct brw_reg depth_payload
,
455 void emit_txb(struct brw_wm_compile
*c
,
459 struct brw_reg depth_payload
,
462 void emit_wpos_xy(struct brw_wm_compile
*c
,
463 const struct brw_reg
*dst
,
465 const struct brw_reg
*arg0
);
466 void emit_xpd(struct brw_compile
*p
,
467 const struct brw_reg
*dst
,
469 const struct brw_reg
*arg0
,
470 const struct brw_reg
*arg1
);
472 GLboolean
brw_compile_shader(struct gl_context
*ctx
,
473 struct gl_shader
*shader
);
474 GLboolean
brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
);
475 struct gl_shader
*brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
);
476 struct gl_shader_program
*brw_new_shader_program(struct gl_context
*ctx
, GLuint name
);
478 bool brw_color_buffer_write_enabled(struct brw_context
*brw
);