2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
38 #include "program/prog_instruction.h"
39 #include "brw_context.h"
41 #include "brw_program.h"
43 #define SATURATE (1<<5)
45 /* A big lookup table is used to figure out which and how many
46 * additional regs will inserted before the main payload in the WM
47 * program execution. These mainly relate to depth and stencil
48 * processing and the early-depth-test optimization.
50 #define IZ_PS_KILL_ALPHATEST_BIT 0x1
51 #define IZ_PS_COMPUTES_DEPTH_BIT 0x2
52 #define IZ_DEPTH_WRITE_ENABLE_BIT 0x4
53 #define IZ_DEPTH_TEST_ENABLE_BIT 0x8
54 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
55 #define IZ_STENCIL_TEST_ENABLE_BIT 0x20
56 #define IZ_BIT_MAX 0x40
59 #define AA_SOMETIMES 1
62 struct brw_wm_prog_key
{
66 GLuint nr_color_regions
:5;
67 GLuint sample_alpha_to_coverage
:1;
68 GLuint render_to_fbo
:1;
69 GLuint clamp_fragment_color
:1;
72 GLbitfield proj_attrib_mask
; /**< one bit per fragment program attribute */
74 GLushort drawable_height
;
75 GLbitfield64 vp_outputs_written
;
76 GLuint program_string_id
:32;
78 struct brw_sampler_prog_key_data tex
;
82 /* A bit of a glossary:
84 * brw_wm_value: A computed value or program input. Values are
85 * constant, they are created once and are never modified. When a
86 * fragment program register is written or overwritten, new values are
87 * created fresh, preserving the rule that values are constant.
89 * brw_wm_ref: A reference to a value. Wherever a value used is by an
90 * instruction or as a program output, that is tracked with an
91 * instance of this struct. All references to a value occur after it
92 * is created. After the last reference, a value is dead and can be
95 * brw_wm_grf: Represents a physical hardware register. May be either
96 * empty or hold a value. Register allocation is the process of
97 * assigning values to grf registers. This occurs in pass2 and the
98 * brw_wm_grf struct is not used before that.
100 * Fragment program registers: These are time-varying constructs that
101 * are hard to reason about and which we translate away in pass0. A
102 * single fragment program register element (eg. temp[0].x) will be
103 * translated to one or more brw_wm_value structs, one for each time
104 * that temp[0].x is written to during the program.
109 /* Used in pass2 to track register allocation.
112 struct brw_wm_value
*value
;
116 struct brw_wm_value
{
117 struct brw_reg hw_reg
; /* emitted to this reg, may not always be there */
118 struct brw_wm_ref
*lastuse
;
119 struct brw_wm_grf
*resident
;
120 GLuint contributes_to_output
:1;
121 GLuint spill_slot
:16; /* if non-zero, spill immediately after calculation */
125 struct brw_reg hw_reg
; /* nr filled in in pass2, everything else, pass0 */
126 struct brw_wm_value
*value
;
127 struct brw_wm_ref
*prevuse
;
128 GLuint unspill_reg
:7; /* unspill to reg */
133 struct brw_wm_constref
{
134 const struct brw_wm_ref
*ref
;
139 struct brw_wm_instruction
{
140 struct brw_wm_value
*dst
[4];
141 struct brw_wm_ref
*src
[3][4];
145 GLuint tex_unit
:4; /* texture unit for TEX, TXD, TXP instructions */
146 GLuint tex_idx
:4; /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
147 GLuint tex_shadow
:1; /* do shadow comparison? */
148 GLuint eot
:1; /* End of thread indicator for FB_WRITE*/
149 GLuint target
:10; /* target binding table index for FB_WRITE*/
153 #define BRW_WM_MAX_INSN (MAX_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3)
154 #define BRW_WM_MAX_GRF 128 /* hardware limit */
155 #define BRW_WM_MAX_VREG (BRW_WM_MAX_INSN * 4)
156 #define BRW_WM_MAX_REF (BRW_WM_MAX_INSN * 12)
157 #define BRW_WM_MAX_PARAM 256
158 #define BRW_WM_MAX_CONST 256
159 #define BRW_WM_MAX_SUBROUTINE 16
161 /* used in masks next to WRITEMASK_*. */
162 #define SATURATE (1<<5)
165 /* New opcodes to track internal operations required for WM unit.
166 * These are added early so that the registers used can be tracked,
167 * freed and reused like those of other instructions.
169 #define WM_PIXELXY (MAX_OPCODE)
170 #define WM_DELTAXY (MAX_OPCODE + 1)
171 #define WM_PIXELW (MAX_OPCODE + 2)
172 #define WM_LINTERP (MAX_OPCODE + 3)
173 #define WM_PINTERP (MAX_OPCODE + 4)
174 #define WM_CINTERP (MAX_OPCODE + 5)
175 #define WM_WPOSXY (MAX_OPCODE + 6)
176 #define WM_FB_WRITE (MAX_OPCODE + 7)
177 #define WM_FRONTFACING (MAX_OPCODE + 8)
178 #define MAX_WM_OPCODE (MAX_OPCODE + 9)
180 #define PROGRAM_PAYLOAD (PROGRAM_FILE_MAX)
181 #define NUM_FILES (PROGRAM_PAYLOAD + 1)
183 #define PAYLOAD_DEPTH (FRAG_ATTRIB_MAX)
184 #define PAYLOAD_W (FRAG_ATTRIB_MAX + 1)
185 #define PAYLOAD_FP_REG_MAX (FRAG_ATTRIB_MAX + 2)
187 struct brw_wm_compile
{
188 struct brw_compile func
;
189 struct brw_wm_prog_key key
;
190 struct brw_wm_prog_data prog_data
;
192 struct brw_fragment_program
*fp
;
194 GLfloat (*env_param
)[4];
201 uint8_t source_depth_reg
;
202 uint8_t source_w_reg
;
203 uint8_t aa_dest_stencil_reg
;
204 uint8_t dest_depth_reg
;
205 uint8_t barycentric_coord_reg
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
206 uint8_t nr_payload_regs
;
207 GLuint computes_depth
:1; /* could be derived from program string */
208 GLuint source_depth_to_render_target
:1;
209 GLuint runtime_check_aads_emit
:1;
211 /* Initial pass - translate fp instructions to fp instructions,
212 * simplifying and adding instructions for interpolation and
213 * framebuffer writes.
215 struct prog_instruction
*prog_instructions
;
218 GLuint fp_interp_emitted
;
220 struct prog_src_register pixel_xy
;
221 struct prog_src_register delta_xy
;
222 struct prog_src_register pixel_w
;
225 struct brw_wm_value
*vreg
;
228 struct brw_wm_value creg
[BRW_WM_MAX_PARAM
];
232 struct brw_wm_value depth
[4]; /* includes r0/r1 */
233 struct brw_wm_value input_interp
[FRAG_ATTRIB_MAX
];
237 const struct brw_wm_ref
*pass0_fp_reg
[NUM_FILES
][256][4];
239 struct brw_wm_ref undef_ref
;
240 struct brw_wm_value undef_value
;
242 struct brw_wm_ref
*refs
;
245 struct brw_wm_instruction
*instruction
;
248 struct brw_wm_constref constref
[BRW_WM_MAX_CONST
];
251 struct brw_wm_grf pass2_grf
[BRW_WM_MAX_GRF
/2];
257 GLuint cur_inst
; /**< index of current instruction */
259 bool out_of_regs
; /**< ran out of GRF registers? */
261 /** Mapping from Mesa registers to hardware registers */
265 } wm_regs
[NUM_FILES
][256][4];
267 bool used_grf
[BRW_WM_MAX_GRF
];
268 GLuint first_free_grf
;
269 struct brw_reg stack
;
270 struct brw_reg emit_mask_reg
;
271 GLuint tmp_regs
[BRW_WM_MAX_GRF
];
274 GLuint subroutines
[BRW_WM_MAX_SUBROUTINE
];
275 GLuint dispatch_width
;
277 /** we may need up to 3 constants per instruction (if use_const_buffer) */
285 /** Bits for prog_instruction::Aux field */
286 #define INST_AUX_EOT 0x1
287 #define INST_AUX_TARGET(T) (T << 1)
288 #define INST_AUX_GET_TARGET(AUX) ((AUX) >> 1)
291 GLuint
brw_wm_nr_args( GLuint opcode
);
292 GLuint
brw_wm_is_scalar_result( GLuint opcode
);
294 void brw_wm_pass_fp( struct brw_wm_compile
*c
);
295 void brw_wm_pass0( struct brw_wm_compile
*c
);
296 void brw_wm_pass1( struct brw_wm_compile
*c
);
297 void brw_wm_pass2( struct brw_wm_compile
*c
);
298 void brw_wm_emit( struct brw_wm_compile
*c
);
299 bool brw_wm_arg_can_be_immediate(enum prog_opcode
, int arg
);
300 void brw_wm_print_value( struct brw_wm_compile
*c
,
301 struct brw_wm_value
*value
);
303 void brw_wm_print_ref( struct brw_wm_compile
*c
,
304 struct brw_wm_ref
*ref
);
306 void brw_wm_print_insn( struct brw_wm_compile
*c
,
307 struct brw_wm_instruction
*inst
);
309 void brw_wm_print_program( struct brw_wm_compile
*c
,
312 void brw_wm_lookup_iz(struct intel_context
*intel
,
313 struct brw_wm_compile
*c
);
315 bool brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
,
316 struct gl_shader_program
*prog
);
319 void emit_alu1(struct brw_compile
*p
,
320 struct brw_instruction
*(*func
)(struct brw_compile
*,
323 const struct brw_reg
*dst
,
325 const struct brw_reg
*arg0
);
326 void emit_alu2(struct brw_compile
*p
,
327 struct brw_instruction
*(*func
)(struct brw_compile
*,
331 const struct brw_reg
*dst
,
333 const struct brw_reg
*arg0
,
334 const struct brw_reg
*arg1
);
335 void emit_cinterp(struct brw_compile
*p
,
336 const struct brw_reg
*dst
,
338 const struct brw_reg
*arg0
);
339 void emit_cmp(struct brw_compile
*p
,
340 const struct brw_reg
*dst
,
342 const struct brw_reg
*arg0
,
343 const struct brw_reg
*arg1
,
344 const struct brw_reg
*arg2
);
345 void emit_ddxy(struct brw_compile
*p
,
346 const struct brw_reg
*dst
,
349 const struct brw_reg
*arg0
,
351 void emit_delta_xy(struct brw_compile
*p
,
352 const struct brw_reg
*dst
,
354 const struct brw_reg
*arg0
);
355 void emit_dp2(struct brw_compile
*p
,
356 const struct brw_reg
*dst
,
358 const struct brw_reg
*arg0
,
359 const struct brw_reg
*arg1
);
360 void emit_dp3(struct brw_compile
*p
,
361 const struct brw_reg
*dst
,
363 const struct brw_reg
*arg0
,
364 const struct brw_reg
*arg1
);
365 void emit_dp4(struct brw_compile
*p
,
366 const struct brw_reg
*dst
,
368 const struct brw_reg
*arg0
,
369 const struct brw_reg
*arg1
);
370 void emit_dph(struct brw_compile
*p
,
371 const struct brw_reg
*dst
,
373 const struct brw_reg
*arg0
,
374 const struct brw_reg
*arg1
);
375 void emit_fb_write(struct brw_wm_compile
*c
,
376 struct brw_reg
*arg0
,
377 struct brw_reg
*arg1
,
378 struct brw_reg
*arg2
,
381 void emit_frontfacing(struct brw_compile
*p
,
382 const struct brw_reg
*dst
,
384 void emit_linterp(struct brw_compile
*p
,
385 const struct brw_reg
*dst
,
387 const struct brw_reg
*arg0
,
388 const struct brw_reg
*deltas
);
389 void emit_lrp(struct brw_compile
*p
,
390 const struct brw_reg
*dst
,
392 const struct brw_reg
*arg0
,
393 const struct brw_reg
*arg1
,
394 const struct brw_reg
*arg2
);
395 void emit_mad(struct brw_compile
*p
,
396 const struct brw_reg
*dst
,
398 const struct brw_reg
*arg0
,
399 const struct brw_reg
*arg1
,
400 const struct brw_reg
*arg2
);
401 void emit_math1(struct brw_wm_compile
*c
,
403 const struct brw_reg
*dst
,
405 const struct brw_reg
*arg0
);
406 void emit_math2(struct brw_wm_compile
*c
,
408 const struct brw_reg
*dst
,
410 const struct brw_reg
*arg0
,
411 const struct brw_reg
*arg1
);
412 void emit_min(struct brw_compile
*p
,
413 const struct brw_reg
*dst
,
415 const struct brw_reg
*arg0
,
416 const struct brw_reg
*arg1
);
417 void emit_max(struct brw_compile
*p
,
418 const struct brw_reg
*dst
,
420 const struct brw_reg
*arg0
,
421 const struct brw_reg
*arg1
);
422 void emit_pinterp(struct brw_compile
*p
,
423 const struct brw_reg
*dst
,
425 const struct brw_reg
*arg0
,
426 const struct brw_reg
*deltas
,
427 const struct brw_reg
*w
);
428 void emit_pixel_xy(struct brw_wm_compile
*c
,
429 const struct brw_reg
*dst
,
431 void emit_pixel_w(struct brw_wm_compile
*c
,
432 const struct brw_reg
*dst
,
434 const struct brw_reg
*arg0
,
435 const struct brw_reg
*deltas
);
436 void emit_sop(struct brw_compile
*p
,
437 const struct brw_reg
*dst
,
440 const struct brw_reg
*arg0
,
441 const struct brw_reg
*arg1
);
442 void emit_sign(struct brw_compile
*p
,
443 const struct brw_reg
*dst
,
445 const struct brw_reg
*arg0
);
446 void emit_tex(struct brw_wm_compile
*c
,
450 struct brw_reg depth_payload
,
454 void emit_txb(struct brw_wm_compile
*c
,
458 struct brw_reg depth_payload
,
461 void emit_wpos_xy(struct brw_wm_compile
*c
,
462 const struct brw_reg
*dst
,
464 const struct brw_reg
*arg0
);
465 void emit_xpd(struct brw_compile
*p
,
466 const struct brw_reg
*dst
,
468 const struct brw_reg
*arg0
,
469 const struct brw_reg
*arg1
);
471 GLboolean
brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
);
472 struct gl_shader
*brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
);
473 struct gl_shader_program
*brw_new_shader_program(struct gl_context
*ctx
, GLuint name
);
475 bool brw_color_buffer_write_enabled(struct brw_context
*brw
);
476 bool brw_render_target_supported(struct intel_context
*intel
,
477 struct gl_renderbuffer
*rb
);
478 void brw_wm_payload_setup(struct brw_context
*brw
,
479 struct brw_wm_compile
*c
);
480 bool do_wm_prog(struct brw_context
*brw
,
481 struct gl_shader_program
*prog
,
482 struct brw_fragment_program
*fp
,
483 struct brw_wm_prog_key
*key
);
484 void brw_wm_debug_recompile(struct brw_context
*brw
,
485 struct gl_shader_program
*prog
,
486 const struct brw_wm_prog_key
*key
);