src/mesa/drivers/dri/i965/brw_wm_glsl.c

   1 #include "main/macros.h"
   2 #include "program/prog_parameter.h"
   3 #include "program/prog_print.h"
   4 #include "program/prog_optimize.h"
   5 #include "brw_context.h"
   6 #include "brw_eu.h"
   7 #include "brw_wm.h"
   8
   9 static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
  10                                   const struct prog_instruction *inst,
  11                                   GLuint component);
  12
  13 /**
  14  * Determine if the given fragment program uses GLSL features such
  15  * as flow conditionals, loops, subroutines.
  16  * Some GLSL shaders may use these features, others might not.
  17  */
  18 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp)
  19 {
  20     int i;
  21
  22     if (INTEL_DEBUG & DEBUG_GLSL_FORCE)
  23        return GL_TRUE;
  24
  25     for (i = 0; i < fp->Base.NumInstructions; i++) {
  26         const struct prog_instruction *inst = &fp->Base.Instructions[i];
  27         switch (inst->Opcode) {
  28             case OPCODE_ARL:
  29             case OPCODE_IF:
  30             case OPCODE_ENDIF:
  31             case OPCODE_CAL:
  32             case OPCODE_BRK:
  33             case OPCODE_RET:
  34             case OPCODE_BGNLOOP:
  35                 return GL_TRUE;
  36             default:
  37                 break;
  38         }
  39     }
  40     return GL_FALSE;
  41 }
  42
  43
  44
  45 static void
  46 reclaim_temps(struct brw_wm_compile *c);
  47
  48
  49 /** Mark GRF register as used. */
  50 static void
  51 prealloc_grf(struct brw_wm_compile *c, int r)
  52 {
  53    c->used_grf[r] = GL_TRUE;
  54 }
  55
  56
  57 /** Mark given GRF register as not in use. */
  58 static void
  59 release_grf(struct brw_wm_compile *c, int r)
  60 {
  61    /*assert(c->used_grf[r]);*/
  62    c->used_grf[r] = GL_FALSE;
  63    c->first_free_grf = MIN2(c->first_free_grf, r);
  64 }
  65
  66
  67 /** Return index of a free GRF, mark it as used. */
  68 static int
  69 alloc_grf(struct brw_wm_compile *c)
  70 {
  71    GLuint r;
  72    for (r = c->first_free_grf; r < BRW_WM_MAX_GRF; r++) {
  73       if (!c->used_grf[r]) {
  74          c->used_grf[r] = GL_TRUE;
  75          c->first_free_grf = r + 1;  /* a guess */
  76          return r;
  77       }
  78    }
  79
  80    /* no free temps, try to reclaim some */
  81    reclaim_temps(c);
  82    c->first_free_grf = 0;
  83
  84    /* try alloc again */
  85    for (r = c->first_free_grf; r < BRW_WM_MAX_GRF; r++) {
  86       if (!c->used_grf[r]) {
  87          c->used_grf[r] = GL_TRUE;
  88          c->first_free_grf = r + 1;  /* a guess */
  89          return r;
  90       }
  91    }
  92
  93    for (r = 0; r < BRW_WM_MAX_GRF; r++) {
  94       assert(c->used_grf[r]);
  95    }
  96
  97    /* really, no free GRF regs found */
  98    if (!c->out_of_regs) {
  99       /* print warning once per compilation */
 100       _mesa_warning(NULL, "i965: ran out of registers for fragment program");
 101       c->out_of_regs = GL_TRUE;
 102    }
 103
 104    return -1;
 105 }
 106
 107
 108 /** Return number of GRF registers used */
 109 static int
 110 num_grf_used(const struct brw_wm_compile *c)
 111 {
 112    int r;
 113    for (r = BRW_WM_MAX_GRF - 1; r >= 0; r--)
 114       if (c->used_grf[r])
 115          return r + 1;
 116    return 0;
 117 }
 118
 119
 120
 121 /**
 122  * Record the mapping of a Mesa register to a hardware register.
 123  */
 124 static void set_reg(struct brw_wm_compile *c, int file, int index,
 125         int component, struct brw_reg reg)
 126 {
 127     c->wm_regs[file][index][component].reg = reg;
 128     c->wm_regs[file][index][component].inited = GL_TRUE;
 129 }
 130
 131 static struct brw_reg alloc_tmp(struct brw_wm_compile *c)
 132 {
 133     struct brw_reg reg;
 134
 135     /* if we need to allocate another temp, grow the tmp_regs[] array */
 136     if (c->tmp_index == c->tmp_max) {
 137        int r = alloc_grf(c);
 138        if (r < 0) {
 139           /*printf("Out of temps in %s\n", __FUNCTION__);*/
 140           r = 50; /* XXX random register! */
 141        }
 142        c->tmp_regs[ c->tmp_max++ ] = r;
 143     }
 144
 145     /* form the GRF register */
 146     reg = brw_vec8_grf(c->tmp_regs[ c->tmp_index++ ], 0);
 147     /*printf("alloc_temp %d\n", reg.nr);*/
 148     assert(reg.nr < BRW_WM_MAX_GRF);
 149     return reg;
 150
 151 }
 152
 153 /**
 154  * Save current temp register info.
 155  * There must be a matching call to release_tmps().
 156  */
 157 static int mark_tmps(struct brw_wm_compile *c)
 158 {
 159     return c->tmp_index;
 160 }
 161
 162 static void release_tmps(struct brw_wm_compile *c, int mark)
 163 {
 164     c->tmp_index = mark;
 165 }
 166
 167 /**
 168  * Convert Mesa src register to brw register.
 169  *
 170  * Since we're running in SOA mode each Mesa register corresponds to four
 171  * hardware registers.  We allocate the hardware registers as needed here.
 172  *
 173  * \param file  register file, one of PROGRAM_x
 174  * \param index  register number
 175  * \param component  src component (X=0, Y=1, Z=2, W=3)
 176  * \param nr  not used?!?
 177  * \param neg  negate value?
 178  * \param abs  take absolute value?
 179  */
 180 static struct brw_reg
 181 get_reg(struct brw_wm_compile *c, int file, int index, int component,
 182         int nr, GLuint neg, GLuint abs)
 183 {
 184     struct brw_reg reg;
 185     switch (file) {
 186         case PROGRAM_STATE_VAR:
 187         case PROGRAM_CONSTANT:
 188         case PROGRAM_UNIFORM:
 189             file = PROGRAM_STATE_VAR;
 190             break;
 191         case PROGRAM_UNDEFINED:
 192             return brw_null_reg();
 193         case PROGRAM_TEMPORARY:
 194         case PROGRAM_INPUT:
 195         case PROGRAM_OUTPUT:
 196         case PROGRAM_PAYLOAD:
 197             break;
 198         default:
 199             _mesa_problem(NULL, "Unexpected file in get_reg()");
 200             return brw_null_reg();
 201     }
 202
 203     assert(index < 256);
 204     assert(component < 4);
 205
 206     /* see if we've already allocated a HW register for this Mesa register */
 207     if (c->wm_regs[file][index][component].inited) {
 208        /* yes, re-use */
 209        reg = c->wm_regs[file][index][component].reg;
 210     }
 211     else {
 212         /* no, allocate new register */
 213        int grf = alloc_grf(c);
 214        /*printf("alloc grf %d for reg %d:%d.%d\n", grf, file, index, component);*/
 215        if (grf < 0) {
 216           /* totally out of temps */
 217           grf = 51; /* XXX random register! */
 218        }
 219
 220        reg = brw_vec8_grf(grf, 0);
 221        /*printf("Alloc new grf %d for %d.%d\n", reg.nr, index, component);*/
 222
 223        set_reg(c, file, index, component, reg);
 224     }
 225
 226     if (neg & (1 << component)) {
 227         reg = negate(reg);
 228     }
 229     if (abs)
 230         reg = brw_abs(reg);
 231     return reg;
 232 }
 233
 234
 235
 236 /**
 237  * This is called if we run out of GRF registers.  Examine the live intervals
 238  * of temp regs in the program and free those which won't be used again.
 239  */
 240 static void
 241 reclaim_temps(struct brw_wm_compile *c)
 242 {
 243    GLint intBegin[MAX_PROGRAM_TEMPS];
 244    GLint intEnd[MAX_PROGRAM_TEMPS];
 245    int index;
 246
 247    /*printf("Reclaim temps:\n");*/
 248
 249    _mesa_find_temp_intervals(c->prog_instructions, c->nr_fp_insns,
 250                              intBegin, intEnd);
 251
 252    for (index = 0; index < MAX_PROGRAM_TEMPS; index++) {
 253       if (intEnd[index] != -1 && intEnd[index] < c->cur_inst) {
 254          /* program temp[i] can be freed */
 255          int component;
 256          /*printf("  temp[%d] is dead\n", index);*/
 257          for (component = 0; component < 4; component++) {
 258             if (c->wm_regs[PROGRAM_TEMPORARY][index][component].inited) {
 259                int r = c->wm_regs[PROGRAM_TEMPORARY][index][component].reg.nr;
 260                release_grf(c, r);
 261                /*
 262                printf("  Reclaim temp %d, reg %d at inst %d\n",
 263                       index, r, c->cur_inst);
 264                */
 265                c->wm_regs[PROGRAM_TEMPORARY][index][component].inited = GL_FALSE;
 266             }
 267          }
 268       }
 269    }
 270 }
 271
 272
 273
 274
 275 /**
 276  * Preallocate registers.  This sets up the Mesa to hardware register
 277  * mapping for certain registers, such as constants (uniforms/state vars)
 278  * and shader inputs.
 279  */
 280 static void prealloc_reg(struct brw_wm_compile *c)
 281 {
 282     struct intel_context *intel = &c->func.brw->intel;
 283     int i, j;
 284     struct brw_reg reg;
 285     int urb_read_length = 0;
 286     GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted;
 287     GLuint reg_index = 0;
 288
 289     memset(c->used_grf, GL_FALSE, sizeof(c->used_grf));
 290     c->first_free_grf = 0;
 291
 292     for (i = 0; i < 4; i++) {
 293         if (i < (c->key.nr_payload_regs + 1) / 2)
 294             reg = brw_vec8_grf(i * 2, 0);
 295         else
 296             reg = brw_vec8_grf(0, 0);
 297         set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, i, reg);
 298     }
 299     set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_W, 0,
 300             brw_vec8_grf(c->key.source_w_reg, 0));
 301     reg_index += c->key.nr_payload_regs;
 302
 303     /* constants */
 304     {
 305         const GLuint nr_params = c->fp->program.Base.Parameters->NumParameters;
 306         const GLuint nr_temps = c->fp->program.Base.NumTemporaries;
 307
 308         /* use a real constant buffer, or just use a section of the GRF? */
 309         /* XXX this heuristic may need adjustment... */
 310         if ((nr_params + nr_temps) * 4 + reg_index > 80)
 311            c->fp->use_const_buffer = GL_TRUE;
 312         else
 313            c->fp->use_const_buffer = GL_FALSE;
 314         /*printf("WM use_const_buffer = %d\n", c->fp->use_const_buffer);*/
 315
 316         if (c->fp->use_const_buffer) {
 317            /* We'll use a real constant buffer and fetch constants from
 318             * it with a dataport read message.
 319             */
 320
 321            /* number of float constants in CURBE */
 322            c->prog_data.nr_params = 0;
 323         }
 324         else {
 325            const struct gl_program_parameter_list *plist =
 326               c->fp->program.Base.Parameters;
 327            int index = 0;
 328
 329            /* number of float constants in CURBE */
 330            c->prog_data.nr_params = 4 * nr_params;
 331
 332            /* loop over program constants (float[4]) */
 333            for (i = 0; i < nr_params; i++) {
 334               /* loop over XYZW channels */
 335               for (j = 0; j < 4; j++, index++) {
 336                  reg = brw_vec1_grf(reg_index + index / 8, index % 8);
 337                  /* Save pointer to parameter/constant value.
 338                   * Constants will be copied in prepare_constant_buffer()
 339                   */
 340                  c->prog_data.param[index] = &plist->ParameterValues[i][j];
 341                  set_reg(c, PROGRAM_STATE_VAR, i, j, reg);
 342               }
 343            }
 344            /* number of constant regs used (each reg is float[8]) */
 345            c->nr_creg = ALIGN(nr_params, 2) / 2;
 346            reg_index += c->nr_creg;
 347         }
 348     }
 349
 350     /* fragment shader inputs: One 2-reg pair of interpolation
 351      * coefficients for each vec4 to be set up.
 352      */
 353     if (intel->gen >= 6) {
 354        for (i = 0; i < FRAG_ATTRIB_MAX; i++) {
 355           if (!(c->fp->program.Base.InputsRead & BITFIELD64_BIT(i)))
 356              continue;
 357
 358           reg = brw_vec8_grf(reg_index, 0);
 359           for (j = 0; j < 4; j++) {
 360              set_reg(c, PROGRAM_PAYLOAD, i, j, reg);
 361           }
 362           reg_index += 2;
 363        }
 364        urb_read_length = reg_index;
 365     } else {
 366        for (i = 0; i < VERT_RESULT_MAX; i++) {
 367           int fp_input;
 368
 369           if (i >= VERT_RESULT_VAR0)
 370              fp_input = i - VERT_RESULT_VAR0 + FRAG_ATTRIB_VAR0;
 371           else if (i <= VERT_RESULT_TEX7)
 372              fp_input = i;
 373           else
 374              fp_input = -1;
 375
 376           if (fp_input >= 0 && inputs & (1 << fp_input)) {
 377              urb_read_length = reg_index;
 378              reg = brw_vec8_grf(reg_index, 0);
 379              for (j = 0; j < 4; j++)
 380                 set_reg(c, PROGRAM_PAYLOAD, fp_input, j, reg);
 381           }
 382           if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
 383              reg_index += 2;
 384           }
 385        }
 386     }
 387
 388     c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
 389     c->prog_data.urb_read_length = urb_read_length;
 390     c->prog_data.curb_read_length = c->nr_creg;
 391     c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, reg_index, 0);
 392     reg_index++;
 393     c->stack =  brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, reg_index, 0);
 394     reg_index += 2;
 395
 396     /* mark GRF regs [0..reg_index-1] as in-use */
 397     for (i = 0; i < reg_index; i++)
 398        prealloc_grf(c, i);
 399
 400     /* Don't use GRF 126, 127.  Using them seems to lead to GPU lock-ups */
 401     prealloc_grf(c, 126);
 402     prealloc_grf(c, 127);
 403
 404     for (i = 0; i < c->nr_fp_insns; i++) {
 405         const struct prog_instruction *inst = &c->prog_instructions[i];
 406         struct brw_reg dst[4];
 407
 408         switch (inst->Opcode) {
 409         case OPCODE_TEX:
 410         case OPCODE_TXB:
 411             /* Allocate the channels of texture results contiguously,
 412              * since they are written out that way by the sampler unit.
 413              */
 414             for (j = 0; j < 4; j++) {
 415                 dst[j] = get_dst_reg(c, inst, j);
 416                 if (j != 0)
 417                     assert(dst[j].nr == dst[j - 1].nr + 1);
 418             }
 419             break;
 420         default:
 421             break;
 422         }
 423     }
 424
 425     for (i = 0; i < c->nr_fp_insns; i++) {
 426         const struct prog_instruction *inst = &c->prog_instructions[i];
 427
 428         switch (inst->Opcode) {
 429         case WM_DELTAXY:
 430             /* Allocate WM_DELTAXY destination on G45/GM45 to an
 431              * even-numbered GRF if possible so that we can use the PLN
 432              * instruction.
 433              */
 434             if (inst->DstReg.WriteMask == WRITEMASK_XY &&
 435                 !c->wm_regs[inst->DstReg.File][inst->DstReg.Index][0].inited &&
 436                 !c->wm_regs[inst->DstReg.File][inst->DstReg.Index][1].inited &&
 437                 (IS_G4X(intel->intelScreen->deviceID) || intel->gen == 5)) {
 438                 int grf;
 439
 440                 for (grf = c->first_free_grf & ~1;
 441                      grf < BRW_WM_MAX_GRF;
 442                      grf += 2)
 443                 {
 444                     if (!c->used_grf[grf] && !c->used_grf[grf + 1]) {
 445                         c->used_grf[grf] = GL_TRUE;
 446                         c->used_grf[grf + 1] = GL_TRUE;
 447                         c->first_free_grf = grf + 2;  /* a guess */
 448
 449                         set_reg(c, inst->DstReg.File, inst->DstReg.Index, 0,
 450                                 brw_vec8_grf(grf, 0));
 451                         set_reg(c, inst->DstReg.File, inst->DstReg.Index, 1,
 452                                 brw_vec8_grf(grf + 1, 0));
 453                         break;
 454                     }
 455                 }
 456             }
 457         default:
 458             break;
 459         }
 460     }
 461
 462     /* An instruction may reference up to three constants.
 463      * They'll be found in these registers.
 464      * XXX alloc these on demand!
 465      */
 466     if (c->fp->use_const_buffer) {
 467        for (i = 0; i < 3; i++) {
 468           c->current_const[i].index = -1;
 469           c->current_const[i].reg = brw_vec8_grf(alloc_grf(c), 0);
 470        }
 471     }
 472 #if 0
 473     printf("USE CONST BUFFER? %d\n", c->fp->use_const_buffer);
 474     printf("AFTER PRE_ALLOC, reg_index = %d\n", reg_index);
 475 #endif
 476 }
 477
 478
 479 /**
 480  * Check if any of the instruction's src registers are constants, uniforms,
 481  * or statevars.  If so, fetch any constants that we don't already have in
 482  * the three GRF slots.
 483  */
 484 static void fetch_constants(struct brw_wm_compile *c,
 485                             const struct prog_instruction *inst)
 486 {
 487    struct brw_compile *p = &c->func;
 488    GLuint i;
 489
 490    /* loop over instruction src regs */
 491    for (i = 0; i < 3; i++) {
 492       const struct prog_src_register *src = &inst->SrcReg[i];
 493       if (src->File == PROGRAM_STATE_VAR ||
 494           src->File == PROGRAM_CONSTANT ||
 495           src->File == PROGRAM_UNIFORM) {
 496          c->current_const[i].index = src->Index;
 497
 498 #if 0
 499          printf("  fetch const[%d] for arg %d into reg %d\n",
 500                 src->Index, i, c->current_const[i].reg.nr);
 501 #endif
 502
 503          /* need to fetch the constant now */
 504          brw_dp_READ_4(p,
 505                        c->current_const[i].reg,  /* writeback dest */
 506                        src->RelAddr,             /* relative indexing? */
 507                        16 * src->Index,          /* byte offset */
 508                        SURF_INDEX_FRAG_CONST_BUFFER/* binding table index */
 509                        );
 510       }
 511    }
 512 }
 513
 514
 515 /**
 516  * Convert Mesa dst register to brw register.
 517  */
 518 static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
 519                                   const struct prog_instruction *inst,
 520                                   GLuint component)
 521 {
 522     const int nr = 1;
 523     return get_reg(c, inst->DstReg.File, inst->DstReg.Index, component, nr,
 524             0, 0);
 525 }
 526
 527
 528 static struct brw_reg
 529 get_src_reg_const(struct brw_wm_compile *c,
 530                   const struct prog_instruction *inst,
 531                   GLuint srcRegIndex, GLuint component)
 532 {
 533    /* We should have already fetched the constant from the constant
 534     * buffer in fetch_constants().  Now we just have to return a
 535     * register description that extracts the needed component and
 536     * smears it across all eight vector components.
 537     */
 538    const struct prog_src_register *src = &inst->SrcReg[srcRegIndex];
 539    struct brw_reg const_reg;
 540
 541    assert(component < 4);
 542    assert(srcRegIndex < 3);
 543    assert(c->current_const[srcRegIndex].index != -1);
 544    const_reg = c->current_const[srcRegIndex].reg;
 545
 546    /* extract desired float from the const_reg, and smear */
 547    const_reg = stride(const_reg, 0, 1, 0);
 548    const_reg.subnr = component * 4;
 549
 550    if (src->Negate & (1 << component))
 551       const_reg = negate(const_reg);
 552    if (src->Abs)
 553       const_reg = brw_abs(const_reg);
 554
 555 #if 0
 556    printf("  form const[%d].%d for arg %d, reg %d\n",
 557           c->current_const[srcRegIndex].index,
 558           component,
 559           srcRegIndex,
 560           const_reg.nr);
 561 #endif
 562
 563    return const_reg;
 564 }
 565
 566
 567 /**
 568  * Convert Mesa src register to brw register.
 569  */
 570 static struct brw_reg get_src_reg(struct brw_wm_compile *c,
 571                                   const struct prog_instruction *inst,
 572                                   GLuint srcRegIndex, GLuint channel)
 573 {
 574     const struct prog_src_register *src = &inst->SrcReg[srcRegIndex];
 575     const GLuint nr = 1;
 576     const GLuint component = GET_SWZ(src->Swizzle, channel);
 577
 578     /* Only one immediate value can be used per native opcode, and it
 579      * has be in the src1 slot, so not all Mesa instructions will get
 580      * to take advantage of immediate constants.
 581      */
 582     if (brw_wm_arg_can_be_immediate(inst->Opcode, srcRegIndex)) {
 583        const struct gl_program_parameter_list *params;
 584
 585        params = c->fp->program.Base.Parameters;
 586
 587        /* Extended swizzle terms */
 588        if (component == SWIZZLE_ZERO) {
 589           return brw_imm_f(0.0F);
 590        } else if (component == SWIZZLE_ONE) {
 591           if (src->Negate)
 592              return brw_imm_f(-1.0F);
 593           else
 594              return brw_imm_f(1.0F);
 595        }
 596
 597        if (src->File == PROGRAM_CONSTANT) {
 598           float f = params->ParameterValues[src->Index][component];
 599
 600           if (src->Abs)
 601              f = fabs(f);
 602           if (src->Negate)
 603              f = -f;
 604
 605           return brw_imm_f(f);
 606        }
 607     }
 608
 609     if (c->fp->use_const_buffer &&
 610         (src->File == PROGRAM_STATE_VAR ||
 611          src->File == PROGRAM_CONSTANT ||
 612          src->File == PROGRAM_UNIFORM)) {
 613        return get_src_reg_const(c, inst, srcRegIndex, component);
 614     }
 615     else {
 616        /* other type of source register */
 617        return get_reg(c, src->File, src->Index, component, nr,
 618                       src->Negate, src->Abs);
 619     }
 620 }
 621
 622 static void emit_arl(struct brw_wm_compile *c,
 623                      const struct prog_instruction *inst)
 624 {
 625     struct brw_compile *p = &c->func;
 626     struct brw_reg src0, addr_reg;
 627     brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 628     addr_reg = brw_uw8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 629                            BRW_ARF_ADDRESS, 0);
 630     src0 = get_src_reg(c, inst, 0, 0); /* channel 0 */
 631     brw_MOV(p, addr_reg, src0);
 632     brw_set_saturate(p, 0);
 633 }
 634
 635 static INLINE struct brw_reg high_words( struct brw_reg reg )
 636 {
 637     return stride( suboffset( retype( reg, BRW_REGISTER_TYPE_W ), 1 ),
 638                    0, 8, 2 );
 639 }
 640
 641 static INLINE struct brw_reg low_words( struct brw_reg reg )
 642 {
 643     return stride( retype( reg, BRW_REGISTER_TYPE_W ), 0, 8, 2 );
 644 }
 645
 646 static INLINE struct brw_reg even_bytes( struct brw_reg reg )
 647 {
 648     return stride( retype( reg, BRW_REGISTER_TYPE_B ), 0, 16, 2 );
 649 }
 650
 651 static INLINE struct brw_reg odd_bytes( struct brw_reg reg )
 652 {
 653     return stride( suboffset( retype( reg, BRW_REGISTER_TYPE_B ), 1 ),
 654                    0, 16, 2 );
 655 }
 656
 657 /**
 658  * Resolve subroutine calls after code emit is done.
 659  */
 660 static void post_wm_emit( struct brw_wm_compile *c )
 661 {
 662     brw_resolve_cals(&c->func);
 663 }
 664
 665 static void
 666 get_argument_regs(struct brw_wm_compile *c,
 667                   const struct prog_instruction *inst,
 668                   int index,
 669                   struct brw_reg *dst,
 670                   struct brw_reg *regs,
 671                   int mask)
 672 {
 673     struct brw_compile *p = &c->func;
 674     int i, j;
 675
 676     for (i = 0; i < 4; i++) {
 677         if (mask & (1 << i)) {
 678             regs[i] = get_src_reg(c, inst, index, i);
 679
 680             /* Unalias destination registers from our sources. */
 681             if (regs[i].file == BRW_GENERAL_REGISTER_FILE) {
 682                for (j = 0; j < 4; j++) {
 683                    if (memcmp(&regs[i], &dst[j], sizeof(regs[0])) == 0) {
 684                        struct brw_reg tmp = alloc_tmp(c);
 685                        brw_MOV(p, tmp, regs[i]);
 686                        regs[i] = tmp;
 687                        break;
 688                    }
 689                }
 690             }
 691         }
 692     }
 693 }
 694
 695 static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 696 {
 697    struct intel_context *intel = &brw->intel;
 698 #define MAX_IF_DEPTH 32
 699 #define MAX_LOOP_DEPTH 32
 700     struct brw_instruction *if_inst[MAX_IF_DEPTH], *loop_inst[MAX_LOOP_DEPTH];
 701     int if_depth_in_loop[MAX_LOOP_DEPTH];
 702     GLuint i, if_depth = 0, loop_depth = 0;
 703     struct brw_compile *p = &c->func;
 704     struct brw_indirect stack_index = brw_indirect(0, 0);
 705
 706     c->out_of_regs = GL_FALSE;
 707
 708     if_depth_in_loop[loop_depth] = 0;
 709
 710     prealloc_reg(c);
 711     brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 712     brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
 713
 714     if (intel->gen >= 6)
 715         brw_set_acc_write_control(p, 1);
 716
 717     for (i = 0; i < c->nr_fp_insns; i++) {
 718         const struct prog_instruction *inst = &c->prog_instructions[i];
 719         int dst_flags;
 720         struct brw_reg args[3][4], dst[4];
 721         int j;
 722         int mark = mark_tmps( c );
 723
 724         c->cur_inst = i;
 725
 726 #if 0
 727         printf("Inst %d: ", i);
 728         _mesa_print_instruction(inst);
 729 #endif
 730
 731         /* fetch any constants that this instruction needs */
 732         if (c->fp->use_const_buffer)
 733            fetch_constants(c, inst);
 734
 735         if (inst->Opcode != OPCODE_ARL) {
 736            for (j = 0; j < 4; j++) {
 737               if (inst->DstReg.WriteMask & (1 << j))
 738                  dst[j] = get_dst_reg(c, inst, j);
 739               else
 740                  dst[j] = brw_null_reg();
 741            }
 742         }
 743         for (j = 0; j < brw_wm_nr_args(inst->Opcode); j++)
 744             get_argument_regs(c, inst, j, dst, args[j], WRITEMASK_XYZW);
 745
 746         dst_flags = inst->DstReg.WriteMask;
 747         if (inst->SaturateMode == SATURATE_ZERO_ONE)
 748             dst_flags |= SATURATE;
 749
 750         if (inst->CondUpdate)
 751             brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 752         else
 753             brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE);
 754
 755         switch (inst->Opcode) {
 756             case WM_PIXELXY:
 757                 emit_pixel_xy(c, dst, dst_flags);
 758                 break;
 759             case WM_DELTAXY:
 760                 emit_delta_xy(p, dst, dst_flags, args[0]);
 761                 break;
 762             case WM_PIXELW:
 763                 emit_pixel_w(c, dst, dst_flags, args[0], args[1]);
 764                 break;
 765             case WM_LINTERP:
 766                 emit_linterp(p, dst, dst_flags, args[0], args[1]);
 767                 break;
 768             case WM_PINTERP:
 769                 emit_pinterp(p, dst, dst_flags, args[0], args[1], args[2]);
 770                 break;
 771             case WM_CINTERP:
 772                 emit_cinterp(p, dst, dst_flags, args[0]);
 773                 break;
 774             case WM_WPOSXY:
 775                 emit_wpos_xy(c, dst, dst_flags, args[0]);
 776                 break;
 777             case WM_FB_WRITE:
 778                 emit_fb_write(c, args[0], args[1], args[2],
 779                               INST_AUX_GET_TARGET(inst->Aux),
 780                               inst->Aux & INST_AUX_EOT);
 781                 break;
 782             case WM_FRONTFACING:
 783                 emit_frontfacing(p, dst, dst_flags);
 784                 break;
 785             case OPCODE_ADD:
 786                 emit_alu2(p, brw_ADD, dst, dst_flags, args[0], args[1]);
 787                 break;
 788             case OPCODE_ARL:
 789                 emit_arl(c, inst);
 790                 break;
 791             case OPCODE_FRC:
 792                 emit_alu1(p, brw_FRC, dst, dst_flags, args[0]);
 793                 break;
 794             case OPCODE_FLR:
 795                 emit_alu1(p, brw_RNDD, dst, dst_flags, args[0]);
 796                 break;
 797             case OPCODE_LRP:
 798                 emit_lrp(p, dst, dst_flags, args[0], args[1], args[2]);
 799                 break;
 800             case OPCODE_TRUNC:
 801                 emit_alu1(p, brw_RNDZ, dst, dst_flags, args[0]);
 802                 break;
 803             case OPCODE_MOV:
 804             case OPCODE_SWZ:
 805                 emit_alu1(p, brw_MOV, dst, dst_flags, args[0]);
 806                 break;
 807             case OPCODE_DP2:
 808                 emit_dp2(p, dst, dst_flags, args[0], args[1]);
 809                 break;
 810             case OPCODE_DP3:
 811                 emit_dp3(p, dst, dst_flags, args[0], args[1]);
 812                 break;
 813             case OPCODE_DP4:
 814                 emit_dp4(p, dst, dst_flags, args[0], args[1]);
 815                 break;
 816             case OPCODE_XPD:
 817                 emit_xpd(p, dst, dst_flags, args[0], args[1]);
 818                 break;
 819             case OPCODE_DPH:
 820                 emit_dph(p, dst, dst_flags, args[0], args[1]);
 821                 break;
 822             case OPCODE_RCP:
 823                 emit_math1(c, BRW_MATH_FUNCTION_INV, dst, dst_flags, args[0]);
 824                 break;
 825             case OPCODE_RSQ:
 826                 emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, dst_flags, args[0]);
 827                 break;
 828             case OPCODE_SIN:
 829                 emit_math1(c, BRW_MATH_FUNCTION_SIN, dst, dst_flags, args[0]);
 830                 break;
 831             case OPCODE_COS:
 832                 emit_math1(c, BRW_MATH_FUNCTION_COS, dst, dst_flags, args[0]);
 833                 break;
 834             case OPCODE_EX2:
 835                 emit_math1(c, BRW_MATH_FUNCTION_EXP, dst, dst_flags, args[0]);
 836                 break;
 837             case OPCODE_LG2:
 838                 emit_math1(c, BRW_MATH_FUNCTION_LOG, dst, dst_flags, args[0]);
 839                 break;
 840             case OPCODE_CMP:
 841                 emit_cmp(p, dst, dst_flags, args[0], args[1], args[2]);
 842                 break;
 843             case OPCODE_MIN:
 844                 emit_min(p, dst, dst_flags, args[0], args[1]);
 845                 break;
 846             case OPCODE_MAX:
 847                 emit_max(p, dst, dst_flags, args[0], args[1]);
 848                 break;
 849             case OPCODE_DDX:
 850             case OPCODE_DDY:
 851                 emit_ddxy(p, dst, dst_flags, (inst->Opcode == OPCODE_DDX),
 852                           args[0]);
 853                 break;
 854             case OPCODE_SLT:
 855                 emit_sop(p, dst, dst_flags,
 856                          BRW_CONDITIONAL_L, args[0], args[1]);
 857                 break;
 858             case OPCODE_SLE:
 859                 emit_sop(p, dst, dst_flags,
 860                          BRW_CONDITIONAL_LE, args[0], args[1]);
 861                 break;
 862             case OPCODE_SGT:
 863                 emit_sop(p, dst, dst_flags,
 864                          BRW_CONDITIONAL_G, args[0], args[1]);
 865                 break;
 866             case OPCODE_SGE:
 867                 emit_sop(p, dst, dst_flags,
 868                          BRW_CONDITIONAL_GE, args[0], args[1]);
 869                 break;
 870             case OPCODE_SEQ:
 871                 emit_sop(p, dst, dst_flags,
 872                          BRW_CONDITIONAL_EQ, args[0], args[1]);
 873                 break;
 874             case OPCODE_SNE:
 875                 emit_sop(p, dst, dst_flags,
 876                          BRW_CONDITIONAL_NEQ, args[0], args[1]);
 877                 break;
 878             case OPCODE_SSG:
 879                 emit_sign(p, dst, dst_flags, args[0]);
 880                 break;
 881             case OPCODE_MUL:
 882                 emit_alu2(p, brw_MUL, dst, dst_flags, args[0], args[1]);
 883                 break;
 884             case OPCODE_POW:
 885                 emit_math2(c, BRW_MATH_FUNCTION_POW,
 886                            dst, dst_flags, args[0], args[1]);
 887                 break;
 888             case OPCODE_MAD:
 889                 emit_mad(p, dst, dst_flags, args[0], args[1], args[2]);
 890                 break;
 891             case OPCODE_TEX:
 892                 emit_tex(c, dst, dst_flags, args[0],
 893                          get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH,
 894                                  0, 1, 0, 0),
 895                          inst->TexSrcTarget,
 896                          inst->TexSrcUnit,
 897                          (c->key.shadowtex_mask & (1 << inst->TexSrcUnit)) != 0);
 898                 break;
 899             case OPCODE_TXB:
 900                 emit_txb(c, dst, dst_flags, args[0],
 901                          get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH,
 902                                  0, 1, 0, 0),
 903                          inst->TexSrcTarget,
 904                          c->fp->program.Base.SamplerUnits[inst->TexSrcUnit]);
 905                 break;
 906             case OPCODE_KIL_NV:
 907                 emit_kil_nv(c);
 908                 break;
 909             case OPCODE_IF:
 910                 assert(if_depth < MAX_IF_DEPTH);
 911                 if_inst[if_depth++] = brw_IF(p, BRW_EXECUTE_8);
 912                 if_depth_in_loop[loop_depth]++;
 913                 break;
 914             case OPCODE_ELSE:
 915                 assert(if_depth > 0);
 916                 if_inst[if_depth-1]  = brw_ELSE(p, if_inst[if_depth-1]);
 917                 break;
 918             case OPCODE_ENDIF:
 919                 assert(if_depth > 0);
 920                 brw_ENDIF(p, if_inst[--if_depth]);
 921                 if_depth_in_loop[loop_depth]--;
 922                 break;
 923             case OPCODE_BGNSUB:
 924                 brw_save_label(p, inst->Comment, p->nr_insn);
 925                 break;
 926             case OPCODE_ENDSUB:
 927                 /* no-op */
 928                 break;
 929             case OPCODE_CAL:
 930                 brw_push_insn_state(p);
 931                 brw_set_mask_control(p, BRW_MASK_DISABLE);
 932                 brw_set_access_mode(p, BRW_ALIGN_1);
 933                 brw_ADD(p, deref_1ud(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
 934                 brw_set_access_mode(p, BRW_ALIGN_16);
 935                 brw_ADD(p, get_addr_reg(stack_index),
 936                          get_addr_reg(stack_index), brw_imm_d(4));
 937                 brw_save_call(&c->func, inst->Comment, p->nr_insn);
 938                 brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
 939                 brw_pop_insn_state(p);
 940                 break;
 941
 942             case OPCODE_RET:
 943                 brw_push_insn_state(p);
 944                 brw_set_mask_control(p, BRW_MASK_DISABLE);
 945                 brw_ADD(p, get_addr_reg(stack_index),
 946                         get_addr_reg(stack_index), brw_imm_d(-4));
 947                 brw_set_access_mode(p, BRW_ALIGN_1);
 948                 brw_MOV(p, brw_ip_reg(), deref_1ud(stack_index, 0));
 949                 brw_set_access_mode(p, BRW_ALIGN_16);
 950                 brw_pop_insn_state(p);
 951
 952                 break;
 953             case OPCODE_BGNLOOP:
 954                 /* XXX may need to invalidate the current_constant regs */
 955                 loop_inst[loop_depth++] = brw_DO(p, BRW_EXECUTE_8);
 956                 if_depth_in_loop[loop_depth] = 0;
 957                 break;
 958             case OPCODE_BRK:
 959                 brw_BREAK(p, if_depth_in_loop[loop_depth]);
 960                 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 961                 break;
 962             case OPCODE_CONT:
 963                 brw_CONT(p, if_depth_in_loop[loop_depth]);
 964                 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 965                 break;
 966             case OPCODE_ENDLOOP:
 967                {
 968                   struct brw_instruction *inst0, *inst1;
 969                   GLuint br = 1;
 970
 971                   if (intel->gen == 5)
 972                      br = 2;
 973
 974                   assert(loop_depth > 0);
 975                   loop_depth--;
 976                   inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]);
 977                   /* patch all the BREAK/CONT instructions from last BGNLOOP */
 978                   while (inst0 > loop_inst[loop_depth]) {
 979                      inst0--;
 980                      if (inst0->header.opcode == BRW_OPCODE_BREAK &&
 981                          inst0->bits3.if_else.jump_count == 0) {
 982                         inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
 983                      }
 984                      else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
 985                               inst0->bits3.if_else.jump_count == 0) {
 986                         inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
 987                      }
 988                   }
 989                }
 990                break;
 991             default:
 992                 printf("unsupported opcode %d (%s) in fragment shader\n",
 993                        inst->Opcode, inst->Opcode < MAX_OPCODE ?
 994                        _mesa_opcode_string(inst->Opcode) : "unknown");
 995         }
 996
 997         /* Release temporaries containing any unaliased source regs. */
 998         release_tmps( c, mark );
 999
1000         if (inst->CondUpdate)
1001             brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
1002         else
1003             brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1004     }
1005     post_wm_emit(c);
1006
1007     if (INTEL_DEBUG & DEBUG_WM) {
1008       printf("wm-native:\n");
1009       for (i = 0; i < p->nr_insn; i++)
1010          brw_disasm(stdout, &p->store[i], intel->gen);
1011       printf("\n");
1012     }
1013 }
1014
1015 /**
1016  * Do GPU code generation for shaders that use GLSL features such as
1017  * flow control.  Other shaders will be compiled with the
1018  */
1019 void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
1020 {
1021     if (INTEL_DEBUG & DEBUG_WM) {
1022         printf("brw_wm_glsl_emit:\n");
1023     }
1024
1025     /* initial instruction translation/simplification */
1026     brw_wm_pass_fp(c);
1027
1028     /* actual code generation */
1029     brw_wm_emit_glsl(brw, c);
1030
1031     if (INTEL_DEBUG & DEBUG_WM) {
1032         brw_wm_print_program(c, "brw_wm_glsl_emit done");
1033     }
1034
1035     c->prog_data.total_grf = num_grf_used(c);
1036     c->prog_data.total_scratch = 0;
1037 }