1 #include "main/macros.h"
2 #include "program/prog_parameter.h"
3 #include "program/prog_print.h"
4 #include "program/prog_optimize.h"
5 #include "brw_context.h"
9 static struct brw_reg
get_dst_reg(struct brw_wm_compile
*c
,
10 const struct prog_instruction
*inst
,
14 * Determine if the given fragment program uses GLSL features such
15 * as flow conditionals, loops, subroutines.
16 * Some GLSL shaders may use these features, others might not.
18 GLboolean
brw_wm_is_glsl(const struct gl_fragment_program
*fp
)
22 if (INTEL_DEBUG
& DEBUG_GLSL_FORCE
)
25 for (i
= 0; i
< fp
->Base
.NumInstructions
; i
++) {
26 const struct prog_instruction
*inst
= &fp
->Base
.Instructions
[i
];
27 switch (inst
->Opcode
) {
46 reclaim_temps(struct brw_wm_compile
*c
);
49 /** Mark GRF register as used. */
51 prealloc_grf(struct brw_wm_compile
*c
, int r
)
53 c
->used_grf
[r
] = GL_TRUE
;
57 /** Mark given GRF register as not in use. */
59 release_grf(struct brw_wm_compile
*c
, int r
)
61 /*assert(c->used_grf[r]);*/
62 c
->used_grf
[r
] = GL_FALSE
;
63 c
->first_free_grf
= MIN2(c
->first_free_grf
, r
);
67 /** Return index of a free GRF, mark it as used. */
69 alloc_grf(struct brw_wm_compile
*c
)
72 for (r
= c
->first_free_grf
; r
< BRW_WM_MAX_GRF
; r
++) {
73 if (!c
->used_grf
[r
]) {
74 c
->used_grf
[r
] = GL_TRUE
;
75 c
->first_free_grf
= r
+ 1; /* a guess */
80 /* no free temps, try to reclaim some */
82 c
->first_free_grf
= 0;
85 for (r
= c
->first_free_grf
; r
< BRW_WM_MAX_GRF
; r
++) {
86 if (!c
->used_grf
[r
]) {
87 c
->used_grf
[r
] = GL_TRUE
;
88 c
->first_free_grf
= r
+ 1; /* a guess */
93 for (r
= 0; r
< BRW_WM_MAX_GRF
; r
++) {
94 assert(c
->used_grf
[r
]);
97 /* really, no free GRF regs found */
98 if (!c
->out_of_regs
) {
99 /* print warning once per compilation */
100 _mesa_warning(NULL
, "i965: ran out of registers for fragment program");
101 c
->out_of_regs
= GL_TRUE
;
108 /** Return number of GRF registers used */
110 num_grf_used(const struct brw_wm_compile
*c
)
113 for (r
= BRW_WM_MAX_GRF
- 1; r
>= 0; r
--)
122 * Record the mapping of a Mesa register to a hardware register.
124 static void set_reg(struct brw_wm_compile
*c
, int file
, int index
,
125 int component
, struct brw_reg reg
)
127 c
->wm_regs
[file
][index
][component
].reg
= reg
;
128 c
->wm_regs
[file
][index
][component
].inited
= GL_TRUE
;
131 static struct brw_reg
alloc_tmp(struct brw_wm_compile
*c
)
135 /* if we need to allocate another temp, grow the tmp_regs[] array */
136 if (c
->tmp_index
== c
->tmp_max
) {
137 int r
= alloc_grf(c
);
139 /*printf("Out of temps in %s\n", __FUNCTION__);*/
140 r
= 50; /* XXX random register! */
142 c
->tmp_regs
[ c
->tmp_max
++ ] = r
;
145 /* form the GRF register */
146 reg
= brw_vec8_grf(c
->tmp_regs
[ c
->tmp_index
++ ], 0);
147 /*printf("alloc_temp %d\n", reg.nr);*/
148 assert(reg
.nr
< BRW_WM_MAX_GRF
);
154 * Save current temp register info.
155 * There must be a matching call to release_tmps().
157 static int mark_tmps(struct brw_wm_compile
*c
)
162 static void release_tmps(struct brw_wm_compile
*c
, int mark
)
168 * Convert Mesa src register to brw register.
170 * Since we're running in SOA mode each Mesa register corresponds to four
171 * hardware registers. We allocate the hardware registers as needed here.
173 * \param file register file, one of PROGRAM_x
174 * \param index register number
175 * \param component src component (X=0, Y=1, Z=2, W=3)
176 * \param nr not used?!?
177 * \param neg negate value?
178 * \param abs take absolute value?
180 static struct brw_reg
181 get_reg(struct brw_wm_compile
*c
, int file
, int index
, int component
,
182 int nr
, GLuint neg
, GLuint abs
)
186 case PROGRAM_STATE_VAR
:
187 case PROGRAM_CONSTANT
:
188 case PROGRAM_UNIFORM
:
189 file
= PROGRAM_STATE_VAR
;
191 case PROGRAM_UNDEFINED
:
192 return brw_null_reg();
193 case PROGRAM_TEMPORARY
:
196 case PROGRAM_PAYLOAD
:
199 _mesa_problem(NULL
, "Unexpected file in get_reg()");
200 return brw_null_reg();
204 assert(component
< 4);
206 /* see if we've already allocated a HW register for this Mesa register */
207 if (c
->wm_regs
[file
][index
][component
].inited
) {
209 reg
= c
->wm_regs
[file
][index
][component
].reg
;
212 /* no, allocate new register */
213 int grf
= alloc_grf(c
);
214 /*printf("alloc grf %d for reg %d:%d.%d\n", grf, file, index, component);*/
216 /* totally out of temps */
217 grf
= 51; /* XXX random register! */
220 reg
= brw_vec8_grf(grf
, 0);
221 /*printf("Alloc new grf %d for %d.%d\n", reg.nr, index, component);*/
223 set_reg(c
, file
, index
, component
, reg
);
226 if (neg
& (1 << component
)) {
237 * This is called if we run out of GRF registers. Examine the live intervals
238 * of temp regs in the program and free those which won't be used again.
241 reclaim_temps(struct brw_wm_compile
*c
)
243 GLint intBegin
[MAX_PROGRAM_TEMPS
];
244 GLint intEnd
[MAX_PROGRAM_TEMPS
];
247 /*printf("Reclaim temps:\n");*/
249 _mesa_find_temp_intervals(c
->prog_instructions
, c
->nr_fp_insns
,
252 for (index
= 0; index
< MAX_PROGRAM_TEMPS
; index
++) {
253 if (intEnd
[index
] != -1 && intEnd
[index
] < c
->cur_inst
) {
254 /* program temp[i] can be freed */
256 /*printf(" temp[%d] is dead\n", index);*/
257 for (component
= 0; component
< 4; component
++) {
258 if (c
->wm_regs
[PROGRAM_TEMPORARY
][index
][component
].inited
) {
259 int r
= c
->wm_regs
[PROGRAM_TEMPORARY
][index
][component
].reg
.nr
;
262 printf(" Reclaim temp %d, reg %d at inst %d\n",
263 index, r, c->cur_inst);
265 c
->wm_regs
[PROGRAM_TEMPORARY
][index
][component
].inited
= GL_FALSE
;
276 * Preallocate registers. This sets up the Mesa to hardware register
277 * mapping for certain registers, such as constants (uniforms/state vars)
280 static void prealloc_reg(struct brw_wm_compile
*c
)
282 struct intel_context
*intel
= &c
->func
.brw
->intel
;
285 int urb_read_length
= 0;
286 GLuint inputs
= FRAG_BIT_WPOS
| c
->fp_interp_emitted
;
287 GLuint reg_index
= 0;
289 memset(c
->used_grf
, GL_FALSE
, sizeof(c
->used_grf
));
290 c
->first_free_grf
= 0;
292 for (i
= 0; i
< 4; i
++) {
293 if (i
< (c
->key
.nr_payload_regs
+ 1) / 2)
294 reg
= brw_vec8_grf(i
* 2, 0);
296 reg
= brw_vec8_grf(0, 0);
297 set_reg(c
, PROGRAM_PAYLOAD
, PAYLOAD_DEPTH
, i
, reg
);
299 set_reg(c
, PROGRAM_PAYLOAD
, PAYLOAD_W
, 0,
300 brw_vec8_grf(c
->key
.source_w_reg
, 0));
301 reg_index
+= c
->key
.nr_payload_regs
;
305 const GLuint nr_params
= c
->fp
->program
.Base
.Parameters
->NumParameters
;
306 const GLuint nr_temps
= c
->fp
->program
.Base
.NumTemporaries
;
308 /* use a real constant buffer, or just use a section of the GRF? */
309 /* XXX this heuristic may need adjustment... */
310 if ((nr_params
+ nr_temps
) * 4 + reg_index
> 80)
311 c
->fp
->use_const_buffer
= GL_TRUE
;
313 c
->fp
->use_const_buffer
= GL_FALSE
;
314 /*printf("WM use_const_buffer = %d\n", c->fp->use_const_buffer);*/
316 if (c
->fp
->use_const_buffer
) {
317 /* We'll use a real constant buffer and fetch constants from
318 * it with a dataport read message.
321 /* number of float constants in CURBE */
322 c
->prog_data
.nr_params
= 0;
325 const struct gl_program_parameter_list
*plist
=
326 c
->fp
->program
.Base
.Parameters
;
329 /* number of float constants in CURBE */
330 c
->prog_data
.nr_params
= 4 * nr_params
;
332 /* loop over program constants (float[4]) */
333 for (i
= 0; i
< nr_params
; i
++) {
334 /* loop over XYZW channels */
335 for (j
= 0; j
< 4; j
++, index
++) {
336 reg
= brw_vec1_grf(reg_index
+ index
/ 8, index
% 8);
337 /* Save pointer to parameter/constant value.
338 * Constants will be copied in prepare_constant_buffer()
340 c
->prog_data
.param
[index
] = &plist
->ParameterValues
[i
][j
];
341 set_reg(c
, PROGRAM_STATE_VAR
, i
, j
, reg
);
344 /* number of constant regs used (each reg is float[8]) */
345 c
->nr_creg
= ALIGN(nr_params
, 2) / 2;
346 reg_index
+= c
->nr_creg
;
350 /* fragment shader inputs: One 2-reg pair of interpolation
351 * coefficients for each vec4 to be set up.
353 if (intel
->gen
>= 6) {
354 for (i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
355 if (!(c
->fp
->program
.Base
.InputsRead
& BITFIELD64_BIT(i
)))
358 reg
= brw_vec8_grf(reg_index
, 0);
359 for (j
= 0; j
< 4; j
++) {
360 set_reg(c
, PROGRAM_PAYLOAD
, i
, j
, reg
);
364 urb_read_length
= reg_index
;
366 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
369 if (i
>= VERT_RESULT_VAR0
)
370 fp_input
= i
- VERT_RESULT_VAR0
+ FRAG_ATTRIB_VAR0
;
371 else if (i
<= VERT_RESULT_TEX7
)
376 if (fp_input
>= 0 && inputs
& (1 << fp_input
)) {
377 urb_read_length
= reg_index
;
378 reg
= brw_vec8_grf(reg_index
, 0);
379 for (j
= 0; j
< 4; j
++)
380 set_reg(c
, PROGRAM_PAYLOAD
, fp_input
, j
, reg
);
382 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
388 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
389 c
->prog_data
.urb_read_length
= urb_read_length
;
390 c
->prog_data
.curb_read_length
= c
->nr_creg
;
391 c
->emit_mask_reg
= brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, reg_index
, 0);
393 c
->stack
= brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, reg_index
, 0);
396 /* mark GRF regs [0..reg_index-1] as in-use */
397 for (i
= 0; i
< reg_index
; i
++)
400 /* Don't use GRF 126, 127. Using them seems to lead to GPU lock-ups */
401 prealloc_grf(c
, 126);
402 prealloc_grf(c
, 127);
404 for (i
= 0; i
< c
->nr_fp_insns
; i
++) {
405 const struct prog_instruction
*inst
= &c
->prog_instructions
[i
];
406 struct brw_reg dst
[4];
408 switch (inst
->Opcode
) {
411 /* Allocate the channels of texture results contiguously,
412 * since they are written out that way by the sampler unit.
414 for (j
= 0; j
< 4; j
++) {
415 dst
[j
] = get_dst_reg(c
, inst
, j
);
417 assert(dst
[j
].nr
== dst
[j
- 1].nr
+ 1);
425 for (i
= 0; i
< c
->nr_fp_insns
; i
++) {
426 const struct prog_instruction
*inst
= &c
->prog_instructions
[i
];
428 switch (inst
->Opcode
) {
430 /* Allocate WM_DELTAXY destination on G45/GM45 to an
431 * even-numbered GRF if possible so that we can use the PLN
434 if (inst
->DstReg
.WriteMask
== WRITEMASK_XY
&&
435 !c
->wm_regs
[inst
->DstReg
.File
][inst
->DstReg
.Index
][0].inited
&&
436 !c
->wm_regs
[inst
->DstReg
.File
][inst
->DstReg
.Index
][1].inited
&&
437 (IS_G4X(intel
->intelScreen
->deviceID
) || intel
->gen
== 5)) {
440 for (grf
= c
->first_free_grf
& ~1;
441 grf
< BRW_WM_MAX_GRF
;
444 if (!c
->used_grf
[grf
] && !c
->used_grf
[grf
+ 1]) {
445 c
->used_grf
[grf
] = GL_TRUE
;
446 c
->used_grf
[grf
+ 1] = GL_TRUE
;
447 c
->first_free_grf
= grf
+ 2; /* a guess */
449 set_reg(c
, inst
->DstReg
.File
, inst
->DstReg
.Index
, 0,
450 brw_vec8_grf(grf
, 0));
451 set_reg(c
, inst
->DstReg
.File
, inst
->DstReg
.Index
, 1,
452 brw_vec8_grf(grf
+ 1, 0));
462 /* An instruction may reference up to three constants.
463 * They'll be found in these registers.
464 * XXX alloc these on demand!
466 if (c
->fp
->use_const_buffer
) {
467 for (i
= 0; i
< 3; i
++) {
468 c
->current_const
[i
].index
= -1;
469 c
->current_const
[i
].reg
= brw_vec8_grf(alloc_grf(c
), 0);
473 printf("USE CONST BUFFER? %d\n", c
->fp
->use_const_buffer
);
474 printf("AFTER PRE_ALLOC, reg_index = %d\n", reg_index
);
480 * Check if any of the instruction's src registers are constants, uniforms,
481 * or statevars. If so, fetch any constants that we don't already have in
482 * the three GRF slots.
484 static void fetch_constants(struct brw_wm_compile
*c
,
485 const struct prog_instruction
*inst
)
487 struct brw_compile
*p
= &c
->func
;
490 /* loop over instruction src regs */
491 for (i
= 0; i
< 3; i
++) {
492 const struct prog_src_register
*src
= &inst
->SrcReg
[i
];
493 if (src
->File
== PROGRAM_STATE_VAR
||
494 src
->File
== PROGRAM_CONSTANT
||
495 src
->File
== PROGRAM_UNIFORM
) {
496 c
->current_const
[i
].index
= src
->Index
;
499 printf(" fetch const[%d] for arg %d into reg %d\n",
500 src
->Index
, i
, c
->current_const
[i
].reg
.nr
);
503 /* need to fetch the constant now */
505 c
->current_const
[i
].reg
, /* writeback dest */
506 src
->RelAddr
, /* relative indexing? */
507 16 * src
->Index
, /* byte offset */
508 SURF_INDEX_FRAG_CONST_BUFFER
/* binding table index */
516 * Convert Mesa dst register to brw register.
518 static struct brw_reg
get_dst_reg(struct brw_wm_compile
*c
,
519 const struct prog_instruction
*inst
,
523 return get_reg(c
, inst
->DstReg
.File
, inst
->DstReg
.Index
, component
, nr
,
528 static struct brw_reg
529 get_src_reg_const(struct brw_wm_compile
*c
,
530 const struct prog_instruction
*inst
,
531 GLuint srcRegIndex
, GLuint component
)
533 /* We should have already fetched the constant from the constant
534 * buffer in fetch_constants(). Now we just have to return a
535 * register description that extracts the needed component and
536 * smears it across all eight vector components.
538 const struct prog_src_register
*src
= &inst
->SrcReg
[srcRegIndex
];
539 struct brw_reg const_reg
;
541 assert(component
< 4);
542 assert(srcRegIndex
< 3);
543 assert(c
->current_const
[srcRegIndex
].index
!= -1);
544 const_reg
= c
->current_const
[srcRegIndex
].reg
;
546 /* extract desired float from the const_reg, and smear */
547 const_reg
= stride(const_reg
, 0, 1, 0);
548 const_reg
.subnr
= component
* 4;
550 if (src
->Negate
& (1 << component
))
551 const_reg
= negate(const_reg
);
553 const_reg
= brw_abs(const_reg
);
556 printf(" form const[%d].%d for arg %d, reg %d\n",
557 c
->current_const
[srcRegIndex
].index
,
568 * Convert Mesa src register to brw register.
570 static struct brw_reg
get_src_reg(struct brw_wm_compile
*c
,
571 const struct prog_instruction
*inst
,
572 GLuint srcRegIndex
, GLuint channel
)
574 const struct prog_src_register
*src
= &inst
->SrcReg
[srcRegIndex
];
576 const GLuint component
= GET_SWZ(src
->Swizzle
, channel
);
578 /* Only one immediate value can be used per native opcode, and it
579 * has be in the src1 slot, so not all Mesa instructions will get
580 * to take advantage of immediate constants.
582 if (brw_wm_arg_can_be_immediate(inst
->Opcode
, srcRegIndex
)) {
583 const struct gl_program_parameter_list
*params
;
585 params
= c
->fp
->program
.Base
.Parameters
;
587 /* Extended swizzle terms */
588 if (component
== SWIZZLE_ZERO
) {
589 return brw_imm_f(0.0F
);
590 } else if (component
== SWIZZLE_ONE
) {
592 return brw_imm_f(-1.0F
);
594 return brw_imm_f(1.0F
);
597 if (src
->File
== PROGRAM_CONSTANT
) {
598 float f
= params
->ParameterValues
[src
->Index
][component
];
609 if (c
->fp
->use_const_buffer
&&
610 (src
->File
== PROGRAM_STATE_VAR
||
611 src
->File
== PROGRAM_CONSTANT
||
612 src
->File
== PROGRAM_UNIFORM
)) {
613 return get_src_reg_const(c
, inst
, srcRegIndex
, component
);
616 /* other type of source register */
617 return get_reg(c
, src
->File
, src
->Index
, component
, nr
,
618 src
->Negate
, src
->Abs
);
622 static void emit_arl(struct brw_wm_compile
*c
,
623 const struct prog_instruction
*inst
)
625 struct brw_compile
*p
= &c
->func
;
626 struct brw_reg src0
, addr_reg
;
627 brw_set_saturate(p
, (inst
->SaturateMode
!= SATURATE_OFF
) ? 1 : 0);
628 addr_reg
= brw_uw8_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
630 src0
= get_src_reg(c
, inst
, 0, 0); /* channel 0 */
631 brw_MOV(p
, addr_reg
, src0
);
632 brw_set_saturate(p
, 0);
635 static INLINE
struct brw_reg
high_words( struct brw_reg reg
)
637 return stride( suboffset( retype( reg
, BRW_REGISTER_TYPE_W
), 1 ),
641 static INLINE
struct brw_reg
low_words( struct brw_reg reg
)
643 return stride( retype( reg
, BRW_REGISTER_TYPE_W
), 0, 8, 2 );
646 static INLINE
struct brw_reg
even_bytes( struct brw_reg reg
)
648 return stride( retype( reg
, BRW_REGISTER_TYPE_B
), 0, 16, 2 );
651 static INLINE
struct brw_reg
odd_bytes( struct brw_reg reg
)
653 return stride( suboffset( retype( reg
, BRW_REGISTER_TYPE_B
), 1 ),
658 * Resolve subroutine calls after code emit is done.
660 static void post_wm_emit( struct brw_wm_compile
*c
)
662 brw_resolve_cals(&c
->func
);
666 get_argument_regs(struct brw_wm_compile
*c
,
667 const struct prog_instruction
*inst
,
670 struct brw_reg
*regs
,
673 struct brw_compile
*p
= &c
->func
;
676 for (i
= 0; i
< 4; i
++) {
677 if (mask
& (1 << i
)) {
678 regs
[i
] = get_src_reg(c
, inst
, index
, i
);
680 /* Unalias destination registers from our sources. */
681 if (regs
[i
].file
== BRW_GENERAL_REGISTER_FILE
) {
682 for (j
= 0; j
< 4; j
++) {
683 if (memcmp(®s
[i
], &dst
[j
], sizeof(regs
[0])) == 0) {
684 struct brw_reg tmp
= alloc_tmp(c
);
685 brw_MOV(p
, tmp
, regs
[i
]);
695 static void brw_wm_emit_glsl(struct brw_context
*brw
, struct brw_wm_compile
*c
)
697 struct intel_context
*intel
= &brw
->intel
;
698 #define MAX_IF_DEPTH 32
699 #define MAX_LOOP_DEPTH 32
700 struct brw_instruction
*if_inst
[MAX_IF_DEPTH
], *loop_inst
[MAX_LOOP_DEPTH
];
701 int if_depth_in_loop
[MAX_LOOP_DEPTH
];
702 GLuint i
, if_depth
= 0, loop_depth
= 0;
703 struct brw_compile
*p
= &c
->func
;
704 struct brw_indirect stack_index
= brw_indirect(0, 0);
706 c
->out_of_regs
= GL_FALSE
;
708 if_depth_in_loop
[loop_depth
] = 0;
711 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
712 brw_MOV(p
, get_addr_reg(stack_index
), brw_address(c
->stack
));
715 brw_set_acc_write_control(p
, 1);
717 for (i
= 0; i
< c
->nr_fp_insns
; i
++) {
718 const struct prog_instruction
*inst
= &c
->prog_instructions
[i
];
720 struct brw_reg args
[3][4], dst
[4];
722 int mark
= mark_tmps( c
);
727 printf("Inst %d: ", i
);
728 _mesa_print_instruction(inst
);
731 /* fetch any constants that this instruction needs */
732 if (c
->fp
->use_const_buffer
)
733 fetch_constants(c
, inst
);
735 if (inst
->Opcode
!= OPCODE_ARL
) {
736 for (j
= 0; j
< 4; j
++) {
737 if (inst
->DstReg
.WriteMask
& (1 << j
))
738 dst
[j
] = get_dst_reg(c
, inst
, j
);
740 dst
[j
] = brw_null_reg();
743 for (j
= 0; j
< brw_wm_nr_args(inst
->Opcode
); j
++)
744 get_argument_regs(c
, inst
, j
, dst
, args
[j
], WRITEMASK_XYZW
);
746 dst_flags
= inst
->DstReg
.WriteMask
;
747 if (inst
->SaturateMode
== SATURATE_ZERO_ONE
)
748 dst_flags
|= SATURATE
;
750 if (inst
->CondUpdate
)
751 brw_set_conditionalmod(p
, BRW_CONDITIONAL_NZ
);
753 brw_set_conditionalmod(p
, BRW_CONDITIONAL_NONE
);
755 switch (inst
->Opcode
) {
757 emit_pixel_xy(c
, dst
, dst_flags
);
760 emit_delta_xy(p
, dst
, dst_flags
, args
[0]);
763 emit_pixel_w(c
, dst
, dst_flags
, args
[0], args
[1]);
766 emit_linterp(p
, dst
, dst_flags
, args
[0], args
[1]);
769 emit_pinterp(p
, dst
, dst_flags
, args
[0], args
[1], args
[2]);
772 emit_cinterp(p
, dst
, dst_flags
, args
[0]);
775 emit_wpos_xy(c
, dst
, dst_flags
, args
[0]);
778 emit_fb_write(c
, args
[0], args
[1], args
[2],
779 INST_AUX_GET_TARGET(inst
->Aux
),
780 inst
->Aux
& INST_AUX_EOT
);
783 emit_frontfacing(p
, dst
, dst_flags
);
786 emit_alu2(p
, brw_ADD
, dst
, dst_flags
, args
[0], args
[1]);
792 emit_alu1(p
, brw_FRC
, dst
, dst_flags
, args
[0]);
795 emit_alu1(p
, brw_RNDD
, dst
, dst_flags
, args
[0]);
798 emit_lrp(p
, dst
, dst_flags
, args
[0], args
[1], args
[2]);
801 emit_alu1(p
, brw_RNDZ
, dst
, dst_flags
, args
[0]);
805 emit_alu1(p
, brw_MOV
, dst
, dst_flags
, args
[0]);
808 emit_dp2(p
, dst
, dst_flags
, args
[0], args
[1]);
811 emit_dp3(p
, dst
, dst_flags
, args
[0], args
[1]);
814 emit_dp4(p
, dst
, dst_flags
, args
[0], args
[1]);
817 emit_xpd(p
, dst
, dst_flags
, args
[0], args
[1]);
820 emit_dph(p
, dst
, dst_flags
, args
[0], args
[1]);
823 emit_math1(c
, BRW_MATH_FUNCTION_INV
, dst
, dst_flags
, args
[0]);
826 emit_math1(c
, BRW_MATH_FUNCTION_RSQ
, dst
, dst_flags
, args
[0]);
829 emit_math1(c
, BRW_MATH_FUNCTION_SIN
, dst
, dst_flags
, args
[0]);
832 emit_math1(c
, BRW_MATH_FUNCTION_COS
, dst
, dst_flags
, args
[0]);
835 emit_math1(c
, BRW_MATH_FUNCTION_EXP
, dst
, dst_flags
, args
[0]);
838 emit_math1(c
, BRW_MATH_FUNCTION_LOG
, dst
, dst_flags
, args
[0]);
841 emit_cmp(p
, dst
, dst_flags
, args
[0], args
[1], args
[2]);
844 emit_min(p
, dst
, dst_flags
, args
[0], args
[1]);
847 emit_max(p
, dst
, dst_flags
, args
[0], args
[1]);
851 emit_ddxy(p
, dst
, dst_flags
, (inst
->Opcode
== OPCODE_DDX
),
855 emit_sop(p
, dst
, dst_flags
,
856 BRW_CONDITIONAL_L
, args
[0], args
[1]);
859 emit_sop(p
, dst
, dst_flags
,
860 BRW_CONDITIONAL_LE
, args
[0], args
[1]);
863 emit_sop(p
, dst
, dst_flags
,
864 BRW_CONDITIONAL_G
, args
[0], args
[1]);
867 emit_sop(p
, dst
, dst_flags
,
868 BRW_CONDITIONAL_GE
, args
[0], args
[1]);
871 emit_sop(p
, dst
, dst_flags
,
872 BRW_CONDITIONAL_EQ
, args
[0], args
[1]);
875 emit_sop(p
, dst
, dst_flags
,
876 BRW_CONDITIONAL_NEQ
, args
[0], args
[1]);
879 emit_sign(p
, dst
, dst_flags
, args
[0]);
882 emit_alu2(p
, brw_MUL
, dst
, dst_flags
, args
[0], args
[1]);
885 emit_math2(c
, BRW_MATH_FUNCTION_POW
,
886 dst
, dst_flags
, args
[0], args
[1]);
889 emit_mad(p
, dst
, dst_flags
, args
[0], args
[1], args
[2]);
892 emit_tex(c
, dst
, dst_flags
, args
[0],
893 get_reg(c
, PROGRAM_PAYLOAD
, PAYLOAD_DEPTH
,
897 (c
->key
.shadowtex_mask
& (1 << inst
->TexSrcUnit
)) != 0);
900 emit_txb(c
, dst
, dst_flags
, args
[0],
901 get_reg(c
, PROGRAM_PAYLOAD
, PAYLOAD_DEPTH
,
904 c
->fp
->program
.Base
.SamplerUnits
[inst
->TexSrcUnit
]);
910 assert(if_depth
< MAX_IF_DEPTH
);
911 if_inst
[if_depth
++] = brw_IF(p
, BRW_EXECUTE_8
);
912 if_depth_in_loop
[loop_depth
]++;
915 assert(if_depth
> 0);
916 if_inst
[if_depth
-1] = brw_ELSE(p
, if_inst
[if_depth
-1]);
919 assert(if_depth
> 0);
920 brw_ENDIF(p
, if_inst
[--if_depth
]);
921 if_depth_in_loop
[loop_depth
]--;
924 brw_save_label(p
, inst
->Comment
, p
->nr_insn
);
930 brw_push_insn_state(p
);
931 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
932 brw_set_access_mode(p
, BRW_ALIGN_1
);
933 brw_ADD(p
, deref_1ud(stack_index
, 0), brw_ip_reg(), brw_imm_d(3*16));
934 brw_set_access_mode(p
, BRW_ALIGN_16
);
935 brw_ADD(p
, get_addr_reg(stack_index
),
936 get_addr_reg(stack_index
), brw_imm_d(4));
937 brw_save_call(&c
->func
, inst
->Comment
, p
->nr_insn
);
938 brw_ADD(p
, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
939 brw_pop_insn_state(p
);
943 brw_push_insn_state(p
);
944 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
945 brw_ADD(p
, get_addr_reg(stack_index
),
946 get_addr_reg(stack_index
), brw_imm_d(-4));
947 brw_set_access_mode(p
, BRW_ALIGN_1
);
948 brw_MOV(p
, brw_ip_reg(), deref_1ud(stack_index
, 0));
949 brw_set_access_mode(p
, BRW_ALIGN_16
);
950 brw_pop_insn_state(p
);
954 /* XXX may need to invalidate the current_constant regs */
955 loop_inst
[loop_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
956 if_depth_in_loop
[loop_depth
] = 0;
959 brw_BREAK(p
, if_depth_in_loop
[loop_depth
]);
960 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
963 brw_CONT(p
, if_depth_in_loop
[loop_depth
]);
964 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
968 struct brw_instruction
*inst0
, *inst1
;
974 assert(loop_depth
> 0);
976 inst0
= inst1
= brw_WHILE(p
, loop_inst
[loop_depth
]);
977 /* patch all the BREAK/CONT instructions from last BGNLOOP */
978 while (inst0
> loop_inst
[loop_depth
]) {
980 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
981 inst0
->bits3
.if_else
.jump_count
== 0) {
982 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
984 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
985 inst0
->bits3
.if_else
.jump_count
== 0) {
986 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
992 printf("unsupported opcode %d (%s) in fragment shader\n",
993 inst
->Opcode
, inst
->Opcode
< MAX_OPCODE
?
994 _mesa_opcode_string(inst
->Opcode
) : "unknown");
997 /* Release temporaries containing any unaliased source regs. */
998 release_tmps( c
, mark
);
1000 if (inst
->CondUpdate
)
1001 brw_set_predicate_control(p
, BRW_PREDICATE_NORMAL
);
1003 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1007 if (INTEL_DEBUG
& DEBUG_WM
) {
1008 printf("wm-native:\n");
1009 for (i
= 0; i
< p
->nr_insn
; i
++)
1010 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
1016 * Do GPU code generation for shaders that use GLSL features such as
1017 * flow control. Other shaders will be compiled with the
1019 void brw_wm_glsl_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
1021 if (INTEL_DEBUG
& DEBUG_WM
) {
1022 printf("brw_wm_glsl_emit:\n");
1025 /* initial instruction translation/simplification */
1028 /* actual code generation */
1029 brw_wm_emit_glsl(brw
, c
);
1031 if (INTEL_DEBUG
& DEBUG_WM
) {
1032 brw_wm_print_program(c
, "brw_wm_glsl_emit done");
1035 c
->prog_data
.total_grf
= num_grf_used(c
);
1036 c
->prog_data
.total_scratch
= 0;